AM243x MCU+ SDK  08.04.00
soc.h
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32 
33 #ifndef SOC_AM64X_H_
34 #define SOC_AM64X_H_
35 
36 #ifdef __cplusplus
37 extern "C"
38 {
39 #endif
40 
50 #include <drivers/sciclient.h>
51 #include <kernel/dpl/CpuIdP.h>
52 
58 #define SOC_DOMAIN_ID_MAIN (0U)
59 #define SOC_DOMAIN_ID_MCU (1U)
60 
65 #define SOC_BOOTMODE_MMCSD (0X36C3)
66 
76 int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable);
77 
88 int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate);
89 
99 int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate);
100 
108 const char *SOC_getCoreName(uint16_t coreId);
109 
115 uint64_t SOC_getSelfCpuClk(void);
116 
123 void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition);
124 
131 void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition);
132 
139 void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable);
140 
148 uint64_t SOC_virtToPhy(void *virtAddr);
149 
157 void *SOC_phyToVirt(uint64_t phyAddr);
158 
164 void SOC_setDevStat(uint32_t bootMode);
165 
174 
179 
184 
191 
196 
201 
206 
213 
222 void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause);
223 
226 #ifdef __cplusplus
227 }
228 #endif
229 
230 #endif
sciclient.h
This file contains prototypes for APIs contained as a part of SCICLIENT as well as the structures of ...
SOC_moduleSetClockFrequency
int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
Set module clock to specified frequency.
SOC_controlModuleUnlockMMR
void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition)
Unlock control module partition to allow writes into control MMRs.
SOC_virtToPhy
uint64_t SOC_virtToPhy(void *virtAddr)
SOC Virtual (CPU) to Physical address translation function.
SOC_generateSwWarmResetMainDomainFromMcuDomain
void SOC_generateSwWarmResetMainDomainFromMcuDomain(void)
Generate SW WARM Reset Main Domain from Mcu Domain.
SOC_generateSwPORResetMainDomainFromMcuDomain
void SOC_generateSwPORResetMainDomainFromMcuDomain(void)
Generate SW POR Reset Main Domain from Mcu Domain.
SOC_clearResetCauseMainMcuDomain
void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause)
Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLM...
SOC_generateSwWarmResetMcuDomain
void SOC_generateSwWarmResetMcuDomain(void)
Generate SW WARM Reset Mcu Domain.
SOC_moduleGetClockFrequency
int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate)
Get module clock frequency.
SOC_getWarmResetCauseMainDomain
uint32_t SOC_getWarmResetCauseMainDomain(void)
Get the reset reason source for Main Domain.
SOC_phyToVirt
void * SOC_phyToVirt(uint64_t phyAddr)
Physical to Virtual (CPU) address translation function.
CSL_ArmR5CPUInfo
Structure containing the CPU Info such as CPU ID and Cluster Group ID.
Definition: CpuIdP.h:57
SOC_getSelfCpuClk
uint64_t SOC_getSelfCpuClk(void)
Get the clock frequency in Hz of the CPU on which the driver is running.
SOC_generateSwWarmResetMainDomain
void SOC_generateSwWarmResetMainDomain(void)
Generate SW Warm Reset Main Domain.
SOC_generateSwPORResetMainDomain
void SOC_generateSwPORResetMainDomain(void)
Generate SW POR Reset Main Domain.
CpuIdP.h
SOC_controlModuleLockMMR
void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition)
Lock control module partition to prevent writes into control MMRs.
SOC_moduleClockEnable
int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable)
Enable clock to specified module.
SOC_setDevStat
void SOC_setDevStat(uint32_t bootMode)
Change boot mode by setting devstat register.
SOC_getCoreName
const char * SOC_getCoreName(uint16_t coreId)
Convert a core ID to a user readable name.
SOC_isR5FDualCoreMode
uint32_t SOC_isR5FDualCoreMode(CSL_ArmR5CPUInfo *cpuInfo)
Return R5SS supporting single or dual core mode.
SOC_setEpwmTbClk
void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable)
Enable or disable ePWM time base clock from Control MMR.
SOC_getWarmResetCauseMcuDomain
uint32_t SOC_getWarmResetCauseMcuDomain(void)
Get the reset reason source for Mcu Domain.
enable
@ enable
Definition: iPtcpDrv.h:69