AM243x MCU+ SDK  08.04.00
SBL OSPI Multi-Partition

Introduction

This is a bootloader example, which shows an example of booting different CPUs flashed at different offsets within the EVM flash. This allows users to update a single CPU binary without updating the other CPU binaries.

Supported Combinations

Parameter Value
CPU + OS r5fss0-0 nortos
Toolchain ti-arm-clang
Boards am243x-evm, am243x-lp
Example folder examples/drivers/boot/sbl_ospi_multi_partition

Steps to Run the Example

Build the example

  • When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects).
  • When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles)

Run the example

  • This example is the SBL which needs to be flashed on the EVM flash, along with sample application images for each CPU.
  • There is a default flash config file as shown below which flashes this SBL and the IPC Notify echo applications
      ${SDK_INSTALL_PATH}/examples/drivers/boot/sbl_ospi_multi_partition/am243x-evm/{cpu}_{os}/default_sbl_ospi_multi_partition.cfg
    
  • Make sure IPC notify echo application is built before running the flash script. (see IPC Notify Echo)
  • To flash to the EVM, refer to Flash a Hello World example . Only when giving the flash config file, point to the default_sbl_ospi_multi_partition.cfg shown above.
  • Example, assuming SDK is installed at C:/ti/mcu_plus_sdk and this example and IPC application is built using makefiles, in Windows,
      cd C:/ti/mcu_plus_sdk/tools/boot
      C:/ti/mcu_plus_sdk/tools/boot>python uart_uniflash.py -p COM13 --cfg=C:/ti/mcu_plus_sdk/examples/drivers/boot/sbl_ospi_multi_partition/am243x-evm/r5fss0-0_nortos/default_sbl_ospi_multi_partition.cfg
    

See Also

BOOTLOADER

Sample Output

After flashing and booting the EVM, you will see below output on the UART console

Starting OSPI Multi-Partition Bootloader ...

DMSC Firmware Version 21.1.1--v2021.01a (Terrific Lla
DMSC Firmware revision 0x15
DMSC ABI revision 3.1

INFO: Bootloader_runCpu:151: CPU r5f1-0  is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:151: CPU r5f1-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:151: CPU m4f0-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_loadSelfCpu2:222: CPU r5f0-0 is initialized to 800000000 Hz !!!
รพ[IPC NOTIFY ECHO] Message exchange started by main core !!! to 800000000 Hz !!!
[m4f0-0]     0.286023s : [IPC NOTIFY ECHO] Remote Core waiting for messages from main core ... !!!
[r5f0-1]     0.036024s : [IPC NOTIFY ECHO] Remote Core waiting for messages from main core ... !!!
[r5f0-1]     2.217979s : [IPC NOTIFY ECHO] Remote core has echoed all messages !!!
[r5f0-1]     2.217994s : All tests have passed!!
[r5f1-0]     0.512029s : [IPC NOTIFY ECHO] Remote Core waiting for messages from main core ... !!!
[r5f1-0]     2.693704s : [IPC NOTIFY ECHO] Remote core has echoed all messages !!!
[r5f1-0]     2.693719s : All tests have passed!!
[r5f1-1]     0.402025s : [IPC NOTIFY ECHO] Remote Core waiting for messages from main core ... !!!
[r5f1-1]     2.583249s : [IPC NOTIFY ECHO] Remote core has echoed all messages !!!
[r5f1-1]     2.583264s : All tests have passed!!
[IPC NOTIFY ECHO] All echoed messages received by main core from 4 remote cores !!!
[IPC NOTIFY ECHO] Messages sent to each core = 1000000
[IPC NOTIFY ECHO] Number of remote cores = 4
[m4f0-0]     4.280710s : [IPC NOTIFY ECHO] Remote core has echoed all messages !!!
[m4f0-0]     4.280730s : All tests have passed!!