Detailed Description

Struct for FWHAL initialization Parameters.

Data Fields
PRUICSS_Handle	pruicss_handle

int32_t	interrupt_offset

bsp_eeprom_read_t	eeprom_read

bsp_eeprom_write_t	eeprom_write

uint32_t	spinlock_base_address

bsp_ethphy_init_t	ethphy_init

uint8_t	enhancedlink_enable

uint32_t	link0_polarity

uint32_t	link1_polarity

uint32_t	phy0_address

uint32_t	phy1_address

const unsigned char *	default_tiesc_eeprom

uint8_t **	eeprom_pointer_for_stack

bsp_ethercat_stack_isr_function	pdi_isr

bsp_ethercat_stack_isr_function	sync0_isr

bsp_ethercat_stack_isr_function	sync1_isr

uint16_t	phy_rx_err_reg

uint8_t	pruicssClkFreq

Field Documentation

◆ pruicss_handle

PRUICSS_Handle bsp_params::pruicss_handle

PRUICSS Handle

◆ interrupt_offset

int32_t bsp_params::interrupt_offset

Interrupt Input Line number on ARM processor for PRU_ICSSG_PR1_HOST_INTR_PEND_0 interrupt. Out of 8 interrupts PRU_ICSSG_PR1_HOST_INTR_PEND_0 to PRU_ICSSG_PR1_HOST_INTR_PEND_7, following 4 are used for EtherCAT:
PRU_ICSSG_PR1_HOST_INTR_PEND_1 : DC SYNC0 OUT
PRU_ICSSG_PR1_HOST_INTR_PEND_2 : DC SYNC1 OUT
PRU_ICSSG_PR1_HOST_INTR_PEND_3 : PDI Interrupt
PRU_ICSSG_PR1_HOST_INTR_PEND_4 : ESC Command Acknowledgement

◆ eeprom_read

bsp_eeprom_read_t bsp_params::eeprom_read

Function pointer to EEPROM Read function

◆ eeprom_write

bsp_eeprom_write_t bsp_params::eeprom_write

Function pointer to EEPROM Read function

◆ spinlock_base_address

uint32_t bsp_params::spinlock_base_address

Base address for HW spinlock. This is needed to prevent concurrent Host/Firmware shared memory access while reading latch timestamps.

◆ ethphy_init

bsp_ethphy_init_t bsp_params::ethphy_init

Callback function for EtherCAT specific Ethernet PHY initialization

◆ enhancedlink_enable

uint8_t bsp_params::enhancedlink_enable

Enable enhanced link detection using MII RXLINK and PHY's enhanced link detection features. TIESC_MDIO_RX_LINK_ENABLE for enable, TIESC_MDIO_RX_LINK_DISABLE for disable

◆ link0_polarity

uint32_t bsp_params::link0_polarity

Link Polarity for Port 0

◆ link1_polarity

uint32_t bsp_params::link1_polarity

Link Polarity for Port 1

◆ phy0_address

uint32_t bsp_params::phy0_address

Ethernet PHY Address for Port 0

◆ phy1_address

uint32_t bsp_params::phy1_address

Ethernet PHY Address for Port 1

◆ default_tiesc_eeprom

const unsigned char* bsp_params::default_tiesc_eeprom

Pointer to EEPROM array corresponding to ESI XML

◆ eeprom_pointer_for_stack

uint8_t** bsp_params::eeprom_pointer_for_stack

Double pointer to eeprom variable which will be used by stack. bsp_init will populate this pointer appropriately

◆ pdi_isr

bsp_ethercat_stack_isr_function bsp_params::pdi_isr

PDI IRQ handler in the EtherCAT slave stack. Needed only if ENABLE_PDI_TASK is not enabled

◆ sync0_isr

bsp_ethercat_stack_isr_function bsp_params::sync0_isr

SYNC0 IRQ handler in the EtherCAT slave stack. Needed only if ENABLE_SYNC_TASK is not enabled

◆ sync1_isr

bsp_ethercat_stack_isr_function bsp_params::sync1_isr

SYNC1 IRQ handler in the EtherCAT slave stack. Needed only if ENABLE_SYNC_TASK is not enabled

◆ phy_rx_err_reg

uint16_t bsp_params::phy_rx_err_reg

Address of PHY register maintaining RX Error (RX_ERR) count during frame(when RX_DV is asserted). This value will be configured in TI ESC's PHY RX Error Counter Register (0x0E28-0x0E29)

◆ pruicssClkFreq

uint8_t bsp_params::pruicssClkFreq

PRU-ICSS Core Clock and IEP Clock Frequency. Set TIESC_PRUICSS_CLOCK_FREQUENCY_200_MHZ/TIESC_PRUICSS_CLOCK_FREQUENCY_333_MHZ. Default is TIESC_PRUICSS_CLOCK_FREQUENCY_200_MHZ. NOTE : Only applicable for PRU-ICSSG (AM64x/AM243x). Not applicable for PRU-ICSSM(AM263x).