AM243x MCU+ SDK  08.03.00
APIs for SOC Specific Functions

Introduction

For more details and example usage, see SOC

Functions

int32_t SOC_moduleClockEnable (uint32_t moduleId, uint32_t enable)
 Enable clock to specified module. More...
 
int32_t SOC_moduleSetClockFrequency (uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
 Set module clock to specified frequency. More...
 
int32_t SOC_moduleGetClockFrequency (uint32_t moduleId, uint32_t clkId, uint64_t *clkRate)
 Get module clock frequency. More...
 
const char * SOC_getCoreName (uint16_t coreId)
 Convert a core ID to a user readable name. More...
 
uint64_t SOC_getSelfCpuClk (void)
 Get the clock frequency in Hz of the CPU on which the driver is running. More...
 
void SOC_controlModuleLockMMR (uint32_t domainId, uint32_t partition)
 Lock control module partition to prevent writes into control MMRs. More...
 
void SOC_controlModuleUnlockMMR (uint32_t domainId, uint32_t partition)
 Unlock control module partition to allow writes into control MMRs. More...
 
void SOC_setEpwmTbClk (uint32_t epwmInstance, uint32_t enable)
 Enable or disable ePWM time base clock from Control MMR. More...
 
uint64_t SOC_virtToPhy (void *virtAddr)
 SOC Virtual (CPU) to Physical address translation function. More...
 
void * SOC_phyToVirt (uint64_t phyAddr)
 Physical to Virtual (CPU) address translation function. More...
 
void SOC_setDevStat (uint32_t bootMode)
 Change boot mode by setting devstat register. More...
 
uint32_t SOC_isR5FDualCoreMode (CSL_ArmR5CPUInfo *cpuInfo)
 Return R5SS supporting single or dual core mode. More...
 
void SOC_generateSwWarmResetMainDomain (void)
 Generate SW Warm Reset Main Domain. More...
 
void SOC_generateSwPORResetMainDomain (void)
 Generate SW POR Reset Main Domain. More...
 
uint32_t SOC_getWarmResetCauseMainDomain (void)
 Get the reset reason source for Main Domain. More...
 
void SOC_generateSwWarmResetMcuDomain (void)
 Generate SW WARM Reset Mcu Domain. More...
 
void SOC_generateSwWarmResetMainDomainFromMcuDomain (void)
 Generate SW WARM Reset Main Domain from Mcu Domain. More...
 
void SOC_generateSwPORResetMainDomainFromMcuDomain (void)
 Generate SW POR Reset Main Domain from Mcu Domain. More...
 
uint32_t SOC_getWarmResetCauseMcuDomain (void)
 Get the reset reason source for Mcu Domain. More...
 
void SOC_clearResetCauseMainMcuDomain (uint32_t resetCause)
 Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLMMR_MCU_RST_SRC register. It is read only. So we need to write 1 to CTRLMMR_MCU_RST_SRC to clear the reset reason. More...
 

Macros

#define SOC_BOOTMODE_MMCSD   (0X36C3)
 Switch value for SD card boot mode. More...
 

SOC Domain ID

#define SOC_DOMAIN_ID_MAIN   (0U)
 
#define SOC_DOMAIN_ID_MCU   (1U)
 

Macro Definition Documentation

◆ SOC_DOMAIN_ID_MAIN

#define SOC_DOMAIN_ID_MAIN   (0U)

◆ SOC_DOMAIN_ID_MCU

#define SOC_DOMAIN_ID_MCU   (1U)

◆ SOC_BOOTMODE_MMCSD

#define SOC_BOOTMODE_MMCSD   (0X36C3)

Switch value for SD card boot mode.

Function Documentation

◆ SOC_moduleClockEnable()

int32_t SOC_moduleClockEnable ( uint32_t  moduleId,
uint32_t  enable 
)

Enable clock to specified module.

Parameters
moduleId[in] see tisci_devices for list of device ID's
enable[in] 1: enable clock to the module, 0: disable clock to the module
Returns
SystemP_SUCCESS Module clock is enabled
SystemP_FAILURE Module clock could not be enabled

◆ SOC_moduleSetClockFrequency()

int32_t SOC_moduleSetClockFrequency ( uint32_t  moduleId,
uint32_t  clkId,
uint64_t  clkRate 
)

Set module clock to specified frequency.

Parameters
moduleId[in] see tisci_devices for list of module ID's
clkId[in] see tisci_clocks for list of clocks associated with the specified module ID
clkRate[in] Frequency to set in Hz
Returns
SystemP_SUCCESS Module clock is enabled
SystemP_FAILURE Module clock could not be enabled

◆ SOC_moduleGetClockFrequency()

int32_t SOC_moduleGetClockFrequency ( uint32_t  moduleId,
uint32_t  clkId,
uint64_t *  clkRate 
)

Get module clock frequency.

Parameters
moduleId[in] see tisci_devices for list of module ID's
clkId[in] see tisci_clocks for list of clocks associated with the specified module ID
clkRate[out] Frequency of the clock
Returns
SystemP_SUCCESS on success, else failure

◆ SOC_getCoreName()

const char* SOC_getCoreName ( uint16_t  coreId)

Convert a core ID to a user readable name.

Parameters
coreId[in] see CSL_CoreID
Returns
name as a string

◆ SOC_getSelfCpuClk()

uint64_t SOC_getSelfCpuClk ( void  )

Get the clock frequency in Hz of the CPU on which the driver is running.

Returns
Clock frequency in Hz

◆ SOC_controlModuleLockMMR()

void SOC_controlModuleLockMMR ( uint32_t  domainId,
uint32_t  partition 
)

Lock control module partition to prevent writes into control MMRs.

Parameters
domainId[in] See SOC_DomainId_t
partition[in] Partition number to unlock

◆ SOC_controlModuleUnlockMMR()

void SOC_controlModuleUnlockMMR ( uint32_t  domainId,
uint32_t  partition 
)

Unlock control module partition to allow writes into control MMRs.

Parameters
domainId[in] See SOC_DomainId_t
partition[in] Partition number to unlock

◆ SOC_setEpwmTbClk()

void SOC_setEpwmTbClk ( uint32_t  epwmInstance,
uint32_t  enable 
)

Enable or disable ePWM time base clock from Control MMR.

Parameters
epwmInstance[in] ePWM instance number [0 - (CSL_EPWM_PER_CNT-1)]
enable[in] TRUE to enable and FALSE to disable

◆ SOC_virtToPhy()

uint64_t SOC_virtToPhy ( void *  virtAddr)

SOC Virtual (CPU) to Physical address translation function.

Parameters
virtAddr[IN] Virtual/CPU address
Returns
Corresponding SOC physical address

◆ SOC_phyToVirt()

void* SOC_phyToVirt ( uint64_t  phyAddr)

Physical to Virtual (CPU) address translation function.

Parameters
phyAddr[IN] Physical address
Returns
Corresponding virtual/CPU address

◆ SOC_setDevStat()

void SOC_setDevStat ( uint32_t  bootMode)

Change boot mode by setting devstat register.

Parameters
bootMode[IN] Boot mode switch value

◆ SOC_isR5FDualCoreMode()

uint32_t SOC_isR5FDualCoreMode ( CSL_ArmR5CPUInfo cpuInfo)

Return R5SS supporting single or dual core mode.

Parameters
cpuInfo[IN] Pointer to the CSL_ArmR5CPUInfo struct.
Returns
TRUE if it is Dual Core mode else FALSE.

◆ SOC_generateSwWarmResetMainDomain()

void SOC_generateSwWarmResetMainDomain ( void  )

Generate SW Warm Reset Main Domain.

◆ SOC_generateSwPORResetMainDomain()

void SOC_generateSwPORResetMainDomain ( void  )

Generate SW POR Reset Main Domain.

◆ SOC_getWarmResetCauseMainDomain()

uint32_t SOC_getWarmResetCauseMainDomain ( void  )

Get the reset reason source for Main Domain.

Returns
Reset Reason Source Main Domain

◆ SOC_generateSwWarmResetMcuDomain()

void SOC_generateSwWarmResetMcuDomain ( void  )

Generate SW WARM Reset Mcu Domain.

◆ SOC_generateSwWarmResetMainDomainFromMcuDomain()

void SOC_generateSwWarmResetMainDomainFromMcuDomain ( void  )

Generate SW WARM Reset Main Domain from Mcu Domain.

◆ SOC_generateSwPORResetMainDomainFromMcuDomain()

void SOC_generateSwPORResetMainDomainFromMcuDomain ( void  )

Generate SW POR Reset Main Domain from Mcu Domain.

◆ SOC_getWarmResetCauseMcuDomain()

uint32_t SOC_getWarmResetCauseMcuDomain ( void  )

Get the reset reason source for Mcu Domain.

Returns
Reset Reason Source Mcu Domain

◆ SOC_clearResetCauseMainMcuDomain()

void SOC_clearResetCauseMainMcuDomain ( uint32_t  resetCause)

Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLMMR_MCU_RST_SRC register. It is read only. So we need to write 1 to CTRLMMR_MCU_RST_SRC to clear the reset reason.

Parameters
resetCause[IN] Reset reason value to clear.