Features Supported

Note: PCIe makes use of 2 Ring Accelerators (Rings for IPC), one each for MSI and MSIx to route interrupts to the core.; The actual index for the Ring Accelerator, Global Event and Virtual Interrupt is depended on the Board Config for the soc and core.

EP and RC operation
Gen 2 operation speed
x1 lane support
Legacy interrupts
MSI (Message Signalled Interrupt)
MSIx (Message Signalled Interrupt Extended)

SysConfig Features

Note: It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig can be used to configure below parameters apart from common configuration like Clock,MPU,RAT and others.

PCIe operation mode - Root complex (RC) or End point (EP)
PCIe instances
Operation speed (Gen1, Gen2 or Gen3)
Number of lanes
Inbound Address Translation Unit (ATU) configuration
Outbound Address Translation Unit (ATU) configuration

Features NOT supported

Bridge mode of operation
Bus enumeration
x2 and x4 lanes

Usage Overview

Initializing PCIe driver

Pcie_init() must be called before any other PCIe APIs. This function iterates through the elements of the gPcieConfig[] array, initializing the driver. Please note that initializing of PCIe driver is taken care by the SysConfig generated code.

Opening PCIe driver

After initializing the driver by calling Pcie_init(), the application can open a PCIe instance by calling Pcie_open(). Please note that the opening of PCIe driver is taken care by the SysConfig generated code. This function takes and index into the gPcieConfig[] array, and the PCIe parameters data structure. The PCIe instance is specified by the index of the PCIe in the gPcieConfig[]. Calling Pcie_open() second time with same index, previously passed to Pcie_open() will result in an error.

Important Usage Guidelines

Care must be taken so that the ATU address regions does not overlap. The ATU configuration can be done using SysConfig.
The zeroth Outbound ATU region for RC device is used for configuration space access of the remote EP.

Example Usage

Include the below file to access the APIs

#include <drivers/pcie.h>

Instance open Example

gPcieHandle = Pcie_open(CONFIG_PCIE0);

DebugP_assert(gPcieHandle != NULL);

Instance close Example

Pcie_close(gPcieHandle);

Outbound ATU config Example

    int32_t status;
    Pcie_AtuRegionParams regionParams;
    uint32_t regionIndex = 1;
 
    regionParams.regionDir = PCIE_ATU_REGION_DIR_OUTBOUND;
    regionParams.tlpType   = PCIE_TLP_TYPE_MEM;
 
    regionParams.lowerBaseAddr    = 0x68000000UL + 0x01000000U;
    regionParams.upperBaseAddr    = 0x0;
 
    regionParams.regionWindowSize = 0xFFFU;
 
    regionParams.lowerTargetAddr    = 0x70000000U;
    regionParams.upperTargetAddr    = 0x0U;
 
    status = Pcie_atuRegionConfig (gPcieHandle, PCIE_LOCATION_LOCAL, regionIndex, &regionParams);
 
    DebugP_assert(SystemP_SUCCESS == status);
 

Inbound ATU config Example

    int32_t status;
    Pcie_AtuRegionParams regionParams;
    uint32_t regionIndex = 1;
 
    regionParams.regionDir = PCIE_ATU_REGION_DIR_INBOUND;
    regionParams.tlpType   = PCIE_TLP_TYPE_MEM;
 
    regionParams.lowerBaseAddr    = 0x90000000U;
    regionParams.upperBaseAddr    = 0x0;
 
    regionParams.regionWindowSize = 0xFFFU;
 
    regionParams.lowerTargetAddr    = (uint32_t)dst_buf;
    regionParams.upperTargetAddr    = 0x0U;
 
    status = Pcie_atuRegionConfig (gPcieHandle, PCIE_LOCATION_LOCAL, regionIndex, &regionParams);
 
    DebugP_assert(SystemP_SUCCESS == status);

BAR Configuration for EP Example

    Pcie_BarCfg barCfg;
    int32_t status;
    uint32_t regionIndex = 0;
 
    barCfg.location = PCIE_LOCATION_LOCAL;
    barCfg.mode     = PCIE_EP_MODE;
    barCfg.barxc    = PCIE_BARC_32B_MEM_BAR_NON_PREFETCH;
    barCfg.barxa    = PCIE_RCBARA_4K;
    barCfg.idx      = regionIndex;
 
    status = Pcie_cfgBar (object->handle, &barCfg);
 
    DebugP_assert(SystemP_SUCCESS == status);
 

API

APIs for PCIE

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