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AM243x MCU+ SDK
08.02.00
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54 #ifndef RM_TISCI_UDMAP_H
55 #define RM_TISCI_UDMAP_H
64 #define TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID ((uint32_t) 1u << 0u)
69 #define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID ((uint32_t) 1u << 1u)
74 #define TISCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID ((uint32_t) 1u << 2u)
79 #define TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID ((uint32_t) 1u << 3u)
84 #define TISCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID ((uint32_t) 1u << 4u)
89 #define TISCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID ((uint32_t) 1u << 5u)
94 #define TISCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID ((uint32_t) 1u << 6u)
99 #define TISCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID ((uint32_t) 1u << 7u)
104 #define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID ((uint32_t) 1u << 8u)
109 #define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID ((uint32_t) 1u << 14U)
113 #define TISCI_MSG_VALUE_RM_UDMAP_EXTENDED_CH_TYPE_VALID ((uint32_t) 1u << 16U)
118 #define TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED (0u)
123 #define TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_ENABLED (1u)
130 #define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS (0u)
137 #define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_INTERMEDIATE (1u)
144 #define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VIRTUAL (2u)
151 #define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_NON_COHERENT (3U)
159 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET (2u)
169 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET_SINGLE_BUF (3u)
176 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF (10u)
183 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_VAL (11u)
190 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF (12u)
197 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_VAL (13u)
204 #define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH (0u)
210 #define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH (1u)
216 #define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDLOW (2u)
222 #define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_LOW (3u)
228 #define TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_MAX (127u)
232 #define TISCI_MSG_VALUE_RM_UDMAP_QNUM_SUPPRESS (0xFFFFu)
237 #define TISCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_MAX (7u)
242 #define TISCI_MSG_VALUE_RM_UDMAP_CH_QOS_MAX (7u)
247 #define TISCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_MAX (15u)
254 #define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES (1U)
260 #define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES (2U)
266 #define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_256_BYTES (3U)
274 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID ((uint32_t) 1U << 9U)
279 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID ((uint32_t) 1U << 10U)
284 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID ((uint32_t) 1U << 11U)
289 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID ((uint32_t) 1U << 12U)
294 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID ((uint32_t) 1U << 13U)
299 #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID ((uint32_t) 1U << 15U)
305 #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_DISABLED (0u)
310 #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_ENABLED (1u)
315 #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_DISABLED (0u)
320 #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_ENABLED (1u)
324 #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED (0u)
328 #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_ENABLED (1u)
333 #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_CREDIT_CNT_MAX (7u)
338 #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_TDTYPE_IMMEDIATE (0U)
343 #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_TDTYPE_WAIT (1U)
351 #define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID ((uint32_t) 1u << 9u)
356 #define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID ((uint32_t) 1u << 10u)
361 #define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID ((uint32_t) 1u << 11u)
366 #define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID ((uint32_t) 1u << 12u)
374 #define TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION (0u)
381 #define TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_IGNORED (1u)
387 #define TISCI_MSG_VALUE_RM_UDMAP_RX_CH_FLOW_CNT_NONE (0u)
395 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID ((uint32_t) 1u << 0u)
400 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID ((uint32_t) 1u << 1u)
405 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID ((uint32_t) 1u << 2u)
410 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID ((uint32_t) 1u << 3u)
415 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID ((uint32_t) 1u << 4u)
420 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID ((uint32_t) 1u << 5u)
425 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID ((uint32_t) 1u << 6u)
430 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID ((uint32_t) 1u << 7u)
435 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID ((uint32_t) 1u << 8u)
440 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID ((uint32_t) 1u << 9u)
445 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID ((uint32_t) 1u << 10u)
450 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID ((uint32_t) 1u << 11u)
455 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID ((uint32_t) 1u << 12u)
460 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID ((uint32_t) 1u << 13u)
465 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID ((uint32_t) 1u << 14u)
470 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID ((uint32_t) 1u << 15u)
475 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID ((uint32_t) 1u << 16u)
480 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID ((uint32_t) 1u << 17u)
485 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID ((uint32_t) 1u << 18u)
491 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH0_VALID ((uint32_t) 1u << 0u)
496 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH1_VALID ((uint32_t) 1u << 1u)
501 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH2_VALID ((uint32_t) 1u << 2u)
506 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ1_QNUM_VALID ((uint32_t) 1u << 3u)
511 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ2_QNUM_VALID ((uint32_t) 1u << 4u)
516 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ3_QNUM_VALID ((uint32_t) 1u << 5u)
521 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH_EN_VALID ((uint32_t) 1u << 6u)
528 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_EINFO_NOT_PRESENT (0u)
534 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_EINFO_PRESENT (1u)
540 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PSINFO_NOT_PRESENT (0u)
546 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PSINFO_PRESENT (1u)
551 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_ERR_DROP (0u)
556 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_ERR_RETRY (1u)
562 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PS_END_PD (0u)
568 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PS_BEGIN_DB (1u)
574 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DESC_HOST (0u)
579 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DESC_MONO (2u)
586 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_NONE (0u)
595 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_CFG_TAG (1u)
602 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_FLOW_ID (2u)
609 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_SRC_TAG (4u)
616 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_NONE (0u)
624 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_CFG_TAG (1u)
631 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_FLOW_ID (2u)
638 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_DEST_TAG_LO (4u)
645 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_DEST_TAG_HI (5u)
650 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SOP_MAX (255u)
655 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_0_ENABLE (1U)
660 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_1_ENABLE (2U)
665 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_2_ENABLE (4U)
670 #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_MAX (7u)
678 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DELEGATE_HOST_VALID ((uint32_t) 1U << 0U)
682 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DELEGATE_CLEAR_VALID ((uint32_t) 1U << 1U)
688 #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DELEGATE_CLEAR (1U)
696 #define TISCI_MSG_VALUE_RM_UDMAP_GCFG_PERF_CTRL_VALID ((uint32_t) 1U << 0U)
701 #define TISCI_MSG_VALUE_RM_UDMAP_GCFG_EMU_CTRL_VALID ((uint32_t) 1U << 1U)
706 #define TISCI_MSG_VALUE_RM_UDMAP_GCFG_PSIL_TO_VALID ((uint32_t) 1U << 2U)
711 #define TISCI_MSG_VALUE_RM_UDMAP_GCFG_RFLOWFWSTAT_VALID ((uint32_t) 1U << 3U)
Configures a Navigator Subsystem UDMAP transmit channel.
Definition: tisci_rm_udmap.h:1006
uint16_t nav_id
Definition: tisci_rm_udmap.h:1556
uint16_t rx_fdq0_sz1_qnum
Definition: tisci_rm_udmap.h:1722
uint16_t flowid_cnt
Definition: tisci_rm_udmap.h:1250
uint8_t rx_qos
Definition: tisci_rm_udmap.h:1246
uint8_t rx_ignore_short
Definition: tisci_rm_udmap.h:1254
uint16_t nav_id
Definition: tisci_rm_udmap.h:765
Response to configuring a UDMAP transmit channel.
Definition: tisci_rm_udmap.h:1036
uint16_t rx_size_thresh1
Definition: tisci_rm_udmap.h:1720
struct tisci_header hdr
Definition: tisci_rm_udmap.h:779
uint16_t rx_size_thresh2
Definition: tisci_rm_udmap.h:1721
uint16_t rx_size_thresh0
Definition: tisci_rm_udmap.h:1719
uint8_t rx_psinfo_present
Definition: tisci_rm_udmap.h:1559
uint8_t tx_filt_einfo
Definition: tisci_rm_udmap.h:1012
struct tisci_header hdr
Definition: tisci_rm_udmap.h:1037
uint8_t rx_ps_location
Definition: tisci_rm_udmap.h:1576
uint8_t rx_pause_on_err
Definition: tisci_rm_udmap.h:1251
struct tisci_header hdr
Definition: tisci_rm_udmap.h:1239
uint16_t flowid_start
Definition: tisci_rm_udmap.h:1249
uint32_t psil_to
Definition: tisci_rm_udmap.h:768
uint32_t valid_params
Definition: tisci_rm_udmap.h:1240
uint8_t tx_orderid
Definition: tisci_rm_udmap.h:1022
struct tisci_header hdr
Definition: tisci_rm_udmap.h:1586
uint32_t valid_params
Definition: tisci_rm_udmap.h:1008
uint16_t index
Definition: tisci_rm_udmap.h:1010
Response to configuring a UDMAP receive channel.
Definition: tisci_rm_udmap.h:1265
uint16_t dev_id
Definition: tisci_rm_udmap.h:1777
uint8_t tx_atype
Definition: tisci_rm_udmap.h:1014
uint16_t tx_fetch_size
Definition: tisci_rm_udmap.h:1017
uint32_t valid_params
Definition: tisci_rm_udmap.h:764
struct tisci_header hdr
Definition: tisci_rm_udmap.h:1715
Response to delegating a flow to another host for configuration.
Definition: tisci_rm_udmap.h:1789
uint16_t rx_fdq0_sz3_qnum
Definition: tisci_rm_udmap.h:1724
uint16_t nav_id
Definition: tisci_rm_udmap.h:1009
Delegates the specified flow to another host for configuration. Only the original owner of the flow,...
Definition: tisci_rm_udmap.h:1774
struct tisci_header hdr
Definition: tisci_rm_udmap.h:763
uint8_t tx_tdtype
Definition: tisci_rm_udmap.h:1026
uint16_t nav_id
Definition: tisci_rm_udmap.h:1717
uint8_t rx_burst_size
Definition: tisci_rm_udmap.h:1256
uint32_t rflowfwstat
Definition: tisci_rm_udmap.h:769
uint16_t rxcq_qnum
Definition: tisci_rm_udmap.h:1244
uint8_t rx_chan_type
Definition: tisci_rm_udmap.h:1253
uint8_t rx_src_tag_hi
Definition: tisci_rm_udmap.h:1564
uint8_t rx_dest_tag_lo
Definition: tisci_rm_udmap.h:1567
uint16_t flow_index
Definition: tisci_rm_udmap.h:1557
uint8_t rx_priority
Definition: tisci_rm_udmap.h:1245
uint8_t rx_src_tag_lo
Definition: tisci_rm_udmap.h:1565
uint8_t tx_priority
Definition: tisci_rm_udmap.h:1020
uint8_t tx_supr_tdpkt
Definition: tisci_rm_udmap.h:1016
uint16_t rx_fdq0_sz2_qnum
Definition: tisci_rm_udmap.h:1723
uint8_t rx_dest_tag_lo_sel
Definition: tisci_rm_udmap.h:1571
struct tisci_header hdr
Definition: tisci_rm_udmap.h:1554
uint16_t txcq_qnum
Definition: tisci_rm_udmap.h:1019
Configures a Navigator Subsystem UDMAP receive flow.
Definition: tisci_rm_udmap.h:1553
uint8_t rx_src_tag_hi_sel
Definition: tisci_rm_udmap.h:1568
uint8_t tx_chan_type
Definition: tisci_rm_udmap.h:1015
uint8_t tx_sched_priority
Definition: tisci_rm_udmap.h:1024
uint32_t perf_ctrl
Definition: tisci_rm_udmap.h:766
uint16_t rx_sop_offset
Definition: tisci_rm_udmap.h:1562
uint8_t delegated_host
Definition: tisci_rm_udmap.h:1779
uint16_t rx_fetch_size
Definition: tisci_rm_udmap.h:1243
uint8_t tx_pause_on_err
Definition: tisci_rm_udmap.h:1011
uint8_t rx_dest_tag_hi_sel
Definition: tisci_rm_udmap.h:1570
uint8_t tx_filt_pswords
Definition: tisci_rm_udmap.h:1013
Response to configuring a Navigator Subsystem UDMAP receive flow's size threshold fields.
Definition: tisci_rm_udmap.h:1735
uint8_t rx_dest_tag_hi
Definition: tisci_rm_udmap.h:1566
Configures a Navigator Subsystem UDMAP receive flow's size threshold fields.
Definition: tisci_rm_udmap.h:1714
uint32_t valid_params
Definition: tisci_rm_udmap.h:1555
uint8_t rx_einfo_present
Definition: tisci_rm_udmap.h:1558
struct tisci_header hdr
Definition: tisci_rm_udmap.h:1790
uint32_t valid_params
Definition: tisci_rm_udmap.h:1716
struct tisci_header hdr
Definition: tisci_rm_udmap.h:1736
uint8_t rx_sched_priority
Definition: tisci_rm_udmap.h:1248
uint8_t tx_burst_size
Definition: tisci_rm_udmap.h:1025
struct tisci_msg_rm_udmap_gcfg_cfg_req __attribute__((__packed__))
uint16_t fdepth
Definition: tisci_rm_udmap.h:1023
uint8_t rx_orderid
Definition: tisci_rm_udmap.h:1247
uint16_t rx_fdq1_qnum
Definition: tisci_rm_udmap.h:1573
uint16_t index
Definition: tisci_rm_udmap.h:1242
uint8_t rx_size_thresh_en
Definition: tisci_rm_udmap.h:1725
uint16_t flow_index
Definition: tisci_rm_udmap.h:1778
struct tisci_header hdr
Definition: tisci_rm_udmap.h:1266
uint8_t clear
Definition: tisci_rm_udmap.h:1780
uint16_t rx_fdq0_sz0_qnum
Definition: tisci_rm_udmap.h:1572
uint8_t extended_ch_type
Definition: tisci_rm_udmap.h:1027
uint8_t rx_atype
Definition: tisci_rm_udmap.h:1252
struct tisci_header hdr
Definition: tisci_rm_udmap.h:1775
uint16_t rx_fdq3_qnum
Definition: tisci_rm_udmap.h:1575
Response to configuring a Navigator Subsystem UDMAP receive flow.
Definition: tisci_rm_udmap.h:1585
uint32_t emu_ctrl
Definition: tisci_rm_udmap.h:767
Configures a Navigator Subsystem UDMAP global configuration region. Configures the non-real-time regi...
Definition: tisci_rm_udmap.h:762
uint8_t rx_desc_type
Definition: tisci_rm_udmap.h:1561
uint16_t rx_dest_qnum
Definition: tisci_rm_udmap.h:1563
uint8_t tx_qos
Definition: tisci_rm_udmap.h:1021
uint8_t rx_ignore_long
Definition: tisci_rm_udmap.h:1255
uint16_t flow_index
Definition: tisci_rm_udmap.h:1718
uint8_t rx_error_handling
Definition: tisci_rm_udmap.h:1560
struct tisci_header hdr
Definition: tisci_rm_udmap.h:1007
uint16_t rx_fdq2_qnum
Definition: tisci_rm_udmap.h:1574
Configures a Navigator Subsystem UDMAP receive channel.
Definition: tisci_rm_udmap.h:1238
uint8_t rx_src_tag_lo_sel
Definition: tisci_rm_udmap.h:1569
uint32_t valid_params
Definition: tisci_rm_udmap.h:1776
uint16_t nav_id
Definition: tisci_rm_udmap.h:1241
uint8_t tx_credit_count
Definition: tisci_rm_udmap.h:1018
Response to configuring UDMAP global configuration.
Definition: tisci_rm_udmap.h:778