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AM243x MCU+ SDK
08.01.00
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61 #include <drivers/hw_include/csl_types.h>
62 #include <drivers/hw_include/cslr_mcspi.h>
63 #include <drivers/hw_include/cslr.h>
85 #define MCSPI_CHANNEL_0 (0U)
86 #define MCSPI_CHANNEL_1 (1U)
87 #define MCSPI_CHANNEL_2 (2U)
88 #define MCSPI_CHANNEL_3 (3U)
92 #define MCSPI_MAX_NUM_CHANNELS (4U)
102 #define MCSPI_TRANSFER_COMPLETED (0U)
103 #define MCSPI_TRANSFER_STARTED (1U)
104 #define MCSPI_TRANSFER_CANCELLED (2U)
105 #define MCSPI_TRANSFER_FAILED (3U)
106 #define MCSPI_TRANSFER_CSN_DEASSERT (4U)
107 #define MCSPI_TRANSFER_TIMEOUT (5U)
129 #define MCSPI_TRANSFER_MODE_BLOCKING (0U)
134 #define MCSPI_TRANSFER_MODE_CALLBACK (1U)
153 #define MCSPI_MS_MODE_MASTER (CSL_MCSPI_MODULCTRL_MS_MASTER)
155 #define MCSPI_MS_MODE_SLAVE (CSL_MCSPI_MODULCTRL_MS_SLAVE)
172 #define MCSPI_FF_POL0_PHA0 (0U)
173 #define MCSPI_FF_POL0_PHA1 (1U)
174 #define MCSPI_FF_POL1_PHA0 (2U)
175 #define MCSPI_FF_POL1_PHA1 (3U)
187 #define MCSPI_CS_POL_HIGH (CSL_MCSPI_CH0CONF_EPOL_ACTIVEHIGH)
189 #define MCSPI_CS_POL_LOW (CSL_MCSPI_CH0CONF_EPOL_ACTIVELOW)
198 #define MCSPI_TR_MODE_TX_RX (CSL_MCSPI_CH0CONF_TRM_TRANSRECEI)
199 #define MCSPI_TR_MODE_RX_ONLY (CSL_MCSPI_CH0CONF_TRM_RECEIVONLY)
200 #define MCSPI_TR_MODE_TX_ONLY (CSL_MCSPI_CH0CONF_TRM_TRANSONLY)
210 #define MCSPI_IS_D0 (CSL_MCSPI_CH0CONF_IS_LINE0)
212 #define MCSPI_IS_D1 (CSL_MCSPI_CH0CONF_IS_LINE1)
222 #define MCSPI_DPE_ENABLE (CSL_MCSPI_CH0CONF_DPE0_ENABLED)
224 #define MCSPI_DPE_DISABLE (CSL_MCSPI_CH0CONF_DPE0_DISABLED)
233 #define MCSPI_SLV_CS_SELECT_0 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN0)
234 #define MCSPI_SLV_CS_SELECT_1 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN1)
235 #define MCSPI_SLV_CS_SELECT_2 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN2)
236 #define MCSPI_SLV_CS_SELECT_3 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN3)
246 #define MCSPI_SB_POL_HIGH (CSL_MCSPI_CH0CONF_SBPOL_HIGHLEVEL)
248 #define MCSPI_SB_POL_LOW (CSL_MCSPI_CH0CONF_SBPOL_LOWLEVEL)
260 #define MCSPI_TCS0_0_CLK (CSL_MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY)
262 #define MCSPI_TCS0_1_CLK (CSL_MCSPI_CH0CONF_TCS0_ONECYCLEDLY)
264 #define MCSPI_TCS0_2_CLK (CSL_MCSPI_CH0CONF_TCS0_TWOCYCLEDLY)
266 #define MCSPI_TCS0_3_CLK (CSL_MCSPI_CH0CONF_TCS0_THREECYCLEDLY)
279 #define MCSPI_CH_MODE_SINGLE (CSL_MCSPI_MODULCTRL_SINGLE_SINGLE)
281 #define MCSPI_CH_MODE_MULTI (CSL_MCSPI_MODULCTRL_SINGLE_MULTI)
294 #define MCSPI_PINMODE_3PIN (CSL_MCSPI_MODULCTRL_PIN34_3PINMODE)
295 #define MCSPI_PINMODE_4PIN (CSL_MCSPI_MODULCTRL_PIN34_4PINMODE)
307 #define MCSPI_INITDLY_0 (CSL_MCSPI_MODULCTRL_INITDLY_NODELAY)
309 #define MCSPI_INITDLY_4 (CSL_MCSPI_MODULCTRL_INITDLY_4CLKDLY)
311 #define MCSPI_INITDLY_8 (CSL_MCSPI_MODULCTRL_INITDLY_8CLKDLY)
313 #define MCSPI_INITDLY_16 (CSL_MCSPI_MODULCTRL_INITDLY_16CLKDLY)
315 #define MCSPI_INITDLY_32 (CSL_MCSPI_MODULCTRL_INITDLY_32CLKDLY)
772 #define MCSPI_FIFO_LENGTH (64U)
776 #define MCSPI_RX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFENABLED \
778 CSL_MCSPI_CH0CONF_FFER_SHIFT)
783 #define MCSPI_RX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFDISABLED \
784 << CSL_MCSPI_CH0CONF_FFER_SHIFT)
789 #define MCSPI_TX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFENABLED \
790 << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
795 #define MCSPI_TX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFDISABLED \
796 << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
801 #define MCSPI_REG_OFFSET (0x14U)
803 #define MCSPI_CHCONF(x) ((uint32_t) CSL_MCSPI_CH0CONF + \
804 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
807 #define MCSPI_CHSTAT(x) ((uint32_t) CSL_MCSPI_CH0STAT + \
808 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
811 #define MCSPI_CHCTRL(x) ((uint32_t) CSL_MCSPI_CH0CTRL + \
812 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
815 #define MCSPI_CHTX(x) ((uint32_t) CSL_MCSPI_TX0 + \
816 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
819 #define MCSPI_CHRX(x) ((uint32_t) CSL_MCSPI_RX0 + \
820 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
823 #define MCSPI_CLKD_MASK (0x0FU)
826 #define MCSPI_IRQSTATUS_CLEAR_ALL (CSL_MCSPI_IRQSTATUS_EOW_MASK | \
827 CSL_MCSPI_IRQSTATUS_WKS_MASK | \
828 CSL_MCSPI_IRQSTATUS_RX3_FULL_MASK | \
829 CSL_MCSPI_IRQSTATUS_TX3_UNDERFLOW_MASK | \
830 CSL_MCSPI_IRQSTATUS_TX3_EMPTY_MASK | \
831 CSL_MCSPI_IRQSTATUS_RX2_FULL_MASK | \
832 CSL_MCSPI_IRQSTATUS_TX2_UNDERFLOW_MASK | \
833 CSL_MCSPI_IRQSTATUS_TX2_EMPTY_MASK | \
834 CSL_MCSPI_IRQSTATUS_RX1_FULL_MASK | \
835 CSL_MCSPI_IRQSTATUS_TX1_UNDERFLOW_MASK | \
836 CSL_MCSPI_IRQSTATUS_TX1_EMPTY_MASK | \
837 CSL_MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK | \
838 CSL_MCSPI_IRQSTATUS_RX0_FULL_MASK | \
839 CSL_MCSPI_IRQSTATUS_TX0_UNDERFLOW_MASK | \
840 CSL_MCSPI_IRQSTATUS_TX0_EMPTY_MASK)
868 uint32_t numWordsRxTx);
999 uint32_t enableFlag);
1021 uint32_t enableFlag);
1046 uint32_t bufWidthShift = 0U;
1052 else if(dataSize <= 16U)
1061 return bufWidthShift;
1097 CSL_REG32_WR(baseAddr +
MCSPI_CHTX(chNum), txData);
1102 uint32_t enableFlag)
1108 enableFlag >> CSL_MCSPI_CH0CONF_FFEW_SHIFT);
1113 uint32_t enableFlag)
1119 enableFlag >> CSL_MCSPI_CH0CONF_FFER_SHIFT);
1125 return (CSL_REG32_RD(baseAddr +
MCSPI_CHRX(chNum)));
#define MCSPI_IS_D1
Data line 1 (SPIDAT[1]) selected for reception.
Definition: mcspi/v0/mcspi.h:212
#define MCSPI_CHRX(x)
Base address of McSPI_CHRX(x)
Definition: mcspi/v0/mcspi.h:819
void MCSPI_close(MCSPI_Handle handle)
Function to close a MCSPI peripheral specified by the MCSPI handle.
MCSPI instance attributes - used during init time.
Definition: mcspi/v0/mcspi.h:453
uint32_t transferTimeout
Definition: mcspi/v0/mcspi.h:386
static uint32_t MCSPI_readRxDataReg(uint32_t baseAddr, uint32_t chNum)
This API will return the data present in the MCSPI_RX register.
Definition: mcspi/v0/mcspi.h:1122
MCSPI channel object.
Definition: mcspi/v0/mcspi.h:491
uint32_t count
Definition: mcspi/v0/mcspi.h:335
static void MCSPI_writeTxDataReg(uint32_t baseAddr, uint32_t txData, uint32_t chNum)
This API will put the data on to the McSPI Channel transmit register.
Definition: mcspi/v0/mcspi.h:1092
static uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum)
This API returns Channel control register value.
Definition: mcspi/v0/mcspi.h:1070
void(* MCSPI_CallbackFxn)(MCSPI_Handle handle, MCSPI_Transaction *transaction)
The definition of a callback function used by the SPI driver when used in MCSPI_TRANSFER_MODE_CALLBAC...
Definition: mcspi/v0/mcspi.h:369
uint32_t status
Definition: mcspi/v0/mcspi.h:358
Data structure used with MCSPI_transfer()
Definition: mcspi/v0/mcspi.h:331
uint32_t initDelay
Definition: mcspi/v0/mcspi.h:479
uint32_t effTxFifoDepth
Definition: mcspi/v0/mcspi.h:529
static void MCSPI_enableRxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Rx FIFOs of McSPI peripheral.
Definition: mcspi/v0/mcspi.h:1111
static uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum)
This API will return the status of the McSPI channel currently in use.
Definition: mcspi/v0/mcspi.h:1064
MCSPI_ChConfig chCfg
Definition: mcspi/v0/mcspi.h:495
uint32_t intrMask
Definition: mcspi/v0/mcspi.h:533
static uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum)
This API returns Channel Config register value.
Definition: mcspi/v0/mcspi.h:1081
#define MCSPI_CS_POL_LOW
SPIEN (CS) is held low during the ACTIVE state.
Definition: mcspi/v0/mcspi.h:189
uint16_t index
Definition: tisci_rm_proxy.h:3
int32_t MCSPI_reConfigFifo(MCSPI_Handle handle, uint32_t chNum, uint32_t numWordsRxTx)
Function to re-configure Effective FIFO Words.
static uint32_t MCSPI_getBufWidthShift(uint32_t dataSize)
This API will return the buffer width in bytes based on dataSize.
Definition: mcspi/v0/mcspi.h:1044
uint32_t transferMode
Definition: mcspi/v0/mcspi.h:384
#define MCSPI_DPE_DISABLE
No transmission on Data Line.
Definition: mcspi/v0/mcspi.h:224
MCSPI driver object.
Definition: mcspi/v0/mcspi.h:541
uint32_t MCSPI_getBaseAddr(MCSPI_Handle handle)
Function to get base address of MCSPI instance of a particular handle.
#define MCSPI_SB_POL_LOW
Start-bit polarity is held to 0 during MCSPI transfer.
Definition: mcspi/v0/mcspi.h:248
uint32_t bitRate
Definition: mcspi/v0/mcspi.h:411
void MCSPI_deinit(void)
This function de-initializes the MCSPI module.
MCSPI_Handle handle
Definition: mcspi/v0/mcspi.h:545
#define MCSPI_MAX_NUM_CHANNELS
Max number of channels/Chip Select (CS) supported.
Definition: mcspi/v0/mcspi.h:92
MCSPI Parameters.
Definition: mcspi/v0/mcspi.h:383
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
void * MCSPI_Handle
A handle that is returned from a MCSPI_open() call.
Definition: mcspi/v0/mcspi.h:74
uint32_t trMode
Definition: mcspi/v0/mcspi.h:426
MCSPI_Object * object
Definition: mcspi/v0/mcspi.h:586
uint32_t txFifoTrigLvl
Definition: mcspi/v0/mcspi.h:525
uint32_t inputClkFreq
Definition: mcspi/v0/mcspi.h:459
void MCSPI_init(void)
This function initializes the MCSPI module.
#define MCSPI_MS_MODE_MASTER
The module generates the clock and CS.
Definition: mcspi/v0/mcspi.h:153
#define MCSPI_TRANSFER_MODE_BLOCKING
MCSPI_transfer() blocks execution. This mode can only be used when called within a Task context
Definition: mcspi/v0/mcspi.h:129
uint32_t isOpen
Definition: mcspi/v0/mcspi.h:501
HwiP_Object hwiObj
Definition: mcspi/v0/mcspi.h:566
uint32_t dataSize
Definition: mcspi/v0/mcspi.h:415
SemaphoreP_Object transferSemObj
Definition: mcspi/v0/mcspi.h:562
uint32_t baseAddr
Definition: mcspi/v0/mcspi.h:457
uint32_t rxFifoTrigLvl
Definition: mcspi/v0/mcspi.h:527
uint32_t curRxWords
Definition: mcspi/v0/mcspi.h:511
#define MCSPI_CHSTAT(x)
Base address of McSPI_CHSTAT(x)
Definition: mcspi/v0/mcspi.h:807
uint32_t csPolarity
Definition: mcspi/v0/mcspi.h:413
uint32_t startBitPolarity
Definition: mcspi/v0/mcspi.h:440
#define MCSPI_SLV_CS_SELECT_0
Definition: mcspi/v0/mcspi.h:233
static void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel control register value.
Definition: mcspi/v0/mcspi.h:1075
uint32_t chMode
Definition: mcspi/v0/mcspi.h:475
int32_t MCSPI_transfer(MCSPI_Handle handle, MCSPI_Transaction *transaction)
Function to perform MCSPI transactions.
uint32_t intrNum
Definition: mcspi/v0/mcspi.h:465
int32_t MCSPI_transferCancel(MCSPI_Handle handle)
Function to cancel MCSPI transactions on channel of a SPI peripheral specified by the MCSPI handle.
uint32_t msMode
Definition: mcspi/v0/mcspi.h:390
const uint8_t * curTxBufPtr
Definition: mcspi/v0/mcspi.h:503
void * args
Definition: mcspi/v0/mcspi.h:356
uint32_t dataWidthBitMask
Definition: mcspi/v0/mcspi.h:523
uint32_t pinMode
Definition: mcspi/v0/mcspi.h:477
#define MCSPI_CHTX(x)
Base address of McSPI_CHTX(x)
Definition: mcspi/v0/mcspi.h:815
uint32_t startBitEnable
Definition: mcspi/v0/mcspi.h:437
#define MCSPI_TCS0_0_CLK
0.5 clock cycles delay
Definition: mcspi/v0/mcspi.h:260
void * txBuf
Definition: mcspi/v0/mcspi.h:338
void * rxBuf
Definition: mcspi/v0/mcspi.h:349
uint32_t effRxFifoDepth
Definition: mcspi/v0/mcspi.h:531
static void MCSPI_ChConfig_init(MCSPI_ChConfig *chConfig)
Function to initialize the MCSPI_ChConfig struct to its defaults.
Definition: mcspi/v0/mcspi.h:747
uint32_t curTxWords
Definition: mcspi/v0/mcspi.h:507
uint32_t slvCsSelect
Definition: mcspi/v0/mcspi.h:434
int32_t MCSPI_chConfig(MCSPI_Handle handle, const MCSPI_ChConfig *chCfg)
Function to configure a MCSPI channel.
uint8_t intrPriority
Definition: mcspi/v0/mcspi.h:469
uint32_t intrEnable
Definition: mcspi/v0/mcspi.h:467
static void MCSPI_enableTxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Tx FIFOs of McSPI peripheral.
Definition: mcspi/v0/mcspi.h:1100
uint8_t bufWidthShift
Definition: mcspi/v0/mcspi.h:517
MCSPI global configuration array.
Definition: mcspi/v0/mcspi.h:583
void * transferSem
Definition: mcspi/v0/mcspi.h:559
MCSPI_Transaction * currTransaction
Definition: mcspi/v0/mcspi.h:569
#define MCSPI_CHCONF(x)
Base address of McSPI_CHCONF(x)
Definition: mcspi/v0/mcspi.h:803
uint8_t * curRxBufPtr
Definition: mcspi/v0/mcspi.h:505
#define MCSPI_FF_POL0_PHA0
Definition: mcspi/v0/mcspi.h:172
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
MCSPI_OpenParams openPrms
Definition: mcspi/v0/mcspi.h:547
uint32_t defaultTxData
Definition: mcspi/v0/mcspi.h:446
static void MCSPI_OpenParams_init(MCSPI_OpenParams *openPrms)
Function to initialize the MCSPI_OpenParams struct to its defaults.
Definition: mcspi/v0/mcspi.h:736
uint32_t dpe1
Definition: mcspi/v0/mcspi.h:432
uint32_t gMcspiConfigNum
Externally defined driver configuration array size.
Opaque semaphore object used with the semaphore APIs.
Definition: SemaphoreP.h:59
uint32_t channel
Definition: mcspi/v0/mcspi.h:332
#define MCSPI_TR_MODE_TX_RX
Definition: mcspi/v0/mcspi.h:198
uint32_t inputSelect
Definition: mcspi/v0/mcspi.h:428
uint32_t isOpen
Definition: mcspi/v0/mcspi.h:557
uint32_t dpe0
Definition: mcspi/v0/mcspi.h:430
static void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel Config register value.
Definition: mcspi/v0/mcspi.h:1086
MCSPI_Handle MCSPI_open(uint32_t index, const MCSPI_OpenParams *openPrms)
This function opens a given MCSPI peripheral.
MCSPI configuration parameters for the channel.
Definition: mcspi/v0/mcspi.h:406
MCSPI_Config gMcspiConfig[]
Externally defined driver configuration array.
MCSPI_CallbackFxn transferCallbackFxn
Definition: mcspi/v0/mcspi.h:388
uint32_t baseAddr
Definition: mcspi/v0/mcspi.h:549
const MCSPI_Attrs * attrs
Definition: mcspi/v0/mcspi.h:584
#define MCSPI_CHCTRL(x)
Base address of McSPI_CHCTRL(x)
Definition: mcspi/v0/mcspi.h:811
#define MCSPI_CHANNEL_0
Definition: mcspi/v0/mcspi.h:85
uint32_t frameFormat
Definition: mcspi/v0/mcspi.h:409
uint32_t csIdleTime
Definition: mcspi/v0/mcspi.h:443
#define MCSPI_DPE_ENABLE
Data line selected for transmission.
Definition: mcspi/v0/mcspi.h:222
uint32_t chNum
Definition: mcspi/v0/mcspi.h:407
void * hwiHandle
Definition: mcspi/v0/mcspi.h:564