AM243x MCU+ SDK  08.00.00
uart/v0/uart.h
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1 /*
2  * Copyright (C) 2021 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
48 #ifndef UART_V0_H_
49 #define UART_V0_H_
50 
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
54 
55 #include <stdint.h>
56 #include <kernel/dpl/SystemP.h>
57 #include <kernel/dpl/SemaphoreP.h>
58 #include <kernel/dpl/HwiP.h>
59 #include <drivers/hw_include/cslr.h>
60 #include <drivers/hw_include/cslr_uart.h>
61 #include <drivers/hw_include/hw_types.h>
62 
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66 
67 /* ========================================================================== */
68 /* Macros & Typedefs */
69 /* ========================================================================== */
70 
72 #define UART_FIFO_SIZE (64U)
73 
79 #define UART_TRANSMITEMPTY_TRIALCOUNT (3000U)
80 
82 #define UART_ERROR_COUNT (0x00FFFFFFU)
83 
85 typedef void *UART_Handle;
86 
96 #define UART_TRANSFER_STATUS_SUCCESS (0U)
97 
98 #define UART_TRANSFER_STATUS_TIMEOUT (1U)
99 
100 #define UART_TRANSFER_STATUS_ERROR_BI (2U)
101 
102 #define UART_TRANSFER_STATUS_ERROR_FE (3U)
103 
104 #define UART_TRANSFER_STATUS_ERROR_PE (4U)
105 
106 #define UART_TRANSFER_STATUS_ERROR_OE (5U)
107 
108 #define UART_TRANSFER_STATUS_CANCELLED (6U)
109 
110 #define UART_TRANSFER_STATUS_STARTED (7U)
111 
112 #define UART_TRANSFER_STATUS_READ_TIMEOUT (8U)
113 
114 #define UART_TRANSFER_STATUS_ERROR_INUSE (9U)
115 
116 #define UART_TRANSFER_STATUS_ERROR_OTH (10U)
117 
138 #define UART_TRANSFER_MODE_BLOCKING (0U)
139 
143 #define UART_TRANSFER_MODE_CALLBACK (1U)
144 
166 #define UART_READ_RETURN_MODE_FULL (0U)
167 
170 #define UART_READ_RETURN_MODE_PARTIAL (1U)
171 
181 #define UART_LEN_5 (0U)
182 #define UART_LEN_6 (1U)
183 #define UART_LEN_7 (2U)
184 #define UART_LEN_8 (3U)
185 
195 #define UART_STOPBITS_1 (0U)
196 #define UART_STOPBITS_2 (1U)
197 
207 #define UART_PARITY_NONE (0x00U)
208 #define UART_PARITY_ODD (0x01U)
209 #define UART_PARITY_EVEN (0x03U)
210 #define UART_PARITY_FORCED0 (0x07U)
211 #define UART_PARITY_FORCED1 (0x05U)
212 
222 #define UART_FCTYPE_NONE (0x00U)
223 #define UART_FCTYPE_HW (0x02U)
224 
234 #define UART_FCPARAM_RXNONE (0x00U)
235 #define UART_FCPARAM_RXXONXOFF_2 (0x01U)
236 #define UART_FCPARAM_RXXONXOFF_1 (0x02U)
237 #define UART_FCPARAM_RXXONXOFF_12 (0x03U)
238 #define UART_FCPARAM_AUTO_RTS (0x40U)
239 
249 #define UART_FCPARAM_TXNONE (0x00U)
250 #define UART_FCPARAM_TXXONXOFF_2 (0x04U)
251 #define UART_FCPARAM_TXXONXOFF_1 (0x08U)
252 #define UART_FCPARAM_TXXONXOFF_12 (0x0CU)
253 #define UART_FCPARAM_AUTO_CTS (0x80U)
254 
264 #define UART_RXTRIGLVL_1 (1U)
265 #define UART_RXTRIGLVL_8 (8U)
266 #define UART_RXTRIGLVL_16 (16U)
267 #define UART_RXTRIGLVL_56 (56U)
268 #define UART_RXTRIGLVL_60 (60U)
269 
279 #define UART_TXTRIGLVL_1 (1U)
280 #define UART_TXTRIGLVL_8 (8U)
281 #define UART_TXTRIGLVL_16 (16U)
282 #define UART_TXTRIGLVL_32 (32U)
283 #define UART_TXTRIGLVL_56 (56U)
284 
294 #define UART_OPER_MODE_16X (0U)
295 #define UART_OPER_MODE_SIR (1U)
296 #define UART_OPER_MODE_16X_AUTO_BAUD (2U)
297 #define UART_OPER_MODE_13X (3U)
298 #define UART_OPER_MODE_MIR (4U)
299 #define UART_OPER_MODE_FIR (5U)
300 #define UART_OPER_MODE_CIR (6U)
301 #define UART_OPER_MODE_DISABLED (7U)
302 
313 #define UART_TX_FIFO_NOT_FULL ( \
314  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_0)
315 #define UART_TX_FIFO_FULL ( \
316  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_1)
317 
327 #define UART_INTID_MODEM_STAT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_0 \
328  << \
329  UART_IIR_IT_TYPE_SHIFT)
330 #define UART_INTID_TX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_1 \
331  << \
332  UART_IIR_IT_TYPE_SHIFT)
333 #define UART_INTID_RX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_2 \
334  << \
335  UART_IIR_IT_TYPE_SHIFT)
336 #define UART_INTID_RX_LINE_STAT_ERROR (UART_IIR_IT_TYPE_IT_TYPE_VALUE_3 \
337  << \
338  UART_IIR_IT_TYPE_SHIFT)
339 #define UART_INTID_CHAR_TIMEOUT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_6 \
340  << \
341  UART_IIR_IT_TYPE_SHIFT)
342 #define UART_INTID_XOFF_SPEC_CHAR_DETECT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_8 \
343  << \
344  UART_IIR_IT_TYPE_SHIFT)
345 #define UART_INTID_MODEM_SIG_STATE_CHANGE (UART_IIR_IT_TYPE_IT_TYPE_VALUE_10 \
346  << \
347  UART_IIR_IT_TYPE_SHIFT)
348 
350 #define UART_INTR_PENDING (0U)
351 #define UART_N0_INTR_PENDING (1U)
352 
361 #define UART_INTR_CTS (UART_IER_CTS_IT_MASK)
362 #define UART_INTR_RTS (UART_IER_RTS_IT_MASK)
363 #define UART_INTR_XOFF (UART_IER_XOFF_IT_MASK)
364 #define UART_INTR_SLEEPMODE (UART_IER_SLEEP_MODE_MASK)
365 #define UART_INTR_MODEM_STAT (UART_IER_MODEM_STS_IT_MASK)
366 #define UART_INTR_LINE_STAT (UART_IER_LINE_STS_IT_MASK)
367 #define UART_INTR_THR (UART_IER_THR_IT_MASK)
368 #define UART_INTR_RHR_CTI (UART_IER_RHR_IT_MASK)
369 
370 #define UART_INTR2_RX_EMPTY (UART_IER2_EN_RXFIFO_EMPTY_MASK)
371 #define UART_INTR2_TX_EMPTY (UART_IER2_EN_TXFIFO_EMPTY_MASK)
372 
381 #define UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS_MASK)
382 #define UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI_MASK)
383 #define UART_FRAMING_ERROR (UART_LSR_RX_FE_MASK)
384 #define UART_PARITY_ERROR (UART_LSR_RX_PE_MASK)
385 #define UART_OVERRUN_ERROR (UART_LSR_RX_OE_MASK)
386 
395 #define UART_REG_CONFIG_MODE_A ((uint32_t) 0x0080)
396 #define UART_REG_CONFIG_MODE_B ((uint32_t) 0x00BF)
397 #define UART_REG_OPERATIONAL_MODE ((uint32_t) 0x007F)
398 
399 /* ========================================================================== */
400 /* Structures and Enums */
401 /* ========================================================================== */
402 
407 typedef struct
408 {
409  void *buf;
412  uint32_t count;
416  uint32_t timeout;
418  uint32_t status;
420  void *args;
422 } UART_Transaction;
423 
431 typedef void (*UART_CallbackFxn) (UART_Handle handle,
432  UART_Transaction *transaction);
433 
444 typedef struct
445 {
446  uint32_t baudRate;
448  uint32_t dataLength;
450  uint32_t stopBits;
452  uint32_t parityType;
454  uint32_t readMode;
456  uint32_t readReturnMode;
458  uint32_t writeMode;
460  UART_CallbackFxn readCallbackFxn;
462  UART_CallbackFxn writeCallbackFxn;
464  uint32_t hwFlowControl;
466  uint32_t hwFlowControlThr;
469  /*
470  * Driver configuration
471  */
472  uint32_t intrEnable;
474  uint32_t intrNum;
476  uint8_t intrPriority;
478  uint32_t skipIntrReg;
480  uint32_t dmaEnable;
483  /*
484  * UART configuration
485  */
486  uint32_t rxTrigLvl;
488  uint32_t txTrigLvl;
490 } UART_Params;
491 
493 typedef struct
494 {
495  /*
496  * SOC configuration
497  */
498  uint32_t baseAddr;
500  uint32_t inputClkFreq;
502 } UART_Attrs;
503 
504 /* ========================================================================== */
505 /* Internal/Private Structure Declarations */
506 /* ========================================================================== */
507 
511 typedef struct
512 {
513  /*
514  * User parameters
515  */
516  UART_Handle handle;
518  UART_Params prms;
520  /*
521  * UART write variables
522  */
523  const void *writeBuf;
525  uint32_t writeCount;
527  uint32_t writeSizeRemaining;
529  /*
530  * UART receive variables
531  */
532  void *readBuf;
534  uint32_t readCount;
536  uint32_t readSizeRemaining;
538  uint32_t rxTimeoutCnt;
540  uint32_t readErrorCnt;
542  /*
543  * UART ransaction status variables
544  */
545  UART_Transaction *readTrans;
547  UART_Transaction *writeTrans;
549  /*
550  * State variables
551  */
552  uint32_t isOpen;
554  void *lock;
556  SemaphoreP_Object lockObj;
558  void *readTransferSem;
561  SemaphoreP_Object readTransferSemObj;
563  void *writeTransferSem;
566  SemaphoreP_Object writeTransferSemObj;
568  void *hwiHandle;
570  HwiP_Object hwiObj;
572 } UART_Object;
573 
583 typedef struct
584 {
585  UART_Attrs *attrs;
587  UART_Object *object;
589 } UART_Config;
590 
592 extern UART_Config gUartConfig[];
594 extern uint32_t gUartConfigNum;
595 
596 /* ========================================================================== */
597 /* Global Variables Declarations */
598 /* ========================================================================== */
599 
600 /* None */
601 
602 /* ========================================================================== */
603 /* Function Declarations */
604 /* ========================================================================== */
605 
609 void UART_init(void);
610 
614 void UART_deinit(void);
615 
632 UART_Handle UART_open(uint32_t index, const UART_Params *prms);
633 
643 void UART_close(UART_Handle handle);
644 
679 int32_t UART_write(UART_Handle handle, UART_Transaction *trans);
680 
715 int32_t UART_read(UART_Handle handle, UART_Transaction *trans);
716 
748 int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans);
749 
781 int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans);
782 
791 UART_Handle UART_getHandle(uint32_t index);
792 
798 static inline void UART_Params_init(UART_Params *prms);
799 
806 static inline void UART_Transaction_init(UART_Transaction *trans);
807 
808 /* ========================================================================== */
809 /* Static Function Definitions */
810 /* ========================================================================== */
811 
812 static inline void UART_Params_init(UART_Params *prms)
813 {
814  if(prms != NULL)
815  {
816  prms->baudRate = 115200U;
817  prms->dataLength = UART_LEN_8;
818  prms->stopBits = UART_STOPBITS_1;
819  prms->parityType = UART_PARITY_NONE;
820  prms->readMode = UART_TRANSFER_MODE_BLOCKING;
821  prms->readReturnMode = UART_READ_RETURN_MODE_FULL;
822  prms->writeMode = UART_TRANSFER_MODE_BLOCKING;
823  prms->readCallbackFxn = NULL;
824  prms->writeCallbackFxn = NULL;
825  prms->hwFlowControl = FALSE;
826  prms->hwFlowControlThr = UART_RXTRIGLVL_16;
827  prms->intrNum = 210U;
828  prms->intrEnable = TRUE;
829  prms->intrPriority = 4U;
830  prms->skipIntrReg = FALSE;
831  prms->dmaEnable = FALSE;
832  prms->rxTrigLvl = UART_RXTRIGLVL_8;
833  prms->txTrigLvl = UART_TXTRIGLVL_32;
834  }
835 }
836 
837 static inline void UART_Transaction_init(UART_Transaction *trans)
838 {
839  if(trans != NULL)
840  {
841  trans->buf = NULL;
842  trans->count = 0U;
843  trans->timeout = SystemP_WAIT_FOREVER;
844  trans->status = UART_TRANSFER_STATUS_SUCCESS;
845  trans->args = NULL;
846  }
847 }
848 
849 /* ========================================================================== */
850 /* Advanced Function Declarations */
851 /* ========================================================================== */
860 uint32_t UART_getBaseAddr(UART_Handle handle);
861 
879 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx);
880 
895 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar);
896 
925 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag);
926 
951 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag);
952 
971 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag);
972 
990 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag);
991 
1017 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr);
1018 
1031 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr);
1032 
1047 static inline uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr);
1048 
1059 static inline uint32_t UART_readLineStatus(uint32_t baseAddr);
1060 
1074 static inline uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf);
1075 /* ========================================================================== */
1076 /* Advanced Function Definitions */
1077 /* ========================================================================== */
1078 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
1079 {
1080  /* Write the byte to the Transmit Holding Register(or TX FIFO). */
1081  HW_WR_REG32(baseAddr + UART_THR, (uint32_t) byteTx);
1082 }
1083 
1084 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
1085 {
1086  uint32_t lcrRegValue = 0U;
1087  uint32_t retVal = FALSE;
1088 
1089  /* Preserving the current value of LCR. */
1090  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1091 
1092  /* Switching to Register Operational Mode of operation. */
1093  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1094  & 0x7FU);
1095 
1096  /* Checking if the RX FIFO(or RHR) has atleast one byte of data. */
1097  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1098  (HW_RD_REG32(baseAddr + UART_LSR) &
1099  UART_LSR_RX_FIFO_E_MASK))
1100  {
1101  uint32_t tempRetVal = HW_RD_REG32(baseAddr + UART_RHR);
1102  *pChar = (uint8_t)tempRetVal;
1103  retVal = TRUE;
1104  }
1105 
1106  /* Restoring the value of LCR. */
1107  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1108 
1109  return retVal;
1110 }
1111 
1112 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
1113 {
1114  uint32_t enhanFnBitVal = 0U;
1115  uint32_t lcrRegValue = 0U;
1116 
1117  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1118  if ((intrFlag & 0xF0U) > 0U)
1119  {
1120  /* Preserving the current value of LCR. */
1121  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1122  /* Switching to Register Configuration Mode B. */
1123  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1124 
1125  /* Collecting the current value of EFR[4] and later setting it. */
1126  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1127 
1128  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1129  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1130 
1131  /* Restoring the value of LCR. */
1132  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1133 
1134  /* Preserving the current value of LCR. */
1135  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1136 
1137  /* Switching to Register Operational Mode of operation. */
1138  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1139  & 0x7FU);
1140 
1141  /*
1142  ** It is suggested that the System Interrupts for UART in the
1143  ** Interrupt Controller are enabled after enabling the peripheral
1144  ** interrupts of the UART using this API. If done otherwise, there
1145  ** is a risk of LCR value not getting restored and illicit characters
1146  ** transmitted or received from/to the UART. The situation is explained
1147  ** below.
1148  ** The scene is that the system interrupt for UART is already enabled
1149  ** and the current API is invoked. On enabling the interrupts
1150  ** corresponding to IER[7:4] bits below, if any of those interrupt
1151  ** conditions already existed, there is a possibility that the control
1152  ** goes to Interrupt Service Routine (ISR) without executing the
1153  ** remaining statements in this API. Executing the remaining statements
1154  ** is critical in that the LCR value is restored in them.
1155  ** However, there seems to be no risk in this API for enabling
1156  ** interrupts corresponding to IER[3:0] because it is done at the end
1157  ** and no statements follow that.
1158  */
1159 
1160  /************* ATOMIC STATEMENTS START *************************/
1161 
1162  /* Programming the bits IER[7:4]. */
1163  HW_WR_REG32(baseAddr + UART_IER, intrFlag & 0xF0U);
1164 
1165  /* Restoring the value of LCR. */
1166  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1167 
1168  /* Preserving the current value of LCR. */
1169  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1170  /* Switching to Register Configuration Mode B. */
1171  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1172 
1173  /* Restoring the value of EFR[4] to its original value. */
1174  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1175 
1176  /* Restoring the value of LCR. */
1177  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1178 
1179  /************** ATOMIC STATEMENTS END *************************/
1180  }
1181 
1182  /* Programming the bits IER[3:0]. */
1183  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) |
1184  (intrFlag & 0x0FU));
1185 }
1186 
1187 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
1188 {
1189  uint32_t enhanFnBitVal;
1190  uint32_t lcrRegValue;
1191 
1192  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1193  if((intrFlag & 0xF0U) > 0U)
1194  {
1195  /* Preserving the current value of LCR. */
1196  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1197  /* Switching to Register Configuration Mode B. */
1198  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1199 
1200  /* Collecting the current value of EFR[4] and later setting it. */
1201  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1202 
1203  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1204  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1205 
1206  /* Restoring the value of LCR. */
1207  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1208  }
1209 
1210  /* Preserving the current value of LCR. */
1211  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1212 
1213  /* Switching to Register Operational Mode of operation. */
1214  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1215  & 0x7FU);
1216 
1217  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) &
1218  ~(intrFlag & 0xFFU));
1219 
1220  /* Restoring the value of LCR. */
1221  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1222 
1223  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1224  if((intrFlag & 0xF0U) > 0U)
1225  {
1226  /* Preserving the current value of LCR. */
1227  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1228  /* Switching to Register Configuration Mode B. */
1229  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1230 
1231  /* Restoring the value of EFR[4] to its original value. */
1232  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1233 
1234  /* Restoring the value of LCR. */
1235  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1236  }
1237 }
1238 
1239 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
1240 {
1241  /* Programming the bits IER2[1:0]. */
1242  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) |
1243  (intrFlag & 0x03U));
1244 }
1245 
1246 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
1247 {
1248  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) &
1249  ~(intrFlag & 0x3U));
1250 }
1251 
1252 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
1253 {
1254  uint32_t lcrRegValue = 0U;
1255  uint32_t retVal = 0U;
1256 
1257  /* Preserving the current value of LCR. */
1258  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1259 
1260  /* Switching to Register Operational Mode of operation. */
1261  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1262  & 0x7FU);
1263 
1264  retVal = HW_RD_REG32(baseAddr + UART_IIR) & UART_IIR_IT_TYPE_MASK;
1265 
1266  /* Restoring the value of LCR. */
1267  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1268 
1269  return retVal;
1270 }
1271 
1272 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr)
1273 {
1274  uint32_t retVal = 0U;
1275 
1276  retVal = HW_RD_REG32(baseAddr + UART_ISR2) &
1277  (UART_IER2_EN_RXFIFO_EMPTY_MASK | UART_IER2_EN_TXFIFO_EMPTY_MASK);
1278 
1279  return retVal;
1280 }
1281 
1282 static inline uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
1283 {
1284  uint32_t lcrRegValue = 0;
1285  uint32_t retVal = FALSE;
1286 
1287  /* Preserving the current value of LCR. */
1288  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1289 
1290  /* Switching to Register Operational Mode of operation. */
1291  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1292  & 0x7FU);
1293 
1294  /* Checking if the RHR(or RX FIFO) has atleast one byte to be read. */
1295  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1296  (HW_RD_REG32(baseAddr + UART_LSR) &
1297  UART_LSR_RX_FIFO_E_MASK))
1298  {
1299  retVal = (uint32_t) TRUE;
1300  }
1301 
1302  /* Restoring the value of LCR. */
1303  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1304 
1305  return retVal;
1306 }
1307 
1308 static inline uint32_t UART_readLineStatus(uint32_t baseAddr)
1309 {
1310  uint32_t lcrRegValue = 0U;
1311  uint32_t retVal = 0U;
1312 
1313  /* Preserving the current value of LCR. */
1314  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1315 
1316  /* Switching to Register Operational Mode of operation. */
1317  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1318  & 0x7FU);
1319 
1320  retVal = HW_RD_REG32(baseAddr + UART_LSR);
1321 
1322  /* Restoring the value of LCR. */
1323  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1324 
1325  return retVal;
1326 }
1327 
1328 static inline uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
1329 {
1330  uint8_t readByte = 0;
1331  uint32_t waitCount = UART_ERROR_COUNT;
1332  uint32_t errorVal;
1333  uint32_t lcrRegValue = 0;
1334 
1335  /* Preserving the current value of LCR. */
1336  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1337 
1338  /* Switching to Register Operational Mode of operation. */
1339  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1340  & 0x7FU);
1341 
1342  /* Read Rx Error Status */
1343  errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1344  (UART_LSR_RX_FIFO_STS_MASK |
1345  UART_LSR_RX_BI_MASK |
1346  UART_LSR_RX_FE_MASK |
1347  UART_LSR_RX_PE_MASK |
1348  UART_LSR_RX_OE_MASK);
1349 
1350  /* Restoring the value of LCR. */
1351  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1352 
1353  /* Read and throw Erroneous bytes from RxFIFO */
1354  while ((UART_LSR_RX_FIFO_STS_MASK |
1355  UART_LSR_RX_BI_MASK |
1356  UART_LSR_RX_FE_MASK |
1357  UART_LSR_RX_PE_MASK |
1358  UART_LSR_RX_OE_MASK) == errorVal)
1359  {
1360  readByte = HW_RD_REG32(baseAddr + UART_RHR);
1361  waitCount--;
1362  if (0U == waitCount)
1363  {
1364  break;
1365  }
1366 
1367  /* Preserving the current value of LCR. */
1368  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1369 
1370  /* Switching to Register Operational Mode of operation. */
1371  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1372  & 0x7FU);
1373 
1374  /* Read Rx Error Status */
1375  errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1376  (UART_LSR_RX_FIFO_STS_MASK |
1377  UART_LSR_RX_BI_MASK |
1378  UART_LSR_RX_FE_MASK |
1379  UART_LSR_RX_PE_MASK |
1380  UART_LSR_RX_OE_MASK);
1381 
1382  /* Restoring the value of LCR. */
1383  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1384  }
1385 
1386  /* Read non-erroneous byte from RxFIFO */
1387  readByte = HW_RD_REG32(baseAddr + UART_RHR);
1388 
1389  return readByte;
1390 }
1391 
1392 #ifdef __cplusplus
1393 }
1394 #endif
1395 
1396 #endif /* #ifndef UART_V0_H_ */
1397 
UART_deinit
void UART_deinit(void)
This function de-initializes the UART module.
UART_Object::readTransferSem
void * readTransferSem
Definition: uart/v0/uart.h:558
UART_ERROR_COUNT
#define UART_ERROR_COUNT
Count Value to check error in the recieved byte
Definition: uart/v0/uart.h:82
UART_TRANSFER_MODE_BLOCKING
#define UART_TRANSFER_MODE_BLOCKING
UART read/write APIs blocks execution. This mode can only be used when called within a Task context.
Definition: uart/v0/uart.h:138
UART_Object::lockObj
SemaphoreP_Object lockObj
Definition: uart/v0/uart.h:556
UART_Transaction_init
static void UART_Transaction_init(UART_Transaction *trans)
Function to initialize the UART_Transaction struct to its defaults.
Definition: uart/v0/uart.h:837
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SemaphoreP_Object readTransferSemObj
Definition: uart/v0/uart.h:561
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#define UART_REG_CONFIG_MODE_B
Definition: uart/v0/uart.h:396
UART_STOPBITS_1
#define UART_STOPBITS_1
Definition: uart/v0/uart.h:195
UART_TRANSFER_STATUS_SUCCESS
#define UART_TRANSFER_STATUS_SUCCESS
Transaction success.
Definition: uart/v0/uart.h:96
UART_Object::handle
UART_Handle handle
Definition: uart/v0/uart.h:516
UART_intr2Enable
static void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v0/uart.h:1239
UART_Object::hwiHandle
void * hwiHandle
Definition: uart/v0/uart.h:568
index
uint16_t index
Definition: tisci_rm_proxy.h:3
UART_Object::writeBuf
const void * writeBuf
Definition: uart/v0/uart.h:523
SystemP.h
UART_Transaction::timeout
uint32_t timeout
Definition: uart/v0/uart.h:416
UART_Handle
void * UART_Handle
A handle that is returned from a UART_open() call.
Definition: uart/v0/uart.h:85
UART_Object::writeTrans
UART_Transaction * writeTrans
Definition: uart/v0/uart.h:547
UART_getHandle
UART_Handle UART_getHandle(uint32_t index)
Function to return a open'ed UART handle given a UART instance index.
UART_writeCancel
int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current write transaction.
UART_Config
UART global configuration array.
Definition: uart/v0/uart.h:584
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uint32_t writeMode
Definition: uart/v0/uart.h:458
UART_getIntr2Status
static uint32_t UART_getIntr2Status(uint32_t baseAddr)
This API determines the UART Interrupt Status 2.
Definition: uart/v0/uart.h:1272
UART_Object::writeSizeRemaining
uint32_t writeSizeRemaining
Definition: uart/v0/uart.h:527
UART_CallbackFxn
void(* UART_CallbackFxn)(UART_Handle handle, UART_Transaction *transaction)
The definition of a callback function used by the UART driver when used in UART_TRANSFER_MODE_CALLBAC...
Definition: uart/v0/uart.h:431
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uint32_t dataLength
Definition: uart/v0/uart.h:448
SystemP_WAIT_FOREVER
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
UART_Params::intrPriority
uint8_t intrPriority
Definition: uart/v0/uart.h:476
UART_write
int32_t UART_write(UART_Handle handle, UART_Transaction *trans)
Function to perform UART write operation.
UART_Params::readMode
uint32_t readMode
Definition: uart/v0/uart.h:454
UART_RXTRIGLVL_8
#define UART_RXTRIGLVL_8
Definition: uart/v0/uart.h:265
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uint32_t intrEnable
Definition: uart/v0/uart.h:472
SemaphoreP.h
UART_intrDisable
static void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation.
Definition: uart/v0/uart.h:1187
UART_PARITY_NONE
#define UART_PARITY_NONE
Definition: uart/v0/uart.h:207
UART_Params::rxTrigLvl
uint32_t rxTrigLvl
Definition: uart/v0/uart.h:486
UART_getChar
static uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is rea...
Definition: uart/v0/uart.h:1084
UART_close
void UART_close(UART_Handle handle)
Function to close a UART peripheral specified by the UART handle.
gUartConfig
UART_Config gUartConfig[]
Externally defined driver configuration array.
UART_getIntrIdentityStatus
static uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
This API determines the UART Interrupt Status.
Definition: uart/v0/uart.h:1252
UART_Transaction::args
void * args
Definition: uart/v0/uart.h:420
UART_READ_RETURN_MODE_FULL
#define UART_READ_RETURN_MODE_FULL
Unblock/callback when buffer is full.
Definition: uart/v0/uart.h:166
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uint32_t isOpen
Definition: uart/v0/uart.h:552
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uint32_t skipIntrReg
Definition: uart/v0/uart.h:478
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UART_Attrs * attrs
Definition: uart/v0/uart.h:585
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uint32_t dmaEnable
Definition: uart/v0/uart.h:480
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SemaphoreP_Object writeTransferSemObj
Definition: uart/v0/uart.h:566
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void * lock
Definition: uart/v0/uart.h:554
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uint32_t readCount
Definition: uart/v0/uart.h:534
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uint32_t parityType
Definition: uart/v0/uart.h:452
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Definition: uart/v0/uart.h:538
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static void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
This API writes a byte to the Transmitter FIFO without checking for the emptiness of the Transmitter ...
Definition: uart/v0/uart.h:1078
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uint32_t writeCount
Definition: uart/v0/uart.h:525
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uint32_t hwFlowControl
Definition: uart/v0/uart.h:464
UART_Object::readSizeRemaining
uint32_t readSizeRemaining
Definition: uart/v0/uart.h:536
UART_Params::readReturnMode
uint32_t readReturnMode
Definition: uart/v0/uart.h:456
HwiP.h
UART_init
void UART_init(void)
This function initializes the UART module.
UART_Params
UART Parameters.
Definition: uart/v0/uart.h:445
UART_readCancel
int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current read transaction.
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uint32_t baudRate
Definition: uart/v0/uart.h:446
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UART_CallbackFxn readCallbackFxn
Definition: uart/v0/uart.h:460
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uint32_t readErrorCnt
Definition: uart/v0/uart.h:540
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void * writeTransferSem
Definition: uart/v0/uart.h:563
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uint32_t status
Definition: uart/v0/uart.h:418
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UART_Object * object
Definition: uart/v0/uart.h:587
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Data structure used with UART_read() and UART_write()
Definition: uart/v0/uart.h:408
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uint32_t UART_getBaseAddr(UART_Handle handle)
Function to get base address of UART instance of a particular handle.
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#define UART_LEN_8
Definition: uart/v0/uart.h:184
UART_checkCharsAvailInFifo
static uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
This API checks if the RX FIFO (or RHR in non-FIFO mode) has atleast one byte of data to be read.
Definition: uart/v0/uart.h:1282
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uint32_t intrNum
Definition: uart/v0/uart.h:474
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uint32_t inputClkFreq
Definition: uart/v0/uart.h:500
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UART_Handle UART_open(uint32_t index, const UART_Params *prms)
This function opens a given UART peripheral.
UART_Params::writeCallbackFxn
UART_CallbackFxn writeCallbackFxn
Definition: uart/v0/uart.h:462
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Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
UART_Object
UART driver object.
Definition: uart/v0/uart.h:512
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uint32_t hwFlowControlThr
Definition: uart/v0/uart.h:466
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UART_Transaction * readTrans
Definition: uart/v0/uart.h:545
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uint32_t stopBits
Definition: uart/v0/uart.h:450
UART_intr2Disable
static void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v0/uart.h:1246
UART_Object::readBuf
void * readBuf
Definition: uart/v0/uart.h:532
UART_Params_init
static void UART_Params_init(UART_Params *prms)
Function to initialize the UART_Params struct to its defaults.
Definition: uart/v0/uart.h:812
gUartConfigNum
uint32_t gUartConfigNum
Externally defined driver configuration array size.
SemaphoreP_Object
Opaque semaphore object used with the semaphore APIs.
Definition: SemaphoreP.h:59
UART_read
int32_t UART_read(UART_Handle handle, UART_Transaction *trans)
Function to perform UART read operation.
UART_TXTRIGLVL_32
#define UART_TXTRIGLVL_32
Definition: uart/v0/uart.h:282
UART_Attrs
UART instance attributes - used during init time.
Definition: uart/v0/uart.h:494
UART_RXTRIGLVL_16
#define UART_RXTRIGLVL_16
Definition: uart/v0/uart.h:266
UART_readLineStatus
static uint32_t UART_readLineStatus(uint32_t baseAddr)
This API reads the line status register value.
Definition: uart/v0/uart.h:1308
UART_getCharFifo
static uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
This API reads the data present at the top of the RX FIFO, that is, the data in the Receive Holding R...
Definition: uart/v0/uart.h:1328
UART_Attrs::baseAddr
uint32_t baseAddr
Definition: uart/v0/uart.h:498
UART_Transaction::buf
void * buf
Definition: uart/v0/uart.h:409
UART_intrEnable
static void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation.
Definition: uart/v0/uart.h:1112
UART_Object::hwiObj
HwiP_Object hwiObj
Definition: uart/v0/uart.h:570
UART_Object::prms
UART_Params prms
Definition: uart/v0/uart.h:518
UART_Transaction::count
uint32_t count
Definition: uart/v0/uart.h:412
UART_Params::txTrigLvl
uint32_t txTrigLvl
Definition: uart/v0/uart.h:488