//*****************************************************************************
//! @file       cc13x0f128.cmd
//! @brief      CC13x0F128 PG2 linker configuration file for Code Composer Studio.
//!
//! Revised     $Date: 2015-09-04 10:38:12 +0200 (fr, 04 sep 2015) $
//! Revision    $Revision: 16040 $
//
//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
//
//
//  Redistribution and use in source and binary forms, with or without
//  modification, are permitted provided that the following conditions
//  are met:
//
//    Redistributions of source code must retain the above copyright
//    notice, this list of conditions and the following disclaimer.
//
//    Redistributions in binary form must reproduce the above copyright
//    notice, this list of conditions and the following disclaimer in the
//    documentation and/or other materials provided with the distribution.
//
//    Neither the name of Texas Instruments Incorporated nor the names of
//    its contributors may be used to endorse or promote products derived
//    from this software without specific prior written permission.
//
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//****************************************************************************/

/* Retain interrupt vector table variable                                    */
--retain=g_pfnVectors
/* Override default entry point.                                             */
--entry_point ResetISR
/* Allow main() to take args                                                 */
--args 0x8
/* Suppress warnings and errors:                                             */
/* - 10063: Warning about entry point not being _c_int00                     */
/* - 16011, 16012: 8-byte alignment errors. Observed when linking in object  */ 
/*   files compiled using Keil (ARM compiler)                                */
--diag_suppress=10063,16011,16012

/* The following command line options are set as part of the CCS project.    */
/* If you are building using the command line, or for some reason want to    */
/* define them here, you can uncomment and modify these lines as needed.     */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone.              */
/*                                                                           */
/* --heap_size=0                                                             */
/* --stack_size=256                                                          */
/* --library=rtsv7M3_T_le_eabi.lib                                           */


// Memory segment specification
// ----------------------------
// 0x0000 .. 0xfff  is available for bootloader
#define FLASH_BOOT1_BASE        0x0
#define FLASH_BOOT1_SIZE        0x1000

// The next page is reserved for TI-RTOS hard-coded symbols
// 0x1000 .. 0x14ff
#define FLASH_TIRTOS1_BASE      0x1000
#define FLASH_TIRTOS1_SIZE      0x1000

// Next pages are available for more bootloader code
// 0x2000 .. 0x4fff
#define FLASH_BOOT2_BASE        0x2000
#define FLASH_BOOT2_SIZE        0x3000

// There are 104 KiB left for application
// 0x5000 .. 0x10FFF
#define FLASH_TIRTOS2_BASE      0x5000
#define FLASH_TIRTOS2_SIZE      0x1A000

// The last flash page is reserved for custom configuration
// 0x1F000 .. 0x1FFFF
#define FLASH_CCFG_BASE         0x1F000
#define FLASH_CCFG_SIZE         0x1000

#define RAM_BASE                0x20000000
#define RAM_SIZE                0x5000
#define GPRAM_BASE              0x11000000
#define GPRAM_SIZE              0x2000

// System memory map
// -----------------
MEMORY
{
    FLASH_BOOT1 (RX)   : origin = FLASH_BOOT1_BASE,   length = FLASH_BOOT1_SIZE
    FLASH_TIRTOS1 (RX) : origin = FLASH_TIRTOS1_BASE, length = FLASH_TIRTOS1_SIZE
    FLASH_BOOT2 (RX)   : origin = FLASH_BOOT2_BASE,   length = FLASH_BOOT2_SIZE
    FLASH_TIRTOS2 (RX) : origin = FLASH_TIRTOS2_BASE, length = FLASH_TIRTOS2_SIZE
    FLASH_CCFG  (RX)   : origin = FLASH_CCFG_BASE,    length = FLASH_CCFG_SIZE

    SRAM (RWX)         : origin = RAM_BASE,           length = RAM_SIZE
    GPRAM (RWX)        : origin = GPRAM_BASE,         length = GPRAM_SIZE
}

// Section allocation in memory for the bootloader
SECTIONS
{
    .intvecs        :   >  FLASH_BOOT1_BASE
    .const          :   >> FLASH_BOOT1 | FLASH_BOOT2
    .constdata      :   >> FLASH_BOOT1 | FLASH_BOOT2
    .rodata         :   >> FLASH_BOOT1 | FLASH_BOOT2
    .binit          :   >> FLASH_BOOT1 | FLASH_BOOT2
    .cinit          :   >  FLASH_BOOT2
    .pinit          :   >> FLASH_BOOT1 | FLASH_BOOT2
    .init_array     :   >> FLASH_BOOT1 | FLASH_BOOT2
    .emb_text       :   >> FLASH_BOOT1 | FLASH_BOOT2
    .text           :   >> FLASH_BOOT1 | FLASH_BOOT2
    .ccfg           :   >  FLASH_CCFG (HIGH)

    .vtable         :   > SRAM
    .vtable_ram     :   > SRAM
     vtable_ram     :   > SRAM
    .data           :   > SRAM
    .bss            :   > SRAM
    .sysmem         :   > SRAM
    .stack          :   > SRAM (HIGH)
    .nonretenvar    :   > SRAM
    .gpram          :   > GPRAM
}