Software Diagnostics Library (SDL) - J721E User Guide
01_04_00

Table of Contents

  • 1. Overview
  • 1. Release Notes
  • 2. Getting Started
  • 2. Modules
    • 2.1. ESM : Error Signalling Module
    • 2.2. ECC : Error Correcting Code
    • 2.3. PBIST : Memory Built-In Self-Test
    • 2.4. LBIST : Logic Built-In Self-Test
    • 2.5. VTM : Voltage and Thermal Management
    • 2.6. RTI : RTI/WWDT Windowed Watchdog Timer
    • 2.7. POK: Power OK
    • 2.8. TOG : Time-Out Gasket
    • 2.9. DCC : Dual Clock Comparator
    • 2.10. MCRC : Cyclic Redundancy Check
    • 2.11. R5F CCM: CPU Compare Module
    • 2.12. OSAL
    • 2.13. R5 Core Modules
    • 2.14. ROM_CHECKSUM: ROM Checksum Module
  • 3. Safety Examples
  • 3. Diagnostic Mapping
  • 4. Developer Notes
Software Diagnostics Library (SDL) - J721E User Guide
  • Docs »
  • 2. Modules

2. ModulesΒΆ

  • 2.1. ESM : Error Signalling Module
  • 2.2. ECC : Error Correcting Code
  • 2.3. PBIST : Memory Built-In Self-Test
  • 2.4. LBIST : Logic Built-In Self-Test
  • 2.5. VTM : Voltage and Thermal Management
  • 2.6. RTI : RTI/WWDT Windowed Watchdog Timer
  • 2.7. POK: Power OK
  • 2.8. TOG : Time-Out Gasket
  • 2.9. DCC : Dual Clock Comparator
  • 2.10. MCRC : Cyclic Redundancy Check
  • 2.11. R5F CCM: CPU Compare Module
  • 2.12. OSAL
  • 2.13. R5 Core Modules
  • 2.14. ROM_CHECKSUM: ROM Checksum Module
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