SDL API Guide for J721E
sdl_esm_core.h
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1 /*
2  * SDL ESM
3  *
4  * Software Diagnostics Reference module for Error Signaling Module
5  *
6  * Copyright (c) Texas Instruments Incorporated 2021
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
38 #ifndef INCLUDE_SDL_ESM_CORE_H_
39 #define INCLUDE_SDL_ESM_CORE_H_
40 #include <src/ip/sdl_esm.h>
41 
42 #if defined (SOC_J721E)
43 #include <include/soc/j721e/sdlr_intr_mcu_esm0.h>
44 #include <include/soc/j721e/sdlr_intr_esm0.h>
45 #endif /* SOC_J721E */
46 
47 #if defined (SOC_J7200)
48 #include <include/soc/j7200/sdlr_intr_mcu_esm0.h>
49 #include <include/soc/j7200/sdlr_intr_esm0.h>
50 #endif /* SOC_J7200 */
51 
52 #if defined (SOC_J721S2)
53 #include <include/soc/j721s2/sdlr_intr_mcu_esm0.h>
54 #include <include/soc/j721s2/sdlr_intr_esm0.h>
55 #endif /* SOC_J721S2 */
56 
57 #if defined (SOC_J784S4)
58 #include <include/soc/j784s4/sdlr_intr_mcu_esm0.h>
59 #include <include/soc/j784s4/sdlr_intr_esm0.h>
60 #endif /* SOC_J784S4 */
61 
62 #ifdef __cplusplus
63 extern "C" {
64 #endif
65 
66 /* Enumerate Interrupt number for the different esm interrupts */
67 #define SDL_MCU_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_HI_LVL_0
68 #define SDL_MCU_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_LOW_LVL_0
69 #define SDL_MCU_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_CFG_LVL_0
70 
71 #define SDL_WKUP_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_HI_LVL_0
72 #define SDL_WKUP_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_LOW_LVL_0
73 #define SDL_WKUP_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_CFG_LVL_0
74 
75 #define SDL_MAIN_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_HI_LVL_0
76 #define SDL_MAIN_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_LOW_LVL_0
77 #define SDL_MAIN_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_CFG_LVL_0
78 
79 /* Enumerate ESM events for R5F core handled by SDL */
80 #define SDL_ESM_MCU_R5_CORE0_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0
81 #define SDL_ESM_MCU_R5_CORE0_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
82 #define SDL_ESM_MCU_R5_CORE1_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0
83 #define SDL_ESM_MCU_R5_CORE1_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0
84 #define SDL_ESM_MAIN_ESM_ERROR_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_GLUELOGIC_ESM_MAIN_ERR_GLUE_ERR_I_N_0
85 
86 
87 #if defined (SOC_J721E)
88 #define SDL_ESM_MCU_RTI0_WWD_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_RTI0_INTR_WWD_0
89 #define SDL_ESM_MCU_RTI1_WWD_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_RTI1_INTR_WWD_0
90 #define SDL_ESM_MCU_R5_SELFTEST_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_SELFTEST_ERR_PULSE_0
91 #define SDL_ESM_MCU_R5_CPU_BUS_CMP_ERR SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMPARE_ERR_PULSE_0
92 #define SDL_ESM_MCU_R5_INACTIVITY_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_BUS_MONITOR_ERR_PULSE_0
93 #define SDL_ESM_MCU_R5_VIM_BUS_CMP_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_VIM_COMPARE_ERR_PULSE_0
94 #define SDL_ESM_MCU_R5_CCM_STAT_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0
95 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_0
96 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_1
97 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_2
98 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_3
99 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_4
100 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_5
101 #define SDL_ESM_MAIN_A72_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_7
102 #define SDL_ESM_MAIN_A72_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_8
103 #define SDL_ESM_MAIN_A72_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_9
104 #define SDL_ESM_MAIN_A72_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_10
105 #define SDL_ESM_MAIN_A72_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_11
106 #define SDL_ESM_MAIN_A72_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_12
107 
108 #define SDL_ESM_MCU_CBASS_ECC_AGGR_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0
109 #define SDL_ESM_MCU_CBASS_ECC_AGGR_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0
110 #endif /* SOC_J721E */
111 
112 #if defined (SOC_J7200)
113 #define SDL_ESM_MCU_RTI0_WWD_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_RTI0_INTR_WWD_0
114 #define SDL_ESM_MCU_RTI1_WWD_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_RTI1_INTR_WWD_0
115 #define SDL_ESM_MCU_R5_SELFTEST_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_SELFTEST_ERR_PULSE_0
116 #define SDL_ESM_MCU_R5_CPU_BUS_CMP_ERR SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_COMPARE_ERR_PULSE_0
117 #define SDL_ESM_MCU_R5_INACTIVITY_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_BUS_MONITOR_ERR_PULSE_0
118 #define SDL_ESM_MCU_R5_VIM_BUS_CMP_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_VIM_COMPARE_ERR_PULSE_0
119 #define SDL_ESM_MCU_R5_CCM_STAT_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0
120 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_0
121 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_1
122 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_2
123 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_3
124 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_4
125 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_5
126 #define SDL_ESM_MAIN_A72_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_7
127 #define SDL_ESM_MAIN_A72_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_8
128 #define SDL_ESM_MAIN_A72_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_9
129 #define SDL_ESM_MAIN_A72_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_10
130 #define SDL_ESM_MAIN_A72_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_11
131 #define SDL_ESM_MAIN_A72_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_12
132 
133 #define SDL_ESM_MCU_CBASS_ECC_AGGR_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0
134 #define SDL_ESM_MCU_CBASS_ECC_AGGR_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0
135 #endif /* SOC_J7200 */
136 
137 #if defined (SOC_J721S2)
138 
139 #define SDL_ESM_MCU_RTI0_WWD_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_RTI0_INTR_WWD_0
140 #define SDL_ESM_MCU_RTI1_WWD_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_RTI1_INTR_WWD_0
141 #define SDL_ESM_MCU_R5_SELFTEST_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_SELFTEST_ERR_PULSE_0
142 #define SDL_ESM_MCU_R5_CPU_BUS_CMP_ERR SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_COMPARE_ERR_PULSE_0
143 #define SDL_ESM_MCU_R5_INACTIVITY_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_BUS_MONITOR_ERR_PULSE_0
144 #define SDL_ESM_MCU_R5_VIM_BUS_CMP_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_VIM_COMPARE_ERR_PULSE_0
145 #define SDL_ESM_MCU_R5_CCM_STAT_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0
146 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_0
147 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_1
148 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_2
149 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_3
150 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_4
151 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_5
152 #define SDL_ESM_MAIN_A72_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_7
153 #define SDL_ESM_MAIN_A72_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_8
154 #define SDL_ESM_MAIN_A72_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_9
155 #define SDL_ESM_MAIN_A72_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_10
156 #define SDL_ESM_MAIN_A72_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_11
157 #define SDL_ESM_MAIN_A72_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_12
158 
159 #define SDL_ESM_MCU_CBASS_ECC_AGGR_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0
160 #define SDL_ESM_MCU_CBASS_ECC_AGGR_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0
161 
162 #endif /* SOC_J721S2 */
163 
164 #if defined (SOC_J784S4)
165 
166 #define SDL_ESM_MCU_RTI0_WWD_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_RTI0_INTR_WWD_0
167 #define SDL_ESM_MCU_RTI1_WWD_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_RTI1_INTR_WWD_0
168 #define SDL_ESM_MCU_R5_SELFTEST_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_SELFTEST_ERR_PULSE_0
169 #define SDL_ESM_MCU_R5_CPU_BUS_CMP_ERR SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_COMPARE_ERR_PULSE_0
170 #define SDL_ESM_MCU_R5_INACTIVITY_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_BUS_MONITOR_ERR_PULSE_0
171 #define SDL_ESM_MCU_R5_VIM_BUS_CMP_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_VIM_COMPARE_ERR_PULSE_0
172 #define SDL_ESM_MCU_R5_CCM_STAT_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0
173 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_0
174 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_1
175 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_2
176 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_3
177 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_4
178 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_5
179 #define SDL_ESM_MAIN_A72_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_7
180 #define SDL_ESM_MAIN_A72_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_8
181 #define SDL_ESM_MAIN_A72_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_9
182 #define SDL_ESM_MAIN_A72_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_10
183 #define SDL_ESM_MAIN_A72_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_11
184 #define SDL_ESM_MAIN_A72_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_12
185 
186 #define SDL_ESM_MCU_CBASS_ECC_AGGR_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCUM_MCU_ECC_AGGR0_CORR_LEVEL_0
187 #define SDL_ESM_MCU_CBASS_ECC_AGGR_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCUM_MCU_ECC_AGGR0_UNCORR_LEVEL_0
188 
189 #endif /* SOC_J784S4 */
190 
191 #ifdef __cplusplus
192 }
193 #endif /* extern "C" */
194 #endif /* INCLUDE_SDL_ESM_CORE_H_ */
195 
196 
sdl_esm.h
Header file contains enumerations, structure definitions and function declarations for SDL Error Sign...