SERDES CSL FL

Introduction

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Introduction

Overview

This is the top level SERDES API with enumerations for various supported reference clocks, link rates, lane control rates across different modules.

References

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Data Structures
struct	CSL_SerdesTxCoeff
struct	CSL_SerdesRxCoeff
struct	CSL_SerdesTapOffsets
struct	CSL_SerdesTbusDump
struct	CSL_SerdesTxTerm
struct	CSL_SerdesLaneEnableParams

Functions
void	CSL_serdesCycleDelay (uint64_t count)
void	CSL_serdesDisablePllAndLanes (uint32_t baseAddr, uint32_t numLanes, uint8_t laneMask)
void	CSL_serdesInvertLaneTXPolarity (uint32_t baseAddr, uint32_t laneNum)
void	CSL_serdesInvertLaneRXPolarity (uint32_t baseAddr, uint32_t laneNum)
void	CSL_serdesPorReset (uint32_t baseAddr)
void	CSL_serdesDisablePLL (uint32_t baseAddr, CSL_SerdesPhyType phyType)
void	CSL_serdesDisableLanes (uint32_t baseAddr, uint32_t laneNum, uint8_t laneMask)
void	CSL_serdesEnableLanes (uint32_t baseAddr, uint32_t laneNum, CSL_SerdesPhyType phyType, CSL_SerdesInstance instance)
void	CSL_serdesFastSimEnable (uint32_t baseAddr, uint32_t numLanes, CSL_SerdesPhyType phyType)
void	CSL_serdesSetCMUWaitVal (uint32_t baseAddr, uint32_t val)
void	CSL_serdesSetPhanVal (uint32_t baseAddr)
void	CSL_serdesWrite32Mask (uint32_t baseAddr, uint32_t maskVal, uint32_t setVal)
void	CSL_serdesSetLoopback (uint32_t baseAddr, uint32_t laneNum, CSL_SerdesLoopback loopbackMode, CSL_SerdesInstance serdesInstance, CSL_SerdesPhyType phyType)
void	CSL_serdesReleaseReset (uint32_t baseAddr)
CSL_SerdesStatus	CSL_serdesGetPLLStatus (uint32_t baseAddr, uint32_t laneMask, CSL_SerdesInstance serdesInstance)
CSL_SerdesStatus	CSL_serdesGetSigDetStatus (uint32_t baseAddr, uint32_t numLanes, uint8_t laneMask, CSL_SerdesPhyType phyType)
CSL_SerdesStatus	CSL_serdesGetLaneStatus (uint32_t baseAddr, uint32_t numLanes, uint8_t laneMask, CSL_SerdesPhyType phyType)
CSL_SerdesStatus	CSL_serdesConfigStatus (uint32_t baseAddr)
CSL_SerdesLaneEnableStatus	CSL_serdesLaneEnable (CSL_SerdesLaneEnableParams *serdesLaneEnableParams)
CSL_SerdesResult	CSL_serdesRefclkSel (uint32_t mainCtrlMMRbaseAddr, uint32_t baseAddr, CSL_SerdesRefClock refClk, CSL_SerdesRefClockSrc refClkSrc, CSL_SerdesInstance serdesInstance, CSL_SerdesPhyType phyType)
void	CSL_serdesIPSelect (uint32_t mainCtrlMMRbaseAddr, CSL_SerdesPhyType phyType, uint32_t phyInstanceNum, CSL_SerdesInstance serdesInstance, uint32_t serdeslaneNum)
void	CSL_serdesPCIeModeSelect (uint32_t baseAddr, CSL_SerdesPCIeGenType pcieGenType, uint32_t laneNum)
void	CSL_serdesOutClkEn (uint32_t baseAddr, CSL_SerdesRefClock refClock, CSL_SerdesPhyType phyType)

Typedefs
typedef uint32_t	CSL_SerdesInstance
typedef uint32_t	CSL_SerdesRefClock
typedef uint32_t	CSL_SerdesRefClockSrc
typedef uint32_t	CSL_SerdesSSCMode
typedef uint32_t	CSL_SerdesMultilink
typedef uint32_t	CSL_SerdesLinkRate
typedef uint32_t	CSL_SerdesLoopback
typedef uint32_t	CSL_SerdesStatus
typedef uint32_t	CSL_SerdesResult
typedef uint32_t	CSL_SerdesLaneCtrlRate
typedef uint32_t	CSL_SerdesLaneEnableStatus
typedef uint32_t	CSL_SerdesPhyType
typedef uint32_t	CSL_SerdesPCIeGenType
typedef uint32_t	CSL_SerdesForceAttBoost
typedef uint32_t	CSL_SerdesLaneEnableIterationMode
typedef uint32_t	CSL_SerdesOperatingMode
typedef uint32_t	CSL_SerdesEnableRefClkOut
typedef uint32_t	CSL_SerdesInvertTXPolarity
typedef uint32_t	CSL_SerdesInvertRXPolarity

Macros
#define	CSL_SERDES_MAX_LANES   4
#define	CSL_SERDES_MAX_LANES_SIERRA   2
#define	CSL_SERDES_MAX_LANES_TORRENT   4
#define	CSL_SERDES_MAX_TAPS   5
#define	CSL_SERDES_MAX_COMPARATORS   5
#define	CSL_SERDES_TBUS_SIZE   440
#define	CSL_SIERRA_SERDES0   (0U)
#define	CSL_SIERRA_SERDES1   (1U)
#define	CSL_SIERRA_SERDES2   (2U)
#define	CSL_SIERRA_SERDES3   (3U)
#define	CSL_TORRENT_SERDES0   (4U)
#define	CSL_SERDES_REF_CLOCK_19p2M   (0U)
#define	CSL_SERDES_REF_CLOCK_20M   (1U)
#define	CSL_SERDES_REF_CLOCK_24M   (2U)
#define	CSL_SERDES_REF_CLOCK_25M   (3U)
#define	CSL_SERDES_REF_CLOCK_26M   (4U)
#define	CSL_SERDES_REF_CLOCK_27M   (5U)
#define	CSL_SERDES_REF_CLOCK_60M   (6U)
#define	CSL_SERDES_REF_CLOCK_100M   (7U)
#define	CSL_SERDES_REF_CLOCK_122p88M   (8U)
#define	CSL_SERDES_REF_CLOCK_125M   (9U)
#define	CSL_SERDES_REF_CLOCK_153p6M   (10U)
#define	CSL_SERDES_REF_CLOCK_156p25M   (11U)
#define	CSL_SERDES_REF_CLOCK_312p5M   (12U)
#define	CSL_SERDES_REF_CLOCK_INT   (0U)
#define	CSL_SERDES_REF_CLOCK_EXT_NO_SSC   (1U)
#define	CSL_SERDES_REF_CLOCK_EXT_SSC   (2U)
#define	CSL_SERDES_NO_SSC   (0U)
#define	CSL_SERDES_INTERNAL_SSC   (1U)
#define	CSL_SERDES_EXTERNAL_SSC   (2U)
#define	CSL_SERDES_XAUI_SGMII_MULTILINK   (0U)
#define	CSL_SERDES_XAUI_QSGMII_MULTILINK   (1U)
#define	CSL_SERDES_QSGMII_SGMII_MULTILINK   (2U)
#define	CSL_SERDES_QSGMII_USB_MULTILINK   (3U)
#define	CSL_SERDES_PCIe_USB_MULTILINK   (4U)
#define	CSL_SERDES_PCIe_XAUI_MULTILINK   (5U)
#define	CSL_SERDES_PCIe_QSGMII_MULTILINK   (6U)
#define	CSL_SERDES_LINK_RATE_1p25G   (0U)
#define	CSL_SERDES_LINK_RATE_2p7G   (1U)
#define	CSL_SERDES_LINK_RATE_3p125G   (2U)
#define	CSL_SERDES_LINK_RATE_4p9152G   (3U)
#define	CSL_SERDES_LINK_RATE_5G   (4U)
#define	CSL_SERDES_LINK_RATE_5p15625G   (5U)
#define	CSL_SERDES_LINK_RATE_5p4G   (6U)
#define	CSL_SERDES_LINK_RATE_6p144G   (7U)
#define	CSL_SERDES_LINK_RATE_6p25G   (8U)
#define	CSL_SERDES_LINK_RATE_7p3728G   (9U)
#define	CSL_SERDES_LINK_RATE_8G   (10U)
#define	CSL_SERDES_LINK_RATE_8p1G   (11U)
#define	CSL_SERDES_LINK_RATE_9p8304G   (12U)
#define	CSL_SERDES_LINK_RATE_10G   (13U)
#define	CSL_SERDES_LINK_RATE_10p3125G   (14U)
#define	CSL_SERDES_LINK_RATE_12p5G   (15U)
#define	CSL_SERDES_LINK_RATE_16G   (16U)
#define	CSL_SERDES_LOOPBACK_DISABLED   (0U)
#define	CSL_SERDES_LOOPBACK_LINE   (1U)
#define	CSL_SERDES_LOOPBACK_SER   (2U)
#define	CSL_SERDES_LOOPBACK_NEPAR   (3U)
#define	CSL_SERDES_LOOPBACK_FEPAR   (4U)
#define	CSL_SERDES_LOOPBACK_RECOVEREDCLOCK   (5U)
#define	CSL_SERDES_LOOPBACK_TXONLY   (6U)
#define	CSL_SERDES_LOOPBACK_PCS   (7U)
#define	CSL_SERDES_STATUS_PLL_NOT_LOCKED   (0U)
#define	CSL_SERDES_STATUS_PLL_LOCKED   (1U)
#define	CSL_SERDES_NO_ERR   (0U)
#define	CSL_SERDES_INVALID_REF_CLOCK   (1U)
#define	CSL_SERDES_INVALID_LANE_RATE   (2U)
#define	CSL_SERDES_INVALID_NUM_LANES   (3U)
#define	CSL_SERDES_INVALID_PHY_TYPE   (4U)
#define	CSL_SERDES_LANE_FULL_RATE   (0U)
#define	CSL_SERDES_LANE_HALF_RATE   (1U)
#define	CSL_SERDES_LANE_QUARTER_RATE   (2U)
#define	CSL_SERDES_LANE_ENABLE_NO_ERR   (0U)
#define	CSL_SERDES_LANE_ENABLE_INVALID_RATE   (1U)
#define	CSL_SERDES_LANE_ENABLE_PERIPHERAL_BASE_NOT_SET   (2U)
#define	CSL_SERDES_LANE_ENABLE_ITERATION_MODE_NOT_SET   (3U)
#define	CSL_SERDES_LANE_ENABLE_SIG_UNDETECTED   (4U)
#define	CSL_SERDES_PHY_TYPE_PCIe   (0U)
#define	CSL_SERDES_PHY_TYPE_SGMII   (1U)
#define	CSL_SERDES_PHY_TYPE_SGMII_ICSSG   (2U)
#define	CSL_SERDES_PHY_TYPE_QSGMII   (3U)
#define	CSL_SERDES_PHY_TYPE_USB   (4U)
#define	CSL_SERDES_PHY_TYPE_eDP   (5U)
#define	CSL_SERDES_PHY_TYPE_XFI   (6U)
#define	CSL_SERDES_PHY_TYPE_XAUI   (7U)
#define	CSL_SERDES_PCIE_GEN1   (0U)
#define	CSL_SERDES_PCIE_GEN2   (1U)
#define	CSL_SERDES_PCIE_GEN3   (2U)
#define	CSL_SERDES_PCIE_GEN4   (3U)
#define	CSL_SERDES_FORCE_ATT_BOOST_DISABLED   (0U)
#define	CSL_SERDES_FORCE_ATT_BOOST_ENABLED   (1U)
#define	CSL_SERDES_LANE_ENABLE_COMMON_INIT   (1U)
#define	CSL_SERDES_LANE_ENABLE_LANE_INIT   (2U)
#define	CSL_SERDES_LANE_ENABLE_LANE_INIT_NO_WAIT   (3U)
#define	CSL_SERDES_FUNCTIONAL_MODE   (0U)
#define	CSL_SERDES_FUNCTIONAL_MODE_QT   (1U)
#define	CSL_SERDES_FUNCTIONAL_MODE_FAST_SIM   (2U)
#define	CSL_SERDES_DIAGNOSTIC_MODE   (3U)
#define	CSL_SERDES_DIAGNOSTIC_MODE_QT   (4U)
#define	CSL_SERDES_DIAGNOSTIC_MODE_FAST_SIM   (5U)
#define	CSL_SERDES_REFCLK_OUT_DIS   (0U)
#define	CSL_SERDES_REFCLK_OUT_EN   (1U)
#define	CSL_SERDES_INV_TX_POLARITY_DIS   (0U)
#define	CSL_SERDES_INV_TX_POLARITY_EN   (1U)
#define	CSL_SERDES_INV_RX_POLARITY_DIS   (0U)
#define	CSL_SERDES_INV_RX_POLARITY_EN   (1U)

Macro Definition Documentation

CSL_SERDES_MAX_LANES

#define CSL_SERDES_MAX_LANES   4

CSL_SERDES_MAX_LANES_SIERRA

#define CSL_SERDES_MAX_LANES_SIERRA   2

CSL_SERDES_MAX_LANES_TORRENT

#define CSL_SERDES_MAX_LANES_TORRENT   4

CSL_SERDES_MAX_TAPS

#define CSL_SERDES_MAX_TAPS   5

CSL_SERDES_MAX_COMPARATORS

#define CSL_SERDES_MAX_COMPARATORS   5

CSL_SERDES_TBUS_SIZE

#define CSL_SERDES_TBUS_SIZE   440

CSL_SIERRA_SERDES0

#define CSL_SIERRA_SERDES0   (0U)

CSL_SIERRA_SERDES1

#define CSL_SIERRA_SERDES1   (1U)

CSL_SIERRA_SERDES2

#define CSL_SIERRA_SERDES2   (2U)

CSL_SIERRA_SERDES3

#define CSL_SIERRA_SERDES3   (3U)

CSL_TORRENT_SERDES0

#define CSL_TORRENT_SERDES0   (4U)

CSL_SERDES_REF_CLOCK_19p2M

#define CSL_SERDES_REF_CLOCK_19p2M   (0U)

CSL_SERDES_REF_CLOCK_20M

#define CSL_SERDES_REF_CLOCK_20M   (1U)

CSL_SERDES_REF_CLOCK_24M

#define CSL_SERDES_REF_CLOCK_24M   (2U)

CSL_SERDES_REF_CLOCK_25M

#define CSL_SERDES_REF_CLOCK_25M   (3U)

CSL_SERDES_REF_CLOCK_26M

#define CSL_SERDES_REF_CLOCK_26M   (4U)

CSL_SERDES_REF_CLOCK_27M

#define CSL_SERDES_REF_CLOCK_27M   (5U)

CSL_SERDES_REF_CLOCK_60M

#define CSL_SERDES_REF_CLOCK_60M   (6U)

CSL_SERDES_REF_CLOCK_100M

#define CSL_SERDES_REF_CLOCK_100M   (7U)

CSL_SERDES_REF_CLOCK_122p88M

#define CSL_SERDES_REF_CLOCK_122p88M   (8U)

CSL_SERDES_REF_CLOCK_125M

#define CSL_SERDES_REF_CLOCK_125M   (9U)

CSL_SERDES_REF_CLOCK_153p6M

#define CSL_SERDES_REF_CLOCK_153p6M   (10U)

CSL_SERDES_REF_CLOCK_156p25M

#define CSL_SERDES_REF_CLOCK_156p25M   (11U)

CSL_SERDES_REF_CLOCK_312p5M

#define CSL_SERDES_REF_CLOCK_312p5M   (12U)

CSL_SERDES_REF_CLOCK_INT

#define CSL_SERDES_REF_CLOCK_INT   (0U)

CSL_SERDES_REF_CLOCK_EXT_NO_SSC

#define CSL_SERDES_REF_CLOCK_EXT_NO_SSC   (1U)

CSL_SERDES_REF_CLOCK_EXT_SSC

#define CSL_SERDES_REF_CLOCK_EXT_SSC   (2U)

CSL_SERDES_NO_SSC

#define CSL_SERDES_NO_SSC   (0U)

CSL_SERDES_INTERNAL_SSC

#define CSL_SERDES_INTERNAL_SSC   (1U)

CSL_SERDES_EXTERNAL_SSC

#define CSL_SERDES_EXTERNAL_SSC   (2U)

CSL_SERDES_XAUI_SGMII_MULTILINK

#define CSL_SERDES_XAUI_SGMII_MULTILINK   (0U)

CSL_SERDES_XAUI_QSGMII_MULTILINK

#define CSL_SERDES_XAUI_QSGMII_MULTILINK   (1U)

CSL_SERDES_QSGMII_SGMII_MULTILINK

#define CSL_SERDES_QSGMII_SGMII_MULTILINK   (2U)

CSL_SERDES_QSGMII_USB_MULTILINK

#define CSL_SERDES_QSGMII_USB_MULTILINK   (3U)

CSL_SERDES_PCIe_USB_MULTILINK

#define CSL_SERDES_PCIe_USB_MULTILINK   (4U)

CSL_SERDES_PCIe_XAUI_MULTILINK

#define CSL_SERDES_PCIe_XAUI_MULTILINK   (5U)

CSL_SERDES_PCIe_QSGMII_MULTILINK

#define CSL_SERDES_PCIe_QSGMII_MULTILINK   (6U)

CSL_SERDES_LINK_RATE_1p25G

#define CSL_SERDES_LINK_RATE_1p25G   (0U)

CSL_SERDES_LINK_RATE_2p7G

#define CSL_SERDES_LINK_RATE_2p7G   (1U)

CSL_SERDES_LINK_RATE_3p125G

#define CSL_SERDES_LINK_RATE_3p125G   (2U)

CSL_SERDES_LINK_RATE_4p9152G

#define CSL_SERDES_LINK_RATE_4p9152G   (3U)

CSL_SERDES_LINK_RATE_5G

#define CSL_SERDES_LINK_RATE_5G   (4U)

CSL_SERDES_LINK_RATE_5p15625G

#define CSL_SERDES_LINK_RATE_5p15625G   (5U)

CSL_SERDES_LINK_RATE_5p4G

#define CSL_SERDES_LINK_RATE_5p4G   (6U)

CSL_SERDES_LINK_RATE_6p144G

#define CSL_SERDES_LINK_RATE_6p144G   (7U)

CSL_SERDES_LINK_RATE_6p25G

#define CSL_SERDES_LINK_RATE_6p25G   (8U)

CSL_SERDES_LINK_RATE_7p3728G

#define CSL_SERDES_LINK_RATE_7p3728G   (9U)

CSL_SERDES_LINK_RATE_8G

#define CSL_SERDES_LINK_RATE_8G   (10U)

CSL_SERDES_LINK_RATE_8p1G

#define CSL_SERDES_LINK_RATE_8p1G   (11U)

CSL_SERDES_LINK_RATE_9p8304G

#define CSL_SERDES_LINK_RATE_9p8304G   (12U)

CSL_SERDES_LINK_RATE_10G

#define CSL_SERDES_LINK_RATE_10G   (13U)

CSL_SERDES_LINK_RATE_10p3125G

#define CSL_SERDES_LINK_RATE_10p3125G   (14U)

CSL_SERDES_LINK_RATE_12p5G

#define CSL_SERDES_LINK_RATE_12p5G   (15U)

CSL_SERDES_LINK_RATE_16G

#define CSL_SERDES_LINK_RATE_16G   (16U)

CSL_SERDES_LOOPBACK_DISABLED

#define CSL_SERDES_LOOPBACK_DISABLED   (0U)

CSL_SERDES_LOOPBACK_LINE

#define CSL_SERDES_LOOPBACK_LINE   (1U)

CSL_SERDES_LOOPBACK_SER

#define CSL_SERDES_LOOPBACK_SER   (2U)

CSL_SERDES_LOOPBACK_NEPAR

#define CSL_SERDES_LOOPBACK_NEPAR   (3U)

CSL_SERDES_LOOPBACK_FEPAR

#define CSL_SERDES_LOOPBACK_FEPAR   (4U)

CSL_SERDES_LOOPBACK_RECOVEREDCLOCK

#define CSL_SERDES_LOOPBACK_RECOVEREDCLOCK   (5U)

CSL_SERDES_LOOPBACK_TXONLY

#define CSL_SERDES_LOOPBACK_TXONLY   (6U)

CSL_SERDES_LOOPBACK_PCS

#define CSL_SERDES_LOOPBACK_PCS   (7U)

CSL_SERDES_STATUS_PLL_NOT_LOCKED

#define CSL_SERDES_STATUS_PLL_NOT_LOCKED   (0U)

CSL_SERDES_STATUS_PLL_LOCKED

#define CSL_SERDES_STATUS_PLL_LOCKED   (1U)

CSL_SERDES_NO_ERR

#define CSL_SERDES_NO_ERR   (0U)

CSL_SERDES_INVALID_REF_CLOCK

#define CSL_SERDES_INVALID_REF_CLOCK   (1U)

CSL_SERDES_INVALID_LANE_RATE

#define CSL_SERDES_INVALID_LANE_RATE   (2U)

CSL_SERDES_INVALID_NUM_LANES

#define CSL_SERDES_INVALID_NUM_LANES   (3U)

CSL_SERDES_INVALID_PHY_TYPE

#define CSL_SERDES_INVALID_PHY_TYPE   (4U)

CSL_SERDES_LANE_FULL_RATE

#define CSL_SERDES_LANE_FULL_RATE   (0U)

CSL_SERDES_LANE_HALF_RATE

#define CSL_SERDES_LANE_HALF_RATE   (1U)

CSL_SERDES_LANE_QUARTER_RATE

#define CSL_SERDES_LANE_QUARTER_RATE   (2U)

CSL_SERDES_LANE_ENABLE_NO_ERR

#define CSL_SERDES_LANE_ENABLE_NO_ERR   (0U)

CSL_SERDES_LANE_ENABLE_INVALID_RATE

#define CSL_SERDES_LANE_ENABLE_INVALID_RATE   (1U)

CSL_SERDES_LANE_ENABLE_PERIPHERAL_BASE_NOT_SET

#define CSL_SERDES_LANE_ENABLE_PERIPHERAL_BASE_NOT_SET   (2U)

CSL_SERDES_LANE_ENABLE_ITERATION_MODE_NOT_SET

#define CSL_SERDES_LANE_ENABLE_ITERATION_MODE_NOT_SET   (3U)

CSL_SERDES_LANE_ENABLE_SIG_UNDETECTED

#define CSL_SERDES_LANE_ENABLE_SIG_UNDETECTED   (4U)

CSL_SERDES_PHY_TYPE_PCIe

#define CSL_SERDES_PHY_TYPE_PCIe   (0U)

CSL_SERDES_PHY_TYPE_SGMII

#define CSL_SERDES_PHY_TYPE_SGMII   (1U)

CSL_SERDES_PHY_TYPE_SGMII_ICSSG

#define CSL_SERDES_PHY_TYPE_SGMII_ICSSG   (2U)

CSL_SERDES_PHY_TYPE_QSGMII

#define CSL_SERDES_PHY_TYPE_QSGMII   (3U)

CSL_SERDES_PHY_TYPE_USB

#define CSL_SERDES_PHY_TYPE_USB   (4U)

CSL_SERDES_PHY_TYPE_eDP

#define CSL_SERDES_PHY_TYPE_eDP   (5U)

CSL_SERDES_PHY_TYPE_XFI

#define CSL_SERDES_PHY_TYPE_XFI   (6U)

CSL_SERDES_PHY_TYPE_XAUI

#define CSL_SERDES_PHY_TYPE_XAUI   (7U)

CSL_SERDES_PCIE_GEN1

#define CSL_SERDES_PCIE_GEN1   (0U)

CSL_SERDES_PCIE_GEN2

#define CSL_SERDES_PCIE_GEN2   (1U)

CSL_SERDES_PCIE_GEN3

#define CSL_SERDES_PCIE_GEN3   (2U)

CSL_SERDES_PCIE_GEN4

#define CSL_SERDES_PCIE_GEN4   (3U)

CSL_SERDES_FORCE_ATT_BOOST_DISABLED

#define CSL_SERDES_FORCE_ATT_BOOST_DISABLED   (0U)

CSL_SERDES_FORCE_ATT_BOOST_ENABLED

#define CSL_SERDES_FORCE_ATT_BOOST_ENABLED   (1U)

CSL_SERDES_LANE_ENABLE_COMMON_INIT

#define CSL_SERDES_LANE_ENABLE_COMMON_INIT   (1U)

CSL_SERDES_LANE_ENABLE_LANE_INIT

#define CSL_SERDES_LANE_ENABLE_LANE_INIT   (2U)

CSL_SERDES_LANE_ENABLE_LANE_INIT_NO_WAIT

#define CSL_SERDES_LANE_ENABLE_LANE_INIT_NO_WAIT   (3U)

CSL_SERDES_FUNCTIONAL_MODE

#define CSL_SERDES_FUNCTIONAL_MODE   (0U)

CSL_SERDES_FUNCTIONAL_MODE_QT

#define CSL_SERDES_FUNCTIONAL_MODE_QT   (1U)

CSL_SERDES_FUNCTIONAL_MODE_FAST_SIM

#define CSL_SERDES_FUNCTIONAL_MODE_FAST_SIM   (2U)

CSL_SERDES_DIAGNOSTIC_MODE

#define CSL_SERDES_DIAGNOSTIC_MODE   (3U)

CSL_SERDES_DIAGNOSTIC_MODE_QT

#define CSL_SERDES_DIAGNOSTIC_MODE_QT   (4U)

CSL_SERDES_DIAGNOSTIC_MODE_FAST_SIM

#define CSL_SERDES_DIAGNOSTIC_MODE_FAST_SIM   (5U)

CSL_SERDES_REFCLK_OUT_DIS

#define CSL_SERDES_REFCLK_OUT_DIS   (0U)

CSL_SERDES_REFCLK_OUT_EN

#define CSL_SERDES_REFCLK_OUT_EN   (1U)

CSL_SERDES_INV_TX_POLARITY_DIS

#define CSL_SERDES_INV_TX_POLARITY_DIS   (0U)

CSL_SERDES_INV_TX_POLARITY_EN

#define CSL_SERDES_INV_TX_POLARITY_EN   (1U)

CSL_SERDES_INV_RX_POLARITY_DIS

#define CSL_SERDES_INV_RX_POLARITY_DIS   (0U)

CSL_SERDES_INV_RX_POLARITY_EN

#define CSL_SERDES_INV_RX_POLARITY_EN   (1U)

Typedef Documentation

CSL_SerdesInstance

typedef uint32_t CSL_SerdesInstance

CSL_SerdesRefClock

typedef uint32_t CSL_SerdesRefClock

CSL_SerdesRefClockSrc

typedef uint32_t CSL_SerdesRefClockSrc

CSL_SerdesSSCMode

typedef uint32_t CSL_SerdesSSCMode

CSL_SerdesMultilink

typedef uint32_t CSL_SerdesMultilink

CSL_SerdesLinkRate

typedef uint32_t CSL_SerdesLinkRate

CSL_SerdesLoopback

typedef uint32_t CSL_SerdesLoopback

CSL_SerdesStatus

typedef uint32_t CSL_SerdesStatus

CSL_SerdesResult

typedef uint32_t CSL_SerdesResult

CSL_SerdesLaneCtrlRate

typedef uint32_t CSL_SerdesLaneCtrlRate

CSL_SerdesLaneEnableStatus

typedef uint32_t CSL_SerdesLaneEnableStatus

CSL_SerdesPhyType

typedef uint32_t CSL_SerdesPhyType

CSL_SerdesPCIeGenType

typedef uint32_t CSL_SerdesPCIeGenType

CSL_SerdesForceAttBoost

typedef uint32_t CSL_SerdesForceAttBoost

CSL_SerdesLaneEnableIterationMode

typedef uint32_t CSL_SerdesLaneEnableIterationMode

CSL_SerdesOperatingMode

typedef uint32_t CSL_SerdesOperatingMode

CSL_SerdesEnableRefClkOut

typedef uint32_t CSL_SerdesEnableRefClkOut

CSL_SerdesInvertTXPolarity

typedef uint32_t CSL_SerdesInvertTXPolarity

CSL_SerdesInvertRXPolarity

typedef uint32_t CSL_SerdesInvertRXPolarity

Function Documentation

CSL_serdesCycleDelay()

void CSL_serdesCycleDelay

(

uint64_t

count

)

CSL_serdesDisablePllAndLanes()

void CSL_serdesDisablePllAndLanes	(	uint32_t	baseAddr,
		uint32_t	numLanes,
		uint8_t	laneMask
	)

CSL_serdesInvertLaneTXPolarity()

void CSL_serdesInvertLaneTXPolarity	(	uint32_t	baseAddr,
		uint32_t	laneNum
	)

CSL_serdesInvertLaneRXPolarity()

void CSL_serdesInvertLaneRXPolarity	(	uint32_t	baseAddr,
		uint32_t	laneNum
	)

CSL_serdesPorReset()

void CSL_serdesPorReset

(

uint32_t

baseAddr

)

CSL_serdesDisablePLL()

void CSL_serdesDisablePLL	(	uint32_t	baseAddr,
		CSL_SerdesPhyType	phyType
	)

CSL_serdesDisableLanes()

void CSL_serdesDisableLanes	(	uint32_t	baseAddr,
		uint32_t	laneNum,
		uint8_t	laneMask
	)

CSL_serdesEnableLanes()

void CSL_serdesEnableLanes	(	uint32_t	baseAddr,
		uint32_t	laneNum,
		CSL_SerdesPhyType	phyType,
		CSL_SerdesInstance	instance
	)

CSL_serdesFastSimEnable()

void CSL_serdesFastSimEnable	(	uint32_t	baseAddr,
		uint32_t	numLanes,
		CSL_SerdesPhyType	phyType
	)

CSL_serdesSetCMUWaitVal()

void CSL_serdesSetCMUWaitVal	(	uint32_t	baseAddr,
		uint32_t	val
	)

CSL_serdesSetPhanVal()

void CSL_serdesSetPhanVal

(

uint32_t

baseAddr

)

CSL_serdesWrite32Mask()

void CSL_serdesWrite32Mask	(	uint32_t	baseAddr,
		uint32_t	maskVal,
		uint32_t	setVal
	)

CSL_serdesSetLoopback()

void CSL_serdesSetLoopback	(	uint32_t	baseAddr,
		uint32_t	laneNum,
		CSL_SerdesLoopback	loopbackMode,
		CSL_SerdesInstance	serdesInstance,
		CSL_SerdesPhyType	phyType
	)

CSL_serdesReleaseReset()

void CSL_serdesReleaseReset

(

uint32_t

baseAddr

)

CSL_serdesGetPLLStatus()

CSL_SerdesStatus CSL_serdesGetPLLStatus	(	uint32_t	baseAddr,
		uint32_t	laneMask,
		CSL_SerdesInstance	serdesInstance
	)

CSL_serdesGetSigDetStatus()

CSL_SerdesStatus CSL_serdesGetSigDetStatus	(	uint32_t	baseAddr,
		uint32_t	numLanes,
		uint8_t	laneMask,
		CSL_SerdesPhyType	phyType
	)

CSL_serdesGetLaneStatus()

CSL_SerdesStatus CSL_serdesGetLaneStatus	(	uint32_t	baseAddr,
		uint32_t	numLanes,
		uint8_t	laneMask,
		CSL_SerdesPhyType	phyType
	)

CSL_serdesConfigStatus()

CSL_SerdesStatus CSL_serdesConfigStatus

(

uint32_t

baseAddr

)

CSL_serdesLaneEnable()

CSL_SerdesLaneEnableStatus CSL_serdesLaneEnable

(

CSL_SerdesLaneEnableParams *

serdesLaneEnableParams

)

CSL_serdesRefclkSel()

CSL_SerdesResult CSL_serdesRefclkSel	(	uint32_t	mainCtrlMMRbaseAddr,
		uint32_t	baseAddr,
		CSL_SerdesRefClock	refClk,
		CSL_SerdesRefClockSrc	refClkSrc,
		CSL_SerdesInstance	serdesInstance,
		CSL_SerdesPhyType	phyType
	)

CSL_serdesIPSelect()

void CSL_serdesIPSelect	(	uint32_t	mainCtrlMMRbaseAddr,
		CSL_SerdesPhyType	phyType,
		uint32_t	phyInstanceNum,
		CSL_SerdesInstance	serdesInstance,
		uint32_t	serdeslaneNum
	)

CSL_serdesPCIeModeSelect()

void CSL_serdesPCIeModeSelect	(	uint32_t	baseAddr,
		CSL_SerdesPCIeGenType	pcieGenType,
		uint32_t	laneNum
	)

CSL_serdesOutClkEn()

void CSL_serdesOutClkEn	(	uint32_t	baseAddr,
		CSL_SerdesRefClock	refClock,
		CSL_SerdesPhyType	phyType
	)