Ethernet Firmware Datasheet
EthFw Datasheet

Table of Contents

Boot Time

The Ethernet Firmware boot time measurements in the table below show the current status in the TI Processor SDK for J721E/J7200/J784S4. The test setup is:

  • Hardware: TI Jacinto EVM with MAC-to-MAC connection to a second TI EVM.
  • Software: Ethernet Firmware running on Main R5F 0 core 0 at 1 GHz.

Note: It is worth noting that the reported boot time below is not optimized.

Function Description
main()

Starting time is when Ethernet Firmware application is ready to run in main().

Using main() as starting point decouples these measurements from the EthFw binary loading mechanism.

Layer-2 switching active Time elapsed from main() till L2 switching is active.
  • Board and clocks initialization.
  • CPSW has been initialized.
  • One MAC port have been opened (MAC-to-MAC connection).
  • ALE has been configured to route packets at Layer-2.
  • Two MAC ports are linked (MAC-to-MAC connection).
Host port ready for RX/TX Time elapsed from main() till host port is ready for packet transmission and reception.
  • UDMA RX flow has been opened and host port is ready to receive packets.
  • UDMA TX channel has been opened and host port is ready to transmit packets.
TCP/IP stack initialized Time elapsed from main() till TCP/IP stack is initialized.
  • TCP/IP lwIP stack's netif up status callback reports (static) IP address.
gPTP stack initilized Time elapsed from main() till gPTP stack is initialized.
  • gPTP initialization routine is called.
  • This is not the convergence time to achieve time synchronization.
CPSW Proxy Server initialized Time elapsed from main() till CPSW Proxy Server is initialized.
  • ETHFW is ready to receive remote commands from virtual clients.
  • Excludes MPU1_0 late init, late announcement.

The time taken to reach each of the ETHFW boot stages described above is summarized in the following table.

Boot stage J721E J7200 J784S4
main() 0 ms 0 ms 0 ms
Layer-2 switching active 143.94 ms 188.96 ms 112.97 ms
Host port ready for RX/TX 58.54 ms 101.22 ms 29.91 ms
TCP/IP stack initialized 90.71 ms 127.87 ms 30.75 ms
gPTP stack initilized 230.21 ms 190.56 ms 94.39 ms
CPSW Proxy Server initialized 307.27 ms 222.49 ms 132.32 ms

This table doesn't take into account the time between power-on reset (POR) and the Firmware image loaded and made ready to run, as it will be bootloader dependent.

In a MAC-to-PHY scenario, the Layer-2 switching active time is heavily determined by the time taken by the Ethernet PHYs to establish a link with the remote partner. The total Layer-2 switching active time must take into account the link time corresponding to the PHY configuration being used.

Intercore Performance Numbers

Configuration

Hardware Configuration Value
Processing Core R5F0 and A72
Core Frequency 1 GHz
Packet buffer memory DDR
Hardware checksum offload Yes
Scatter-gather TX Yes
Scatter-gather RX No
Software Configuration Value
RTOS FreeRTOS
RTOS application EthFw applicaton
TCP/IP stack lwIP 2.2.0
Linux client tool version iperf v2.0.5

Shared Memory transport

Inter-core network interface allows EthFw to communicate with another core using standard TCP/IP protocol suite. Tap user-space application serves as a medium to facilitate the exchange of Ethernet frames between the A72 Linux and R5_0 (MCU2_0) master core.

Test Setup

Intercore_SharedMem_Performance_Setup.png
Intercore using shared memory transport

Performance Numbers

TCP Performance

Test Bandwidth (Mbps) CPU Load (%)
TCP RX 11.8 27
TCP TX 11.7 26
TCP Bidirectional RX=5.83, TX=5.98 32

UDP Performance

Test Datagram Length = 64B Datagram Length = 256B Datagram Length = 512B Datagram Length = 1470B

Bandwidth (Mbps)

CPU Load (%)

Packet Loss (%)

Bandwidth (Mbps)

CPU Load (%)

Packet Loss (%)

Bandwidth (Mbps)

CPU Load (%)

Packet Loss (%)

Bandwidth (Mbps)

CPU Load (%)

Packet Loss (%)

UDP RX 0.205 14 0.00 1.00 16 0.00 2.0 16 0.00 5.00 18 0.00
0.410 19 0.00 2.00 21 0.00 4.00 22 0.00 8.00 21 0.00
0.511 21 0.00 10.00 24 0.00
UDP RX (Max) 0.512 22 0.32 2.05 22 0.34 4.09 23 0.71 11.8 26 0.57
UDP TX (Max) 15.5 90 0.0038 32.0 82 0.0064 41.4 78 0.003 51.3 80 0.0023

VEPA intercore (only on J784S4)

EthFw provides support to enable VEPA (Virtual Ethernet Port Aggregator) functionality with CPSW capable of multihost data flow. Multihost is a CPSW ALE feature that enables packets to be sent and received on host port.

VEPA or hairpin mode allows the traffic to return to the same port (host port in this case) at which it ingressed on. It enables to forward packets directly to clients via host port increasing intercore virtual ethernet communication performance.

Test Setup

Intercore_VEPA_Performance_Setup.png
Intercore using shared memory transport

Performance Numbers

TCP Performance

Test Bandwidth (Mbps) CPU Load (%)
TCP RX 238 93
TCP TX 237 92
TCP Bidirectional RX=91, TX=106 76

UDP Performance

Test Datagram Length = 64B Datagram Length = 256B Datagram Length = 512B Datagram Length = 1470B

Bandwidth (Mbps)

CPU Load (%)

Packet Loss (%)

Bandwidth (Mbps)

CPU Load (%)

Packet Loss (%)

Bandwidth (Mbps)

CPU Load (%)

Packet Loss (%)

Bandwidth (Mbps)

CPU Load (%)

Packet Loss (%)

UDP RX 5.02 27 0.00 25.3 37 0.00 25.1 27 0.00 25.0 20 0.00
10.0 46 0.00 51.1 79 0.13 50.6 43 0.006 50.0 30 0.00
15.0 90 0.096 102 87 0.16 101 51 0.00
UDP RX (Max) 20.1 91 0.71 67.7 91 0.88 110 90 0.25 193 93 0.11
UDP TX (Max) 28.6 100 0.003 98.3 100 0.02 169 100 0.001 327 100 0.001


Document Revision History

Revision Date Author Description Status -----—
1.1 28 Nov 2023 Misael Lopez Added SDK 9.1 results Approved
1.2 25 Mar 2024 Misael Lopez Added SDK 9.2 results Approved
1.3 26 Jul 2024 Vaibhav Jindal Added SDK 10.0 results Approved