sdl_ip_ecc.h

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#ifndef SDL_ECC_AGGR_H
#define SDL_ECC_AGGR_H

#ifdef __cplusplus
extern "C" {
#endif

#include <stdint.h>
#include <stdbool.h>
#include <src/ip/sdlr_ecc.h>

typedef uint32_t SDL_Ecc_AggrIntrSrc;
#define SDL_ECC_AGGR_INTR_SRC_NONE                      ((uint32_t) 0U)

#define SDL_ECC_AGGR_INTR_SRC_SINGLE_BIT                ((uint32_t) 1U)

#define SDL_ECC_AGGR_INTR_SRC_DOUBLE_BIT                ((uint32_t) 2U)

#define SDL_ECC_ADDR_ERROR_TYPE_SUCCESSIVE_SINGLE_BITS  ((uint32_t) 3U)

#define SDL_ECC_AGGR_INTR_SRC_INVALID                   ((uint32_t) 4U)

#define SDL_ECC_AGGR_SELECT_ERR_CTRL1   (0U)

#define SDL_ECC_AGGR_SELECT_ERR_CTRL2   (1U)

#define SDL_ECC_AGGR_MAX_NUM_RAM_ERR_CTRL   (2U)

#define SDL_ECC_AGGR_SELECT_ERR_STAT1   (0U)

#define SDL_ECC_AGGR_SELECT_ERR_STAT2   (1U)

#define SDL_ECC_AGGR_SELECT_ERR_STAT3   (2U)

#define SDL_ECC_AGGR_MAX_NUM_RAM_ERR_STAT   (3U)

#define SDL_ECC_AGGR_NUM_ENABLE_REGISTERS   (8U)

typedef uint8_t     SDL_ecc_aggrValid;
#define SDL_ECC_AGGR_VALID_TIMEOUT_ERR  (1U)

#define SDL_ECC_AGGR_VALID_PARITY_ERR   (2U)

typedef uint32_t SDL_Ecc_injectPattern;
#define SDL_ECC_AGGR_INJECT_PATTERN_ZERO                 ((uint32_t) 0U)

#define SDL_ECC_AGGR_INJECT_PATTERN_F                    ((uint32_t) 1U)

#define SDL_ECC_AGGR_INJECT_PATTERN_A                    ((uint32_t) 2U)

#define SDL_ECC_AGGR_INJECT_PATTERN_5                    ((uint32_t) 3U)
   /* Max Inject pattern */
#define SDL_ECC_EGGR_INJECT_PATTERN_MAX                  (SDL_ECC_AGGR_INJECT_PATTERN_A)

typedef uint32_t SDL_Ecc_AggrEDCErrorSubType;
#define SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL                  ((uint32_t) 0U)

#define SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT                  ((uint32_t) 1U)

typedef struct
{
    SDL_Ecc_AggrIntrSrc intrSrc;
    uint32_t            eccRow;
    uint32_t            eccBit1;
    uint32_t            eccBit2;
    bool                bOneShotMode;
    bool                bNextRow;
} SDL_Ecc_AggrErrorInfo;

typedef struct
{
    bool                controlRegErr;
    bool                successiveSingleBitErr;
    bool                sVBUSTimeoutErr;
    bool                writebackPend;
    uint32_t             parityErrorCount;
    uint32_t            eccRow;
    uint32_t            eccBit1;
    uint32_t             singleBitErrorCount;
    uint32_t             doubleBitErrorCount;
} SDL_Ecc_AggrEccRamErrorStatusInfo;

typedef struct
{
    SDL_Ecc_AggrIntrSrc intrSrc;
    uint32_t            eccGroup;
    uint32_t            eccBit1;
    uint32_t            eccBit2;
    bool                bNextBit;
    uint32_t             eccPattern;

} SDL_Ecc_AggrEDCInterconnectErrorInfo;


typedef struct
{
    uint32_t            eccGroup;
    uint32_t            eccBit1;
    uint32_t             singleBitErrorCount;
    uint32_t             doubleBitErrorCount;
    uint32_t             injectSingleBitErrorCount;
    uint32_t             injectDoubleBitErrorCount;
} SDL_Ecc_AggrEDCInterconnectErrorStatusInfo;

typedef struct {
    bool                        intrEnableTimeoutErr;
    bool                        intrEnableParityErr;
    SDL_ecc_aggrValid           validCfg;
} SDL_ecc_aggrEnableCtrl;

typedef struct {
    bool                        intrStatusSetTimeoutErr;
    bool                        intrStatusSetParityErr;
    uint32_t                    timeOutCnt;
    uint32_t                    parityCnt;
    SDL_ecc_aggrValid           validCfg;
} SDL_ecc_aggrStatusCtrl;



typedef struct {
    uint32_t REV;
    uint32_t ECC_CTRL;
    uint32_t ECC_ERR_CTRL1;
    uint32_t ECC_ERR_CTRL2;
    uint32_t ECC_SEC_ENABLE_SET_REG[SDL_ECC_AGGR_NUM_ENABLE_REGISTERS];
    uint32_t ECC_SEC_ENABLE_CLR_REG[SDL_ECC_AGGR_NUM_ENABLE_REGISTERS];
    uint32_t ECC_DED_ENABLE_SET_REG[SDL_ECC_AGGR_NUM_ENABLE_REGISTERS];
    uint32_t ECC_DED_ENABLE_CLR_REG[SDL_ECC_AGGR_NUM_ENABLE_REGISTERS];
} SDL_ECC_staticRegs;

int32_t SDL_ecc_aggrGetRevision(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pRev);

int32_t SDL_ecc_aggrGetNumRams(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pNumRams);

int32_t SDL_ecc_aggrReadEccRamReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t *pRegVal);

int32_t SDL_ecc_aggrReadEccRamWrapRevReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t *pRegVal);

int32_t SDL_ecc_aggrReadEccRamCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t *pRegVal);

int32_t SDL_ecc_aggrReadEccRamErrCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t *pRegVal);

int32_t SDL_ecc_aggrReadEccRamErrStatReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t *pRegVal);

int32_t SDL_ecc_aggrWriteEccRamReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t val);

int32_t SDL_ecc_aggrWriteEccRamCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t val);

int32_t SDL_ecc_aggrWriteEccRamErrCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t val);

int32_t SDL_ecc_aggrWriteEccRamErrStatReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t val);

int32_t SDL_ecc_aggrConfigEccRam(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEnable, bool bEccCheck, bool bEnableRMW);

int32_t SDL_ecc_aggrVerifyConfigEccRam(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEnable, bool bEccCheck, bool bEnableRMW);

int32_t SDL_ecc_aggrGetEccRamErrorStatus(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrEccRamErrorStatusInfo *pEccErrorStatus);

int32_t SDL_ecc_aggrForceEccRamError(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, const SDL_Ecc_AggrErrorInfo *pEccForceError);

int32_t SDL_ecc_aggrReadEDCInterconnectReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t *pRegVal );


int32_t SDL_ecc_aggrWriteEDCInterconnectReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t val);

int32_t SDL_ecc_aggrConfigEDCInterconnect(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId,  bool bEccCheck);

int32_t SDL_ecc_aggrVerifyConfigEDCInterconnect(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEccCheck);

int32_t SDL_ecc_aggrGetEDCInterconnectErrorStatus(SDL_ecc_aggrRegs *pEccAggrRegs,
                                                  uint32_t ramId,
                                                  SDL_Ecc_AggrEDCInterconnectErrorStatusInfo *pEccErrorStatus);

int32_t SDL_ecc_aggrForceEDCInterconnectError(SDL_ecc_aggrRegs *pEccAggrRegs,
                                              uint32_t ramId,
                                              const SDL_Ecc_AggrEDCInterconnectErrorInfo *pEccForceError);

int32_t SDL_ecc_aggrAckIntr(SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc);

int32_t SDL_ecc_aggrIsEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend);

int32_t SDL_ecc_aggrSetEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc);

int32_t SDL_ecc_aggrSetEccRamNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, uint32_t numEvents);

int32_t SDL_ecc_aggrClrEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc);

int32_t SDL_ecc_aggrClrEccRamNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, uint32_t numEvents);

int32_t SDL_ecc_aggrIsEDCInterconnectIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend);

int32_t SDL_ecc_aggrSetEDCInterconnectNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs,
                                                   uint32_t ramId,
                                                   SDL_Ecc_AggrIntrSrc intrSrc,
                                                   SDL_Ecc_AggrEDCErrorSubType subType,
                                                   uint32_t numEvents);

int32_t SDL_ecc_aggrClrEDCInterconnectNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs,
                                                   uint32_t ramId,
                                                   SDL_Ecc_AggrIntrSrc intrSrc,
                                                   SDL_Ecc_AggrEDCErrorSubType subType,
                                                   uint32_t numEvents);

int32_t SDL_ecc_aggrIsIntrPending(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend);

int32_t SDL_ecc_aggrIsAnyIntrPending(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool *pIsPend);

int32_t SDL_ecc_aggrEnableIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc);

int32_t SDL_ecc_aggrDisableIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc);

int32_t SDL_ecc_aggrEnableAllIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId);

int32_t SDL_ecc_aggrDisableAllIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId);

int32_t SDL_ecc_aggrEnableIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc);

int32_t SDL_ecc_aggrDisableIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc);

int32_t SDL_ecc_aggrEnableAllIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs);

int32_t SDL_ecc_aggrDisableAllIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs);

int32_t SDL_ecc_aggrReadStaticRegs(SDL_ecc_aggrRegs *pEccAggrRegs, SDL_ECC_staticRegs *pEccAggrStaticRegs);

int32_t SDL_ecc_aggrIntrEnableCtrl(SDL_ecc_aggrRegs *pEccAggrRegs, const SDL_ecc_aggrEnableCtrl *pEnableCtrl);


int32_t SDL_ecc_aggrIntrStatusCtrl(SDL_ecc_aggrRegs *pEccAggrRegs, const SDL_ecc_aggrStatusCtrl *pStatusCtrl);

int32_t SDL_ecc_aggrIntrGetStatus(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_ecc_aggrStatusCtrl *pStatusCtrl);


#ifdef __cplusplus
}
#endif

#endif