98 #define ETH_ISR_VOID (0x00U) 100 #define ETH_ISR_CAT1 (0x01U) 102 #define ETH_ISR_CAT2 (0x02U) 115 #define ETH_START_SEC_ISR_CODE 116 #include "Eth_MemMap.h" 137 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 139 #elif (ETH_ISR_TYPE == ETH_ISR_CAT2) 162 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 164 #elif (ETH_ISR_TYPE == ETH_ISR_CAT2) 187 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 212 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 218 #if (ETH_CTRL_ID_MAX > 0) 238 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 264 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 289 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 314 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 339 #if (STD_ON == ETH_ENABLE_MII_API) 340 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 342 #elif (ETH_ISR_TYPE == ETH_ISR_CAT2) 347 #define ETH_STOP_SEC_ISR_CODE 348 #include "Eth_MemMap.h" void Eth_MdioIrqHdlr(void)
ISR for MDIO interrupts of all controllers.
void Eth_RxIrqPacingHdlr_1(void)
ISR for RX pacing interrupts of the indexed controller 1.
void Eth_TxIrqHdlr_0(void)
ISR for frame transmission interrupts of the indexed controller 0.
void Eth_RxIrqHdlr_0(void)
ISR for frame reception interrupts of the indexed controller 0.
void Eth_TxIrqHdlr_1(void)
ISR for frame transmission interrupts of the indexed controller 1.
void Eth_RxIrqPacingHdlr_0(void)
ISR for RX pacing interrupts of the indexed controller 0.
void Eth_TxIrqPacingHdlr_1(void)
ISR for RX pacing interrupts of the indexed controller 1.
void Eth_RxIrqHdlr_1(void)
ISR for frame reception interrupts of the indexed controller 1.
void Eth_TxIrqPacingHdlr_0(void)
ISR for TX pacing interrupts of the indexed controller 0.