hwa_vpac_viss.h

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#ifndef HWA_VPAC_VISS_H_
#define HWA_VPAC_VISS_H_

#include <VX/vx.h>
#include <VX/vx_kernels.h>

#include <TI/hwa_vpac_viss_fcp.h>

#ifdef VPAC3
#include <TI/hwa_vpac_viss3.h>
#elif defined (VPAC3L)
#include <TI/hwa_vpac_viss3l.h>
#else
#include <TI/hwa_vpac_viss1.h>
#endif

#ifdef __cplusplus
extern "C" {
#endif

#define TIVX_KERNEL_VPAC_VISS_NAME     "com.ti.hwa.vpac_viss"

/*********************************
 *      VPAC_VISS Control Commands
 *********************************/

#define TIVX_VPAC_VISS_CMD_SET_DCC_PARAMS                   (0x30000000u)

#define TIVX_VPAC_VISS_CMD_GET_ERR_STATUS                    (0x30000001u)

#define TIVX_VPAC_VISS_CMD_GET_PSA_STATUS                    (0x30000002u)

/*********************************
 *      VPAC_VISS Defines
 *********************************/

#define TIVX_VPAC_VISS_MAX_H3A_STAT_NUMBYTES            (24576U)

#define TIVX_VPAC_VISS_H3A_OUT_BUFF_ALIGN  (64U)

#define TIVX_VPAC_VISS_H3A_IN_RAW0     (0U)

#define TIVX_VPAC_VISS_H3A_IN_RAW1     (1U)

#define TIVX_VPAC_VISS_H3A_IN_RAW2     (2U)

#define TIVX_VPAC_VISS_H3A_IN_LSC      (3U)
#ifdef VPAC3L

#define TIVX_VPAC_VISS_H3A_IN_PCID     (4U)
#endif

#define TIVX_VPAC_VISS_H3A_MODE_AEWB   (0U)

#define TIVX_VPAC_VISS_H3A_MODE_AF     (1U)

#define TIVX_VPAC_VISS_RAWFE_CFG_ERR_INTR                 (0x1U)

#define TIVX_VPAC_VISS_RAWFE_AEW_PULSE_INTR               (0x2U)

#define TIVX_VPAC_VISS_RAWFE_AF_PULSE_INTR                (0x4U)

#define TIVX_VPAC_VISS_RAWFE_H3A_PULSE_INTR               (0x8U)

#define TIVX_VPAC_VISS_RAWFE_H3A_BUF_OVRFLOW_PULSE_INTR   (0x10U)

#define TIVX_VPAC_VISS_NSF4V_LINEMEM_CFG_ERR_INTR         (0x20U)

#define TIVX_VPAC_VISS_NSF4V_HBLANK_ERR_INTR              (0x40U)

#define TIVX_VPAC_VISS_NSF4V_VBLANK_ERR_INTR              (0x80U)

#define TIVX_VPAC_VISS_GLBCE_CFG_ERR_INTR                 (0x100U)

#define TIVX_VPAC_VISS_GLBCE_FILT_START_INTR              (0x200U)

#define TIVX_VPAC_VISS_GLBCE_FILT_DONE_INTR               (0x400U)

#define TIVX_VPAC_VISS_GLBCE_HSYNC_ERR_INTR               (0x800U)

#define TIVX_VPAC_VISS_GLBCE_VSYNC_ERR_INTR               (0x1000U)

#define TIVX_VPAC_VISS_GLBCE_VP_ERR_INTR                  (0x2000U)

#define TIVX_VPAC_VISS_FCFA_CFG_ERR_INTR                  (0x4000U)

#define TIVX_VPAC_VISS_FCC_CFG_ERR_INTR                   (0x8000U)

#define TIVX_VPAC_VISS_FCC_OUTIF_OVF_ERR_INTR             (0x10000U)

#define TIVX_VPAC_VISS_FCC_HIST_READ_ERR_INTR             (0x20000U)

#define TIVX_VPAC_VISS_EE_CFG_ERR                         (0x40000U)

#define TIVX_VPAC_VISS_EE_SYNCOVF_ERR                     (0x80000U)

#define TIVX_VPAC_VISS_LSE_FR_DONE_EVT_INTR               (0x100000U)

#define TIVX_VPAC_VISS_LSE_SL2_RD_ERR_INTR                (0x200000U)

#define TIVX_VPAC_VISS_LSE_SL2_WR_ERR_INTR                (0x400000U)

#define TIVX_VPAC_VISS_LSE_CAL_VP_ERR_INTR                (0x800000U)

#define TIVX_VPAC_VISS_LSE_OUT_FR_START_EVT_INTR          (0x1000000U)
#if defined(VPAC3) || defined(VPAC3L)

#define TIVX_VPAC_VISS_RAWFE_X_Y_POINTER                  (0x2000000U)

#define TIVX_VPAC_VISS_CR_CFG_ERR                         (0x4000000U)

#endif
#if defined(VPAC3L)
#define TIVX_VPAC_VISS_RAWFE_DPC_STATS_READ_ERR           (0x8000000U)
#endif

#define TIVX_VPAC_VISS_WDTIMER_ERR                       (0x40000000U)

/*********************************
 *      VPAC_VISS STRUCTURES
 *********************************/

typedef struct {
    uint32_t                    h3a_source_data;
    uint32_t                    exposure_time;
    uint32_t                    analog_gain;
    uint32_t                    ae_valid;
    uint32_t                    ae_converged;
    uint32_t                    digital_gain;
    uint32_t                    wb_gains[4];
    int32_t                     wb_offsets[4];
    uint32_t                    color_temperature;
    uint32_t                    awb_valid;
    uint32_t                    awb_converged;
} tivx_ae_awb_params_t;

typedef struct
{
    uint16_t                    aewwin1_WINH;
    uint16_t                    aewwin1_WINW;
    uint16_t                    aewwin1_WINVC;
    uint16_t                    aewwin1_WINHC;
    uint16_t                    aewsubwin_AEWINCV;
    uint16_t                    aewsubwin_AEWINCH;
} tivx_h3a_aew_config;

typedef struct {
    uint32_t                    aew_af_mode;
    uint32_t                    h3a_source_data;
    tivx_h3a_aew_config         aew_config;
    uint32_t                    cpu_id;
    uint32_t                    channel_id;
    uint32_t                    size;
    uint32_t                    resv[(TIVX_VPAC_VISS_H3A_OUT_BUFF_ALIGN-(sizeof(tivx_h3a_aew_config)+20U))/4U ];
    uint8_t                     data[TIVX_VPAC_VISS_MAX_H3A_STAT_NUMBYTES];
} tivx_h3a_data_t;

/*********************************
 *      Function Prototypes
 *********************************/

void tivxRegisterHwaTargetVpacVissKernels(void);

void tivxUnRegisterHwaTargetVpacVissKernels(void);

void tivx_vpac_viss_params_init(tivx_vpac_viss_params_t *prms);

void tivx_h3a_data_init(tivx_h3a_data_t *prms);

void tivx_ae_awb_params_init(tivx_ae_awb_params_t *prms);

void tivx_h3a_aew_config_init(tivx_h3a_aew_config *prms);


#ifdef __cplusplus
}
#endif

#endif /* HWA_VPAC_VISS_H_ */