AM62PX Interrupt Management Device Descriptions

Introduction

This chapter provides information on the Interrupt Management devices in the AM62PX SoC. Some System Firmware TISCI messages take device specific inputs. This chapter provides information on the valid values for Interrupt Management TISCI message parameters.

Interrupt Router Device IDs

Some System Firmware TISCI message APIs require the Interrupt Router device ID be provided as part of the request. Based on AM62PX Device IDs these are the valid Interrupt Router device IDs.

Interrupt Router Device Name Interrupt Router Device ID
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6

MAIN_GPIOMUX_INTROUTER0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Input Index Source Name Source Interface Source Index
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 0 AM62PX_DEV_GPIO0 gpio 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 1 AM62PX_DEV_GPIO0 gpio 1
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 2 AM62PX_DEV_GPIO0 gpio 2
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 3 AM62PX_DEV_GPIO0 gpio 3
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 4 AM62PX_DEV_GPIO0 gpio 4
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 5 AM62PX_DEV_GPIO0 gpio 5
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 6 AM62PX_DEV_GPIO0 gpio 6
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 7 AM62PX_DEV_GPIO0 gpio 7
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 8 AM62PX_DEV_GPIO0 gpio 8
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 9 AM62PX_DEV_GPIO0 gpio 9
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 10 AM62PX_DEV_GPIO0 gpio 10
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 11 AM62PX_DEV_GPIO0 gpio 11
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 12 AM62PX_DEV_GPIO0 gpio 12
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 13 AM62PX_DEV_GPIO0 gpio 13
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 14 AM62PX_DEV_GPIO0 gpio 14
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 15 AM62PX_DEV_GPIO0 gpio 15
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 16 AM62PX_DEV_GPIO0 gpio 16
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 17 AM62PX_DEV_GPIO0 gpio 17
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 18 AM62PX_DEV_GPIO0 gpio 18
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 19 AM62PX_DEV_GPIO0 gpio 19
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 20 AM62PX_DEV_GPIO0 gpio 20
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 21 AM62PX_DEV_GPIO0 gpio 21
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 22 AM62PX_DEV_GPIO0 gpio 22
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 23 AM62PX_DEV_GPIO0 gpio 23
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 24 AM62PX_DEV_GPIO0 gpio 24
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 25 AM62PX_DEV_GPIO0 gpio 25
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 26 AM62PX_DEV_GPIO0 gpio 26
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 27 AM62PX_DEV_GPIO0 gpio 27
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 28 AM62PX_DEV_GPIO0 gpio 28
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 29 AM62PX_DEV_GPIO0 gpio 29
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 30 AM62PX_DEV_GPIO0 gpio 30
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 31 AM62PX_DEV_GPIO0 gpio 31
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 32 AM62PX_DEV_GPIO0 gpio 32
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 33 AM62PX_DEV_GPIO0 gpio 33
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 34 AM62PX_DEV_GPIO0 gpio 34
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 35 AM62PX_DEV_GPIO0 gpio 35
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 36 AM62PX_DEV_GPIO0 gpio 36
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 37 AM62PX_DEV_GPIO0 gpio 37
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 38 AM62PX_DEV_GPIO0 gpio 38
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 39 AM62PX_DEV_GPIO0 gpio 39
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 40 AM62PX_DEV_GPIO0 gpio 40
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 41 AM62PX_DEV_GPIO0 gpio 41
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 42 AM62PX_DEV_GPIO0 gpio 42
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 43 AM62PX_DEV_GPIO0 gpio 43
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 44 AM62PX_DEV_GPIO0 gpio 44
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 45 AM62PX_DEV_GPIO0 gpio 45
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 46 AM62PX_DEV_GPIO0 gpio 46
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 47 AM62PX_DEV_GPIO0 gpio 47
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 48 AM62PX_DEV_GPIO0 gpio 48
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 49 AM62PX_DEV_GPIO0 gpio 49
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 50 AM62PX_DEV_GPIO0 gpio 50
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 51 AM62PX_DEV_GPIO0 gpio 51
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 52 AM62PX_DEV_GPIO0 gpio 52
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 53 AM62PX_DEV_GPIO0 gpio 53
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 54 AM62PX_DEV_GPIO0 gpio 54
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 55 AM62PX_DEV_GPIO0 gpio 55
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 56 AM62PX_DEV_GPIO0 gpio 56
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 57 AM62PX_DEV_GPIO0 gpio 57
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 58 AM62PX_DEV_GPIO0 gpio 58
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 59 AM62PX_DEV_GPIO0 gpio 59
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 60 AM62PX_DEV_GPIO0 gpio 60
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 61 AM62PX_DEV_GPIO0 gpio 61
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 62 AM62PX_DEV_GPIO0 gpio 62
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 63 AM62PX_DEV_GPIO0 gpio 63
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 64 AM62PX_DEV_GPIO0 gpio 64
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 65 AM62PX_DEV_GPIO0 gpio 65
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 66 AM62PX_DEV_GPIO0 gpio 66
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 67 AM62PX_DEV_GPIO0 gpio 67
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 68 AM62PX_DEV_GPIO0 gpio 68
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 69 AM62PX_DEV_GPIO0 gpio 69
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 70 AM62PX_DEV_GPIO0 gpio 70
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 71 AM62PX_DEV_GPIO0 gpio 71
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 72 AM62PX_DEV_GPIO0 gpio 72
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 73 AM62PX_DEV_GPIO0 gpio 73
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 74 AM62PX_DEV_GPIO0 gpio 74
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 75 AM62PX_DEV_GPIO0 gpio 75
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 76 AM62PX_DEV_GPIO0 gpio 76
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 77 AM62PX_DEV_GPIO0 gpio 77
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 78 AM62PX_DEV_GPIO0 gpio 78
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 79 AM62PX_DEV_GPIO0 gpio 79
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 80 AM62PX_DEV_GPIO0 gpio 80
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 81 AM62PX_DEV_GPIO0 gpio 81
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 82 AM62PX_DEV_GPIO0 gpio 82
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 83 AM62PX_DEV_GPIO0 gpio 83
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 84 AM62PX_DEV_GPIO0 gpio 84
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 85 AM62PX_DEV_GPIO0 gpio 85
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 86 AM62PX_DEV_GPIO0 gpio 86
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 87 AM62PX_DEV_GPIO0 gpio 87
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 88 AM62PX_DEV_GPIO0 gpio 88
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 89 AM62PX_DEV_GPIO0 gpio 89
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 90 AM62PX_DEV_GPIO1 gpio 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 91 AM62PX_DEV_GPIO1 gpio 1
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 92 AM62PX_DEV_GPIO1 gpio 2
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 93 AM62PX_DEV_GPIO1 gpio 3
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 94 AM62PX_DEV_GPIO1 gpio 4
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 95 AM62PX_DEV_GPIO1 gpio 5
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 96 AM62PX_DEV_GPIO1 gpio 6
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 97 AM62PX_DEV_GPIO1 gpio 7
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 98 AM62PX_DEV_GPIO1 gpio 8
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 99 AM62PX_DEV_GPIO1 gpio 9
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 100 AM62PX_DEV_GPIO1 gpio 10
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 101 AM62PX_DEV_GPIO1 gpio 11
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 102 AM62PX_DEV_GPIO1 gpio 12
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 103 AM62PX_DEV_GPIO1 gpio 13
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 104 AM62PX_DEV_GPIO1 gpio 14
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 105 AM62PX_DEV_GPIO1 gpio 15
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 106 AM62PX_DEV_GPIO1 gpio 16
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 107 AM62PX_DEV_GPIO1 gpio 17
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 108 AM62PX_DEV_GPIO1 gpio 18
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 109 AM62PX_DEV_GPIO1 gpio 19
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 110 AM62PX_DEV_GPIO1 gpio 20
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 111 AM62PX_DEV_GPIO1 gpio 21
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 112 AM62PX_DEV_GPIO1 gpio 22
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 113 AM62PX_DEV_GPIO1 gpio 23
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 114 AM62PX_DEV_GPIO1 gpio 24
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 115 AM62PX_DEV_GPIO1 gpio 25
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 116 AM62PX_DEV_GPIO1 gpio 26
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 117 AM62PX_DEV_GPIO1 gpio 27
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 118 AM62PX_DEV_GPIO1 gpio 28
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 119 AM62PX_DEV_GPIO1 gpio 29
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 120 AM62PX_DEV_GPIO1 gpio 30
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 121 AM62PX_DEV_GPIO1 gpio 31
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 122 AM62PX_DEV_GPIO1 gpio 32
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 123 AM62PX_DEV_GPIO1 gpio 33
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 124 AM62PX_DEV_GPIO1 gpio 34
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 125 AM62PX_DEV_GPIO1 gpio 35
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 126 AM62PX_DEV_GPIO1 gpio 36
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 127 AM62PX_DEV_GPIO1 gpio 37
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 128 AM62PX_DEV_GPIO1 gpio 38
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 129 AM62PX_DEV_GPIO1 gpio 39
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 130 AM62PX_DEV_GPIO1 gpio 40
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 131 AM62PX_DEV_GPIO1 gpio 41
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 132 AM62PX_DEV_GPIO1 gpio 42
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 133 AM62PX_DEV_GPIO1 gpio 43
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 134 AM62PX_DEV_GPIO1 gpio 44
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 135 AM62PX_DEV_GPIO1 gpio 45
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 136 AM62PX_DEV_GPIO1 gpio 46
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 137 AM62PX_DEV_GPIO1 gpio 47
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 138 AM62PX_DEV_GPIO1 gpio 48
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 139 AM62PX_DEV_GPIO1 gpio 49
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 140 AM62PX_DEV_GPIO1 gpio 50
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 141 AM62PX_DEV_GPIO1 gpio 51
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 142 AM62PX_DEV_GPIO1 gpio 52
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 143 AM62PX_DEV_GPIO1 gpio 53
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 144 AM62PX_DEV_GPIO1 gpio 54
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 145 AM62PX_DEV_GPIO1 gpio 55
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 146 AM62PX_DEV_GPIO1 gpio 56
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 147 AM62PX_DEV_GPIO1 gpio 57
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 148 AM62PX_DEV_GPIO1 gpio 58
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 149 AM62PX_DEV_GPIO1 gpio 59
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 150 AM62PX_DEV_GPIO1 gpio 60
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 151 AM62PX_DEV_GPIO1 gpio 61
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 152 AM62PX_DEV_GPIO1 gpio 62
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 153 AM62PX_DEV_GPIO1 gpio 63
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 154 AM62PX_DEV_GPIO1 gpio 64
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 155 AM62PX_DEV_GPIO1 gpio 65
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 156 AM62PX_DEV_GPIO1 gpio 66
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 157 AM62PX_DEV_GPIO1 gpio 67
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 158 AM62PX_DEV_GPIO1 gpio 68
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 159 AM62PX_DEV_GPIO1 gpio 69
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 160 AM62PX_DEV_GPIO1 gpio 70
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 161 AM62PX_DEV_GPIO1 gpio 71
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 162 AM62PX_DEV_TIMER0 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 163 AM62PX_DEV_TIMER1 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 164 AM62PX_DEV_TIMER2 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 165 AM62PX_DEV_TIMER3 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 166 AM62PX_DEV_TIMER4 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 167 AM62PX_DEV_TIMER5 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 168 AM62PX_DEV_TIMER6 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 169 AM62PX_DEV_TIMER7 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 170 AM62PX_DEV_MCU_TIMER0 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 171 AM62PX_DEV_MCU_TIMER1 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 172 AM62PX_DEV_MCU_TIMER2 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 173 AM62PX_DEV_MCU_TIMER3 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 174 AM62PX_DEV_WKUP_TIMER0 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 175 AM62PX_DEV_WKUP_TIMER1 timer_pwm 0
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 176 AM62PX_DEV_GPIO0 gpio 90
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 177 AM62PX_DEV_GPIO0 gpio 91
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 178 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 179 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 180 AM62PX_DEV_GPIO1 gpio_bank 72
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 181 AM62PX_DEV_GPIO1 gpio_bank 73
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 182 AM62PX_DEV_GPIO1 gpio_bank 74
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 183 AM62PX_DEV_GPIO1 gpio_bank 75
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 184 AM62PX_DEV_GPIO1 gpio_bank 76
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 185 AM62PX_DEV_GPIO1 gpio_bank 77
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 186 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 187 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 188 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 189 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 190 AM62PX_DEV_GPIO0 gpio_bank 92
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 191 AM62PX_DEV_GPIO0 gpio_bank 93
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 192 AM62PX_DEV_GPIO0 gpio_bank 94
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 193 AM62PX_DEV_GPIO0 gpio_bank 95
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 194 AM62PX_DEV_GPIO0 gpio_bank 96
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 195 AM62PX_DEV_GPIO0 gpio_bank 97
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 196 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 197 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 198 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 199 Use TRM - Not managed by TISCI    

MAIN_GPIOMUX_INTROUTER0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Output Index Destination Name Destination Interface Destination Index
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 0 AM62PX_DEV_GICSS0 spi 32
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 32
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 0 AM62PX_DEV_HSM0 nvic 208
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 1 AM62PX_DEV_GICSS0 spi 33
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 33
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 1 AM62PX_DEV_HSM0 nvic 209
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 2 AM62PX_DEV_GICSS0 spi 34
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 34
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 2 AM62PX_DEV_HSM0 nvic 210
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 3 AM62PX_DEV_GICSS0 spi 35
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 35
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 3 AM62PX_DEV_HSM0 nvic 211
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 4 AM62PX_DEV_GICSS0 spi 36
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 36
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 4 AM62PX_DEV_HSM0 nvic 212
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 5 AM62PX_DEV_GICSS0 spi 37
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 37
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 5 AM62PX_DEV_HSM0 nvic 213
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 6 AM62PX_DEV_GICSS0 spi 38
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 38
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 6 AM62PX_DEV_HSM0 nvic 214
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 7 AM62PX_DEV_GICSS0 spi 39
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 39
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 7 AM62PX_DEV_HSM0 nvic 215
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 8 AM62PX_DEV_GICSS0 spi 40
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 40
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 9 AM62PX_DEV_GICSS0 spi 41
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 41
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 10 AM62PX_DEV_GICSS0 spi 42
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 42
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 11 AM62PX_DEV_GICSS0 spi 43
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 43
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 12 AM62PX_DEV_GICSS0 spi 44
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 44
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 13 AM62PX_DEV_GICSS0 spi 45
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 45
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 14 AM62PX_DEV_GICSS0 spi 46
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 46
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 15 AM62PX_DEV_GICSS0 spi 47
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 47
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 16 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 17 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 18 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 19 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 20 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 21 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 22 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 24
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 23 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 25
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 24 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 16
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 25 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 17
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 26 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 18
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 27 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 19
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 28 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 20
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 29 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 21
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 30 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 22
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 31 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 23
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 32 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 33 Use TRM - Not managed by TISCI    
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 34 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 32
AM62PX_DEV_MAIN_GPIOMUX_INTROUTER0 3 35 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 33

WKUP_MCU_GPIOMUX_INTROUTER0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Input Index Source Name Source Interface Source Index
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 0 AM62PX_DEV_MCU_GPIO0 gpio 0
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 1 AM62PX_DEV_MCU_GPIO0 gpio 1
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 2 AM62PX_DEV_MCU_GPIO0 gpio 2
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 3 AM62PX_DEV_MCU_GPIO0 gpio 3
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 4 AM62PX_DEV_MCU_GPIO0 gpio 4
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 5 AM62PX_DEV_MCU_GPIO0 gpio 5
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 6 AM62PX_DEV_MCU_GPIO0 gpio 6
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 7 AM62PX_DEV_MCU_GPIO0 gpio 7
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 8 AM62PX_DEV_MCU_GPIO0 gpio 8
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 9 AM62PX_DEV_MCU_GPIO0 gpio 9
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 10 AM62PX_DEV_MCU_GPIO0 gpio 10
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 11 AM62PX_DEV_MCU_GPIO0 gpio 11
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 12 AM62PX_DEV_MCU_GPIO0 gpio 12
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 13 AM62PX_DEV_MCU_GPIO0 gpio 13
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 14 AM62PX_DEV_MCU_GPIO0 gpio 14
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 15 AM62PX_DEV_MCU_GPIO0 gpio 15
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 16 AM62PX_DEV_MCU_GPIO0 gpio 16
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 17 AM62PX_DEV_MCU_GPIO0 gpio 17
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 18 AM62PX_DEV_MCU_GPIO0 gpio 18
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 19 AM62PX_DEV_MCU_GPIO0 gpio 19
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 20 AM62PX_DEV_MCU_GPIO0 gpio 20
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 21 AM62PX_DEV_MCU_GPIO0 gpio 21
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 22 AM62PX_DEV_MCU_GPIO0 gpio 22
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 23 AM62PX_DEV_MCU_GPIO0 gpio 23
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 24 Use TRM - Not managed by TISCI    
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 25 Use TRM - Not managed by TISCI    
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 26 Use TRM - Not managed by TISCI    
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 27 Use TRM - Not managed by TISCI    
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 28 Use TRM - Not managed by TISCI    
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 29 Use TRM - Not managed by TISCI    
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 30 AM62PX_DEV_MCU_GPIO0 gpio_bank 24
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 31 AM62PX_DEV_MCU_GPIO0 gpio_bank 25

WKUP_MCU_GPIOMUX_INTROUTER0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Output Index Destination Name Destination Interface Destination Index
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 0 AM62PX_DEV_GICSS0 spi 104
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 104
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 1 AM62PX_DEV_GICSS0 spi 105
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 105
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 2 AM62PX_DEV_GICSS0 spi 106
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 106
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 3 AM62PX_DEV_GICSS0 spi 107
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 107
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 4 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 104
      AM62PX_DEV_HSM0 nvic 78
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 5 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 105
      AM62PX_DEV_HSM0 nvic 79
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 6 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 106
      AM62PX_DEV_HSM0 nvic 80
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 7 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 107
      AM62PX_DEV_HSM0 nvic 81
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 8 AM62PX_DEV_WKUP_ESM0 esm_pls_event0 88
      AM62PX_DEV_WKUP_ESM0 esm_pls_event1 92
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 8 AM62PX_DEV_WKUP_ESM0 esm_pls_event2 96
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 9 AM62PX_DEV_WKUP_ESM0 esm_pls_event0 89
      AM62PX_DEV_WKUP_ESM0 esm_pls_event1 93
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 9 AM62PX_DEV_WKUP_ESM0 esm_pls_event2 97
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 10 AM62PX_DEV_WKUP_ESM0 esm_pls_event0 90
      AM62PX_DEV_WKUP_ESM0 esm_pls_event1 94
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 10 AM62PX_DEV_WKUP_ESM0 esm_pls_event2 98
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 11 AM62PX_DEV_WKUP_ESM0 esm_pls_event0 91
      AM62PX_DEV_WKUP_ESM0 esm_pls_event1 95
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 11 AM62PX_DEV_WKUP_ESM0 esm_pls_event2 99
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 12 Use TRM - Not managed by TISCI    
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 13 Use TRM - Not managed by TISCI    
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 14 Use TRM - Not managed by TISCI    
AM62PX_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5 15 Use TRM - Not managed by TISCI    

TIMESYNC_EVENT_INTROUTER0 Interrupt Router Input Sources

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Input Index Source Name Source Interface Source Index
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 0 AM62PX_DEV_TIMER0 timer_pwm 0
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 1 AM62PX_DEV_TIMER1 timer_pwm 0
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 2 AM62PX_DEV_TIMER2 timer_pwm 0
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 3 AM62PX_DEV_TIMER3 timer_pwm 0
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 4 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 5 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 6 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 7 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 8 AM62PX_DEV_EPWM0 epwm_synco_o 0
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 9 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 10 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 11 AM62PX_DEV_WKUP_GTC0 gtc_push_event 0
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 12 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 13 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 14 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 15 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 16 AM62PX_DEV_CPSW0 cpts_genf0 1
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 17 AM62PX_DEV_CPSW0 cpts_genf1 2
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 18 AM62PX_DEV_CPSW0 cpts_sync 3
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 19 Use TRM - Not managed by TISCI    

TIMESYNC_EVENT_INTROUTER0 Interrupt Router Output Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IR Name IR Device ID IR Output Index Destination Name Destination Interface Destination Index
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 0 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 8
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 1 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 9
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 2 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 10
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 3 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 11
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 4 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 12
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 5 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 13
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 6 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 14
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 7 AM62PX_DEV_DMASS0_INTAGGR_0 intaggr_levi_pend 15
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 8 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 9 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 10 AM62PX_DEV_CPSW0 cpts_hw1_push 0
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 11 AM62PX_DEV_CPSW0 cpts_hw2_push 1
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 12 AM62PX_DEV_CPSW0 cpts_hw3_push 2
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 13 AM62PX_DEV_CPSW0 cpts_hw4_push 3
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 14 AM62PX_DEV_CPSW0 cpts_hw5_push 4
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 15 AM62PX_DEV_CPSW0 cpts_hw6_push 5
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 16 AM62PX_DEV_CPSW0 cpts_hw7_push 6
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 17 AM62PX_DEV_CPSW0 cpts_hw8_push 7
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 18 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 19 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 20 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 21 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 22 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 23 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 24 Use TRM - Not managed by TISCI    
AM62PX_DEV_TIMESYNC_EVENT_INTROUTER0 6 25 Use TRM - Not managed by TISCI    

Interrupt Aggregator Device IDs

Some System Firmware TISCI message APIs require the Interrupt Aggregator device ID be provided as part of the request. Based on AM62PX Device IDs these are the valid Interrupt Aggregator device IDs.

Interrupt Aggregator Device Name Interrupt Aggregator Device ID
AM62PX_DEV_DMASS0_INTAGGR_0 28
AM62PX_DEV_DMASS1_INTAGGR_0 200

Interrupt Aggregator Virtual Interrupts

This section describes Interrupt Aggregator virtual interrupts. The virtual interrupts are used in interrupt management based TISCI messages.

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

Interrupt Aggregator Name Virtual Interrupt Range
AM62PX_DEV_DMASS0_INTAGGR_0 (RESERVED BY SYSTEM FIRMWARE) 0 to 4
AM62PX_DEV_DMASS0_INTAGGR_0 5 to 39
AM62PX_DEV_DMASS0_INTAGGR_0 (RESERVED BY SYSTEM FIRMWARE) 40 to 43
AM62PX_DEV_DMASS0_INTAGGR_0 44 to 135
AM62PX_DEV_DMASS0_INTAGGR_0 (RESERVED BY SYSTEM FIRMWARE) 136 to 139
AM62PX_DEV_DMASS0_INTAGGR_0 140 to 183
AM62PX_DEV_DMASS1_INTAGGR_0 0 to 7

DMASS0_INTAGGR_0 Interrupt Aggregator Virtual Interrupt Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IA Name IA Device ID IA VINT Index Destination Name Destination Interface Destination Index
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 0 AM62PX_DEV_GICSS0 spi 64
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 1 AM62PX_DEV_GICSS0 spi 65
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 2 AM62PX_DEV_GICSS0 spi 66
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 3 AM62PX_DEV_GICSS0 spi 67
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 4 AM62PX_DEV_GICSS0 spi 68
AM62PX_DEV_DMASS0_INTAGGR_0 28 5 AM62PX_DEV_GICSS0 spi 69
AM62PX_DEV_DMASS0_INTAGGR_0 28 6 AM62PX_DEV_GICSS0 spi 70
AM62PX_DEV_DMASS0_INTAGGR_0 28 7 AM62PX_DEV_GICSS0 spi 71
AM62PX_DEV_DMASS0_INTAGGR_0 28 8 AM62PX_DEV_GICSS0 spi 72
AM62PX_DEV_DMASS0_INTAGGR_0 28 9 AM62PX_DEV_GICSS0 spi 73
AM62PX_DEV_DMASS0_INTAGGR_0 28 10 AM62PX_DEV_GICSS0 spi 74
AM62PX_DEV_DMASS0_INTAGGR_0 28 11 AM62PX_DEV_GICSS0 spi 75
AM62PX_DEV_DMASS0_INTAGGR_0 28 12 AM62PX_DEV_GICSS0 spi 76
AM62PX_DEV_DMASS0_INTAGGR_0 28 13 AM62PX_DEV_GICSS0 spi 77
AM62PX_DEV_DMASS0_INTAGGR_0 28 14 AM62PX_DEV_GICSS0 spi 78
AM62PX_DEV_DMASS0_INTAGGR_0 28 15 AM62PX_DEV_GICSS0 spi 79
AM62PX_DEV_DMASS0_INTAGGR_0 28 16 AM62PX_DEV_GICSS0 spi 80
AM62PX_DEV_DMASS0_INTAGGR_0 28 17 AM62PX_DEV_GICSS0 spi 81
AM62PX_DEV_DMASS0_INTAGGR_0 28 18 AM62PX_DEV_GICSS0 spi 82
AM62PX_DEV_DMASS0_INTAGGR_0 28 19 AM62PX_DEV_GICSS0 spi 83
AM62PX_DEV_DMASS0_INTAGGR_0 28 20 AM62PX_DEV_GICSS0 spi 84
AM62PX_DEV_DMASS0_INTAGGR_0 28 21 AM62PX_DEV_GICSS0 spi 85
AM62PX_DEV_DMASS0_INTAGGR_0 28 22 AM62PX_DEV_GICSS0 spi 86
AM62PX_DEV_DMASS0_INTAGGR_0 28 23 AM62PX_DEV_GICSS0 spi 87
AM62PX_DEV_DMASS0_INTAGGR_0 28 24 AM62PX_DEV_GICSS0 spi 88
AM62PX_DEV_DMASS0_INTAGGR_0 28 25 AM62PX_DEV_GICSS0 spi 89
AM62PX_DEV_DMASS0_INTAGGR_0 28 26 AM62PX_DEV_GICSS0 spi 90
AM62PX_DEV_DMASS0_INTAGGR_0 28 27 AM62PX_DEV_GICSS0 spi 91
AM62PX_DEV_DMASS0_INTAGGR_0 28 28 AM62PX_DEV_GICSS0 spi 92
AM62PX_DEV_DMASS0_INTAGGR_0 28 29 AM62PX_DEV_GICSS0 spi 93
AM62PX_DEV_DMASS0_INTAGGR_0 28 30 AM62PX_DEV_GICSS0 spi 94
AM62PX_DEV_DMASS0_INTAGGR_0 28 31 AM62PX_DEV_GICSS0 spi 95
AM62PX_DEV_DMASS0_INTAGGR_0 28 32 AM62PX_DEV_GICSS0 spi 96
AM62PX_DEV_DMASS0_INTAGGR_0 28 33 AM62PX_DEV_GICSS0 spi 97
AM62PX_DEV_DMASS0_INTAGGR_0 28 34 AM62PX_DEV_GICSS0 spi 98
AM62PX_DEV_DMASS0_INTAGGR_0 28 35 AM62PX_DEV_GICSS0 spi 99
AM62PX_DEV_DMASS0_INTAGGR_0 28 36 AM62PX_DEV_GICSS0 spi 100
AM62PX_DEV_DMASS0_INTAGGR_0 28 37 AM62PX_DEV_GICSS0 spi 101
AM62PX_DEV_DMASS0_INTAGGR_0 28 38 AM62PX_DEV_GICSS0 spi 102
AM62PX_DEV_DMASS0_INTAGGR_0 28 39 AM62PX_DEV_GICSS0 spi 103
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 40 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 64
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 41 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 65
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 42 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 66
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 43 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 67
AM62PX_DEV_DMASS0_INTAGGR_0 28 44 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 68
AM62PX_DEV_DMASS0_INTAGGR_0 28 45 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 69
AM62PX_DEV_DMASS0_INTAGGR_0 28 46 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 70
AM62PX_DEV_DMASS0_INTAGGR_0 28 47 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 71
AM62PX_DEV_DMASS0_INTAGGR_0 28 48 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 72
AM62PX_DEV_DMASS0_INTAGGR_0 28 49 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 73
AM62PX_DEV_DMASS0_INTAGGR_0 28 50 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 74
AM62PX_DEV_DMASS0_INTAGGR_0 28 51 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 75
AM62PX_DEV_DMASS0_INTAGGR_0 28 52 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 76
AM62PX_DEV_DMASS0_INTAGGR_0 28 53 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 77
AM62PX_DEV_DMASS0_INTAGGR_0 28 54 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 78
AM62PX_DEV_DMASS0_INTAGGR_0 28 55 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 79
AM62PX_DEV_DMASS0_INTAGGR_0 28 56 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 80
AM62PX_DEV_DMASS0_INTAGGR_0 28 57 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 81
AM62PX_DEV_DMASS0_INTAGGR_0 28 58 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 82
AM62PX_DEV_DMASS0_INTAGGR_0 28 59 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 83
AM62PX_DEV_DMASS0_INTAGGR_0 28 60 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 84
AM62PX_DEV_DMASS0_INTAGGR_0 28 61 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 85
AM62PX_DEV_DMASS0_INTAGGR_0 28 62 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 86
AM62PX_DEV_DMASS0_INTAGGR_0 28 63 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 87
AM62PX_DEV_DMASS0_INTAGGR_0 28 64 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 88
AM62PX_DEV_DMASS0_INTAGGR_0 28 65 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 89
AM62PX_DEV_DMASS0_INTAGGR_0 28 66 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 90
AM62PX_DEV_DMASS0_INTAGGR_0 28 67 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 91
AM62PX_DEV_DMASS0_INTAGGR_0 28 68 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 92
AM62PX_DEV_DMASS0_INTAGGR_0 28 69 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 93
AM62PX_DEV_DMASS0_INTAGGR_0 28 70 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 94
AM62PX_DEV_DMASS0_INTAGGR_0 28 71 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 95
AM62PX_DEV_DMASS0_INTAGGR_0 28 72 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 8
AM62PX_DEV_DMASS0_INTAGGR_0 28 73 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 9
AM62PX_DEV_DMASS0_INTAGGR_0 28 74 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 10
AM62PX_DEV_DMASS0_INTAGGR_0 28 75 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 11
AM62PX_DEV_DMASS0_INTAGGR_0 28 76 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 12
AM62PX_DEV_DMASS0_INTAGGR_0 28 77 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 13
AM62PX_DEV_DMASS0_INTAGGR_0 28 78 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 14
AM62PX_DEV_DMASS0_INTAGGR_0 28 79 AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 15
AM62PX_DEV_DMASS0_INTAGGR_0 28 80 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 81 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 82 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 83 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 84 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 85 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 86 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 87 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 88 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 89 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 90 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 91 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 92 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 93 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 94 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 95 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 96 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 97 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 98 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 99 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 100 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 101 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 102 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 103 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 104 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 105 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 106 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 107 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 108 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 109 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 110 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 111 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 112 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 113 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 114 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 115 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 116 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 117 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 118 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 119 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 120 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 121 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 122 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 123 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 124 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 125 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 126 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 127 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 128 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 129 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 130 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 131 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 132 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 133 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 134 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 135 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 136 AM62PX_DEV_HSM0 nvic 176
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 137 AM62PX_DEV_HSM0 nvic 177
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 138 AM62PX_DEV_HSM0 nvic 178
AM62PX_DEV_DMASS0_INTAGGR_0 (Reserved by System Firmware) 28 139 AM62PX_DEV_HSM0 nvic 179
AM62PX_DEV_DMASS0_INTAGGR_0 28 140 AM62PX_DEV_HSM0 nvic 180
AM62PX_DEV_DMASS0_INTAGGR_0 28 141 AM62PX_DEV_HSM0 nvic 181
AM62PX_DEV_DMASS0_INTAGGR_0 28 142 AM62PX_DEV_HSM0 nvic 182
AM62PX_DEV_DMASS0_INTAGGR_0 28 143 AM62PX_DEV_HSM0 nvic 183
AM62PX_DEV_DMASS0_INTAGGR_0 28 144 AM62PX_DEV_HSM0 nvic 184
AM62PX_DEV_DMASS0_INTAGGR_0 28 145 AM62PX_DEV_HSM0 nvic 185
AM62PX_DEV_DMASS0_INTAGGR_0 28 146 AM62PX_DEV_HSM0 nvic 186
AM62PX_DEV_DMASS0_INTAGGR_0 28 147 AM62PX_DEV_HSM0 nvic 187
AM62PX_DEV_DMASS0_INTAGGR_0 28 148 AM62PX_DEV_HSM0 nvic 188
AM62PX_DEV_DMASS0_INTAGGR_0 28 149 AM62PX_DEV_HSM0 nvic 189
AM62PX_DEV_DMASS0_INTAGGR_0 28 150 AM62PX_DEV_HSM0 nvic 190
AM62PX_DEV_DMASS0_INTAGGR_0 28 151 AM62PX_DEV_HSM0 nvic 191
AM62PX_DEV_DMASS0_INTAGGR_0 28 152 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 153 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 154 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 155 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 156 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 157 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 158 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 159 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 160 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 161 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 162 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 163 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 164 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 165 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 166 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 167 Use TRM - Not managed by TISCI    
AM62PX_DEV_DMASS0_INTAGGR_0 28 168 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 64
AM62PX_DEV_DMASS0_INTAGGR_0 28 169 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 65
AM62PX_DEV_DMASS0_INTAGGR_0 28 170 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 66
AM62PX_DEV_DMASS0_INTAGGR_0 28 171 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 67
AM62PX_DEV_DMASS0_INTAGGR_0 28 172 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 68
AM62PX_DEV_DMASS0_INTAGGR_0 28 173 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 69
AM62PX_DEV_DMASS0_INTAGGR_0 28 174 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 70
AM62PX_DEV_DMASS0_INTAGGR_0 28 175 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 71
AM62PX_DEV_DMASS0_INTAGGR_0 28 176 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 72
AM62PX_DEV_DMASS0_INTAGGR_0 28 177 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 73
AM62PX_DEV_DMASS0_INTAGGR_0 28 178 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 74
AM62PX_DEV_DMASS0_INTAGGR_0 28 179 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 75
AM62PX_DEV_DMASS0_INTAGGR_0 28 180 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 76
AM62PX_DEV_DMASS0_INTAGGR_0 28 181 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 77
AM62PX_DEV_DMASS0_INTAGGR_0 28 182 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 78
AM62PX_DEV_DMASS0_INTAGGR_0 28 183 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 79

DMASS1_INTAGGR_0 Interrupt Aggregator Virtual Interrupt Destinations

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

IA Name IA Device ID IA VINT Index Destination Name Destination Interface Destination Index
AM62PX_DEV_DMASS1_INTAGGR_0 200 0 AM62PX_DEV_GICSS0 spi 237
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 129
AM62PX_DEV_DMASS1_INTAGGR_0 200 0 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 129
AM62PX_DEV_DMASS1_INTAGGR_0 200 1 AM62PX_DEV_GICSS0 spi 238
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 130
AM62PX_DEV_DMASS1_INTAGGR_0 200 1 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 130
AM62PX_DEV_DMASS1_INTAGGR_0 200 2 AM62PX_DEV_GICSS0 spi 239
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 131
AM62PX_DEV_DMASS1_INTAGGR_0 200 2 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 131
AM62PX_DEV_DMASS1_INTAGGR_0 200 3 AM62PX_DEV_GICSS0 spi 240
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 132
AM62PX_DEV_DMASS1_INTAGGR_0 200 3 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 132
AM62PX_DEV_DMASS1_INTAGGR_0 200 4 AM62PX_DEV_GICSS0 spi 241
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 150
AM62PX_DEV_DMASS1_INTAGGR_0 200 4 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 150
AM62PX_DEV_DMASS1_INTAGGR_0 200 5 AM62PX_DEV_GICSS0 spi 242
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 158
AM62PX_DEV_DMASS1_INTAGGR_0 200 5 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 158
AM62PX_DEV_DMASS1_INTAGGR_0 200 6 AM62PX_DEV_GICSS0 spi 243
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 159
AM62PX_DEV_DMASS1_INTAGGR_0 200 6 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 159
AM62PX_DEV_DMASS1_INTAGGR_0 200 7 AM62PX_DEV_GICSS0 spi 244
      AM62PX_DEV_WKUP_R5FSS0_CORE0 intr 160
AM62PX_DEV_DMASS1_INTAGGR_0 200 7 AM62PX_DEV_MCU_R5FSS0_CORE0 cpu0_intr 160

Global Events

This section describes AM62PX global events. The global events are used in interrupt management based TISCI messages.

Warning

Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

Global Event Name Global Event Range
DMASS0_INTAGGR_0 SEVT (RESERVED BY SYSTEM FIRMWARE) 0 to 12
DMASS0_INTAGGR_0 SEVT 13 to 1535
DMASS0_INTAGGR_0 MEVT 8192 to 8319
DMASS0_INTAGGR_0 GEVT 10240 to 10495
DMASS1_INTAGGR_0 SEVT 12288 to 12415
DMASS1_INTAGGR_0 MEVT 13312 to 13343
DMASS1_INTAGGR_0 GEVT 13824 to 13855
DMASS0_INTAGGR_0 LEVT 32768 to 32799
DMASS0_BCDMA_0 TRIGGER 50176 to 50339
DMASS1_BCDMA_0 TRIGGER 51200 to 51211

Event-Based Interrupt Source IDs

Device Name Device ID Interrupt Source Name Interrupt Source Index
AM62PX_DEV_DMASS0_RINGACC_0 33 Ring events N/A to N/A
AM62PX_DEV_DMASS0_RINGACC_0 33 Ring global error event N/A
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_tx_chan_error events 4096 to 4124
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_tx_flow_completion events 4608 to 4706
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_rx_chan_error events 5120 to 5143
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_rx_flow_completion events 5632 to 5682
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_rx_flow_starvation events 6144 to 6194
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_chan_error events 8192 to 8223
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_chan_data_completion events 8704 to 8735
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_chan_ring_completion events 9216 to 9247
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_tx_chan_error events 9728 to 9752
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_tx_chan_data_completion events 10240 to 10264
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_tx_chan_ring_completion events 10752 to 10776
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_rx_chan_error events 11264 to 11288
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_rx_chan_data_completion events 11776 to 11800
AM62PX_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_rx_chan_ring_completion events 12288 to 12312
AM62PX_DEV_DMASS1_INTAGGR_0 200 DMASS1_INTAGGR_0 mapped bcdma_rx_chan_error events 3072 to 3077
AM62PX_DEV_DMASS1_INTAGGR_0 200 DMASS1_INTAGGR_0 mapped bcdma_rx_chan_data_completion events 3584 to 3589
AM62PX_DEV_DMASS1_INTAGGR_0 200 DMASS1_INTAGGR_0 mapped bcdma_rx_chan_ring_completion events 4096 to 4101