4.16.7.2. J721e Peripheral Interrupt Destination Descriptions

4.16.7.2.1. Introduction

This chapter provides information on processor interrupt destination IDs that are permitted in the j721e SoC. The interrupt destination IDs represent inputs to SoC processor interrupt controllers or the processors themselves. The System Firmware interrupt management TISCI message APIs take interrupt destination IDs as input to set and release interrupt routes between source peripherals and destination processors.

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

4.16.7.2.2. Interrupt Destination IDs

Destination Device Name	Destination Device ID	Interrupt Destination Description	Interrupt Destination Input Index
J721E_DEV_COMPUTE_CLUSTER0_CLEC (Reserved by System Firmware)	6	J721E_DEV_COMPUTE_CLUSTER0_CLEC inputs from NAVSS0_INTR_ROUTER_0	64 to 73
J721E_DEV_COMPUTE_CLUSTER0_CLEC	6	J721E_DEV_COMPUTE_CLUSTER0_CLEC inputs from NAVSS0_INTR_ROUTER_0	74 to 127
J721E_DEV_COMPUTE_CLUSTER0_CLEC	6	J721E_DEV_COMPUTE_CLUSTER0_CLEC inputs from GPIOMUX_INTRTR0	392 to 447
J721E_DEV_COMPUTE_CLUSTER0_CLEC	6	J721E_DEV_COMPUTE_CLUSTER0_CLEC inputs from NAVSS0_INTR_ROUTER_0	448 to 511
J721E_DEV_COMPUTE_CLUSTER0_CLEC	6	J721E_DEV_COMPUTE_CLUSTER0_CLEC inputs from CMPEVENT_INTRTR0	544 to 559
J721E_DEV_COMPUTE_CLUSTER0_CLEC	6	J721E_DEV_COMPUTE_CLUSTER0_CLEC inputs from NAVSS0_INTR_ROUTER_0	672 to 731
J721E_DEV_COMPUTE_CLUSTER0_CLEC (Reserved by System Firmware)	6	J721E_DEV_COMPUTE_CLUSTER0_CLEC inputs from NAVSS0_INTR_ROUTER_0	732 to 735
J721E_DEV_COMPUTE_CLUSTER0_CLEC	6	J721E_DEV_COMPUTE_CLUSTER0_CLEC inputs from WKUP_GPIOMUX_INTRTR0	960 to 975
J721E_DEV_COMPUTE_CLUSTER0_GIC500SS (Reserved by System Firmware)	14	J721E_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from NAVSS0_INTR_ROUTER_0	64 to 73
J721E_DEV_COMPUTE_CLUSTER0_GIC500SS	14	J721E_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from NAVSS0_INTR_ROUTER_0	74 to 127
J721E_DEV_COMPUTE_CLUSTER0_GIC500SS	14	J721E_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from GPIOMUX_INTRTR0	392 to 447
J721E_DEV_COMPUTE_CLUSTER0_GIC500SS	14	J721E_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from NAVSS0_INTR_ROUTER_0	448 to 511
J721E_DEV_COMPUTE_CLUSTER0_GIC500SS	14	J721E_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from CMPEVENT_INTRTR0	544 to 559
J721E_DEV_COMPUTE_CLUSTER0_GIC500SS	14	J721E_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from NAVSS0_INTR_ROUTER_0	672 to 731
J721E_DEV_COMPUTE_CLUSTER0_GIC500SS (Reserved by System Firmware)	14	J721E_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from NAVSS0_INTR_ROUTER_0	732 to 735
J721E_DEV_COMPUTE_CLUSTER0_GIC500SS	14	J721E_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from WKUP_GPIOMUX_INTRTR0	960 to 975
J721E_DEV_MCU_CPSW0	18	J721E_DEV_MCU_CPSW0 inputs from TIMESYNC_INTRTR0	0
J721E_DEV_CPSW0	19	J721E_DEV_CPSW0 inputs from TIMESYNC_INTRTR0	0
J721E_DEV_CPSW0	19	J721E_DEV_CPSW0 inputs from TIMESYNC_INTRTR0	1
J721E_DEV_CPSW0	19	J721E_DEV_CPSW0 inputs from TIMESYNC_INTRTR0	2
J721E_DEV_CPSW0	19	J721E_DEV_CPSW0 inputs from TIMESYNC_INTRTR0	3
J721E_DEV_CPSW0	19	J721E_DEV_CPSW0 inputs from TIMESYNC_INTRTR0	4
J721E_DEV_CPSW0	19	J721E_DEV_CPSW0 inputs from TIMESYNC_INTRTR0	5
J721E_DEV_CPSW0	19	J721E_DEV_CPSW0 inputs from TIMESYNC_INTRTR0	6
J721E_DEV_ESM0	97	J721E_DEV_ESM0 inputs from GPIOMUX_INTRTR0	632 to 639
J721E_DEV_ESM0	97	J721E_DEV_ESM0 inputs from GPIOMUX_INTRTR0	640 to 647
J721E_DEV_ESM0	97	J721E_DEV_ESM0 inputs from GPIOMUX_INTRTR0	648 to 655
J721E_DEV_WKUP_ESM0	99	J721E_DEV_WKUP_ESM0 inputs from WKUP_GPIOMUX_INTRTR0	88 to 95
J721E_DEV_WKUP_ESM0	99	J721E_DEV_WKUP_ESM0 inputs from WKUP_GPIOMUX_INTRTR0	96 to 103
J721E_DEV_WKUP_ESM0	99	J721E_DEV_WKUP_ESM0 inputs from WKUP_GPIOMUX_INTRTR0	104 to 111
J721E_DEV_PRU_ICSSG0	119	J721E_DEV_PRU_ICSSG0 inputs from TIMESYNC_INTRTR0	0
J721E_DEV_PRU_ICSSG0	119	J721E_DEV_PRU_ICSSG0 inputs from TIMESYNC_INTRTR0	1
J721E_DEV_PRU_ICSSG0	119	J721E_DEV_PRU_ICSSG0 inputs from TIMESYNC_INTRTR0	2
J721E_DEV_PRU_ICSSG0	119	J721E_DEV_PRU_ICSSG0 inputs from TIMESYNC_INTRTR0	3
J721E_DEV_PRU_ICSSG0	119	J721E_DEV_PRU_ICSSG0 inputs from GPIOMUX_INTRTR0	4 to 9
J721E_DEV_PRU_ICSSG0	119	J721E_DEV_PRU_ICSSG0 inputs from GPIOMUX_INTRTR0	10 to 15
J721E_DEV_PRU_ICSSG0	119	J721E_DEV_PRU_ICSSG0 inputs from NAVSS0_INTR_ROUTER_0	46 to 53
J721E_DEV_PRU_ICSSG1	120	J721E_DEV_PRU_ICSSG1 inputs from TIMESYNC_INTRTR0	0
J721E_DEV_PRU_ICSSG1	120	J721E_DEV_PRU_ICSSG1 inputs from TIMESYNC_INTRTR0	1
J721E_DEV_PRU_ICSSG1	120	J721E_DEV_PRU_ICSSG1 inputs from TIMESYNC_INTRTR0	2
J721E_DEV_PRU_ICSSG1	120	J721E_DEV_PRU_ICSSG1 inputs from TIMESYNC_INTRTR0	3
J721E_DEV_PRU_ICSSG1	120	J721E_DEV_PRU_ICSSG1 inputs from GPIOMUX_INTRTR0	4 to 9
J721E_DEV_PRU_ICSSG1	120	J721E_DEV_PRU_ICSSG1 inputs from GPIOMUX_INTRTR0	10 to 15
J721E_DEV_PRU_ICSSG1	120	J721E_DEV_PRU_ICSSG1 inputs from NAVSS0_INTR_ROUTER_0	46 to 53
J721E_DEV_C66SS0_CORE0 (Reserved by System Firmware)	142	J721E_DEV_C66SS0_CORE0 inputs from C66SS0_INTROUTER0	4 to 7
J721E_DEV_C66SS0_CORE0	142	J721E_DEV_C66SS0_CORE0 inputs from C66SS0_INTROUTER0	8
J721E_DEV_C66SS0_CORE0	142	J721E_DEV_C66SS0_CORE0 inputs from C66SS0_INTROUTER0	15 to 95
J721E_DEV_C66SS0_CORE0	142	J721E_DEV_C66SS0_CORE0 inputs from C66SS0_INTROUTER0	99
J721E_DEV_C66SS0_CORE0	142	J721E_DEV_C66SS0_CORE0 inputs from C66SS0_INTROUTER0	102 to 109
J721E_DEV_C66SS0_CORE0	142	J721E_DEV_C66SS0_CORE0 inputs from C66SS0_INTROUTER0	114 to 115
J721E_DEV_C66SS1_CORE0 (Reserved by System Firmware)	143	J721E_DEV_C66SS1_CORE0 inputs from C66SS1_INTROUTER0	4 to 7
J721E_DEV_C66SS1_CORE0	143	J721E_DEV_C66SS1_CORE0 inputs from C66SS1_INTROUTER0	8
J721E_DEV_C66SS1_CORE0	143	J721E_DEV_C66SS1_CORE0 inputs from C66SS1_INTROUTER0	15 to 95
J721E_DEV_C66SS1_CORE0	143	J721E_DEV_C66SS1_CORE0 inputs from C66SS1_INTROUTER0	99
J721E_DEV_C66SS1_CORE0	143	J721E_DEV_C66SS1_CORE0 inputs from C66SS1_INTROUTER0	102 to 109
J721E_DEV_C66SS1_CORE0	143	J721E_DEV_C66SS1_CORE0 inputs from C66SS1_INTROUTER0	114 to 115
J721E_DEV_NAVSS0	199	J721E_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0	0
J721E_DEV_NAVSS0	199	J721E_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0	1
J721E_DEV_NAVSS0	199	J721E_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0	2
J721E_DEV_NAVSS0	199	J721E_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0	3
J721E_DEV_NAVSS0	199	J721E_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0	4
J721E_DEV_NAVSS0	199	J721E_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0	5
J721E_DEV_NAVSS0	199	J721E_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0	6
J721E_DEV_NAVSS0_UDMASS_INTAGGR_0	209	J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 inputs from TIMESYNC_INTRTR0	52 to 59
J721E_DEV_NAVSS0_UDMASS_INTAGGR_0	209	J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 inputs from CMPEVENT_INTRTR0	60 to 67
J721E_DEV_NAVSS0_UDMASS_INTAGGR_0	209	J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 inputs from GPIOMUX_INTRTR0	68 to 83
J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0	233	J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 inputs from WKUP_GPIOMUX_INTRTR0	4 to 11
J721E_DEV_R5FSS0_CORE0	245	J721E_DEV_R5FSS0_CORE0 inputs from GPIOMUX_INTRTR0	176 to 191
J721E_DEV_R5FSS0_CORE0 (Reserved by System Firmware)	245	J721E_DEV_R5FSS0_CORE0 inputs from NAVSS0_INTR_ROUTER_0	224 to 227
J721E_DEV_R5FSS0_CORE0	245	J721E_DEV_R5FSS0_CORE0 inputs from NAVSS0_INTR_ROUTER_0	228 to 255
J721E_DEV_R5FSS0_CORE0	245	J721E_DEV_R5FSS0_CORE0 inputs from R5FSS0_INTROUTER0	256 to 511
J721E_DEV_R5FSS0_CORE1	246	J721E_DEV_R5FSS0_CORE1 inputs from GPIOMUX_INTRTR0	176 to 191
J721E_DEV_R5FSS0_CORE1 (Reserved by System Firmware)	246	J721E_DEV_R5FSS0_CORE1 inputs from NAVSS0_INTR_ROUTER_0	224 to 227
J721E_DEV_R5FSS0_CORE1	246	J721E_DEV_R5FSS0_CORE1 inputs from NAVSS0_INTR_ROUTER_0	228 to 255
J721E_DEV_R5FSS0_CORE1	246	J721E_DEV_R5FSS0_CORE1 inputs from R5FSS0_INTROUTER0	256 to 511
J721E_DEV_R5FSS1_CORE0	247	J721E_DEV_R5FSS1_CORE0 inputs from GPIOMUX_INTRTR0	176 to 191
J721E_DEV_R5FSS1_CORE0 (Reserved by System Firmware)	247	J721E_DEV_R5FSS1_CORE0 inputs from NAVSS0_INTR_ROUTER_0	224 to 227
J721E_DEV_R5FSS1_CORE0	247	J721E_DEV_R5FSS1_CORE0 inputs from NAVSS0_INTR_ROUTER_0	228 to 255
J721E_DEV_R5FSS1_CORE0	247	J721E_DEV_R5FSS1_CORE0 inputs from R5FSS1_INTROUTER0	256 to 511
J721E_DEV_R5FSS1_CORE1	248	J721E_DEV_R5FSS1_CORE1 inputs from GPIOMUX_INTRTR0	176 to 191
J721E_DEV_R5FSS1_CORE1 (Reserved by System Firmware)	248	J721E_DEV_R5FSS1_CORE1 inputs from NAVSS0_INTR_ROUTER_0	224 to 227
J721E_DEV_R5FSS1_CORE1	248	J721E_DEV_R5FSS1_CORE1 inputs from NAVSS0_INTR_ROUTER_0	228 to 255
J721E_DEV_R5FSS1_CORE1	248	J721E_DEV_R5FSS1_CORE1 inputs from R5FSS1_INTROUTER0	256 to 511
J721E_DEV_MCU_R5FSS0_CORE0 (Reserved by System Firmware)	250	J721E_DEV_MCU_R5FSS0_CORE0 inputs from MCU_NAVSS0_INTR_0	64 to 75
J721E_DEV_MCU_R5FSS0_CORE0	250	J721E_DEV_MCU_R5FSS0_CORE0 inputs from MCU_NAVSS0_INTR_0	76 to 95
J721E_DEV_MCU_R5FSS0_CORE0	250	J721E_DEV_MCU_R5FSS0_CORE0 inputs from WKUP_GPIOMUX_INTRTR0	124 to 139
J721E_DEV_MCU_R5FSS0_CORE0	250	J721E_DEV_MCU_R5FSS0_CORE0 inputs from MAIN2MCU_LVL_INTRTR0	160 to 223
J721E_DEV_MCU_R5FSS0_CORE0	250	J721E_DEV_MCU_R5FSS0_CORE0 inputs from MAIN2MCU_PLS_INTRTR0	224 to 271
J721E_DEV_MCU_R5FSS0_CORE0	250	J721E_DEV_MCU_R5FSS0_CORE0 inputs from NAVSS0_INTR_ROUTER_0	376 to 383
J721E_DEV_MCU_R5FSS0_CORE1 (Reserved by System Firmware)	251	J721E_DEV_MCU_R5FSS0_CORE1 inputs from MCU_NAVSS0_INTR_0	64 to 67
J721E_DEV_MCU_R5FSS0_CORE1	251	J721E_DEV_MCU_R5FSS0_CORE1 inputs from MCU_NAVSS0_INTR_0	68 to 95
J721E_DEV_MCU_R5FSS0_CORE1	251	J721E_DEV_MCU_R5FSS0_CORE1 inputs from WKUP_GPIOMUX_INTRTR0	124 to 139
J721E_DEV_MCU_R5FSS0_CORE1	251	J721E_DEV_MCU_R5FSS0_CORE1 inputs from MAIN2MCU_LVL_INTRTR0	160 to 223
J721E_DEV_MCU_R5FSS0_CORE1	251	J721E_DEV_MCU_R5FSS0_CORE1 inputs from MAIN2MCU_PLS_INTRTR0	224 to 271
J721E_DEV_MCU_R5FSS0_CORE1	251	J721E_DEV_MCU_R5FSS0_CORE1 inputs from NAVSS0_INTR_ROUTER_0	376 to 383