2.2. Release Notes - 08_05_00¶

2.2.3.1. CSL¶

• CSL ARM R5 Cache operation APIs now accepts a third argument wait, to specify if the function should wait or not until the operation is completed.

  Old	New
  CSL_armR5CacheWb(const void * addr, int32_t size)	CSL_armR5CacheWb(const void * addr, int32_t size, bool wait)
  CSL_armR5CacheWbInv(const void * addr, int32_t size)	CSL_armR5CacheWbInv(const void * addr, int32_t size, bool wait)
  CSL_armR5CacheInv(const void * addr, int32_t size)	CSL_armR5CacheInv(const void * addr, int32_t size, bool wait)

• Added new API CSL_armR5CacheWait. This can be used to wait for the previous cache wb/wbInv/inv operation to complete.

• For performance optimizations, following CSL cache line operation functions will not invoke memory barrier instructions. Instead end user is supposed to handle the same after updating all the required cache lines.

  1. CSL_armR5CacheInvalidateDcacheMva
  2. CSL_armR5CacheCleanDcacheMva

2.2.3.2. OSAL¶

• taskFxn paramater for TaskP_Create is updated from type ‘void*’ to function pointer of type TaskP_Fxn

  • i.e, TaskP_create expects a function pointer of prototype

    void ( * TaskP_Fxn )( void *arg0, void *arg1 )
    

• name param in TaskP_Params is updated from type uint8_t * to const char *

• CycleprofilerP_getTimeStamp does not check for R5F PMU counter overflow and refresh the PMU counter higher bits.

  • In case of FreeRTOS, OS tick timer handles this internally by periodically checking for R5F PMU counter overflow and refresh the higher bits of PMU counter in the event of any overflow.
  • In SafeRTOS and Baremetal, this is not handled by default.
  • A new API, CycleprofilerP_refreshCounter is added to check for R5F PMU counter overflow and refresh the higher bits of PMU counter in the event of any overflow.
  • Baremetal/SafeRTOS applications can periodically invoke the new API CycleprofilerP_refreshCounter to handle R5F PMU counter overflow.

2.2.3.3. VHWA¶

MSC

• VHWA_M2M_MSC_MAX_INPUT_BUFF macro is removed and instead a new macro VHWA_M2M_MSC_MAX_IN_CHANNEL is added.

• Following parameters in Vhwa_M2mMscSl2AllocPrms structure is updated from a single dimensional array of size VHWA_M2M_MSC_MAX_INPUT_BUFF to a multi-dimensional array of size VHWA_M2M_MSC_MAX_INST x VHWA_M2M_MSC_MAX_IN_CHANNEL

  1. maxInWidth
  2. inCcsf
  3. inBuffDepth

  • Applications should update the initialization accordingly.

• isInterleaveFormat parameter which was earlier present in CSL_MscConfig structure is now moved to Msc_ScConfig in include/msc_cfg.h

  • Applications should update the initialization accordingly.

2.2.3.4. Sciclient / TIFS¶

• SYSFW/TIFS have added new PSIL host id verification check. Due to this RM PSIL messages from mcu1_0 should use MSG forwarding instead of sending the message to TIFS directly.
  • mcu1_0 will always be in secure mode when trying to send the message to TIFS directly, to avoid self blocking. And all the BoardCfg RM entries for mcu1_0 are for default non-secure host id. Hence for this case, the new PSIL host id verification will fail.
  • By using MSG forwarding, it retains the host id information of the non-secure/secure mode of mcu1_0. Setting forwarding ensures that the mcu1_0 uses the DM2DMSC secure proxy threads. NOTE: Forwarding always leads to forced polling.
  • For all other default base-port and security messages, mcu1_0 can be in secure mode and send the message to TIFS directly.

2.2.3.5. CSI¶

• App can select the source CSIRX instance to re-transmit to a specific CSITX instance using newly added lpbkCsiRxInst parameter in Csitx_InstCfg structure.
• Added a new parameter enableStrm in Csirx_CreateParams. Previously all supported streams were enabled by default, now this info should be provided by the application.

2.2.3.6. SBL¶

• Migrated boot app (a tertiary boot loader) from MCUSW to PDK. This app can be used to boot any HLOS like QNX, Linux, etc. More details on BootApp migration at Boot App

2.2.10.1. PDK¶

• PDK examples do not support SMP mode. Some of examples still support build in SMP mode but these binaries are not supported or validated.
• TI Clang compiler does not enable O3 optimization level and Thumb2 mode which were enabled by default with TI ARM CGT compiler. This has an impact on driver throughput. E.g. Ethernet performance has reduced by ~20% on J721E
• For Baremetal and SafeRTOS, in case of usage of CycleprofilerP APIs the R5F PMU counter overflow is not handled by default.
  • Applications can periodically use the CycleprofilerP_refreshCounter to check overflow and refresh the higher bits of the PMU counter.

2.2.10.2. ENET¶

• Scatter-gather functionality is currently supported only for packet transmission.

2.2.10.3. SafeRTOS¶

• None.