AM62AX Host Descriptions¶
Introduction¶
This chapter provides information of Host IDs that are permitted in the AM62AX SoC. These host IDs represent processing entities (or PEs) which is mandatory identification of a Host in a processor.
Typically a host is a ‘compute entity’ which may be an actual processor or even a virtual machine. We just use host or processing entity to indicate the same thing.
Enumeration of Host IDs¶
| Host ID | Host Name | Security Status | Description |
|---|---|---|---|
| 0 | TIFS | Secure | TI Foundational Security |
| 10 | A53_0 | Secure | Cortex A53 context 0 on Main island |
| 11 | A53_1 | Secure | Cortex A53 context 1 on Main island |
| 12 | A53_2 | Non Secure | Cortex A53 context 2 on Main island |
| 13 | A53_3 | Non Secure | Cortex A53 context 3 on Main island |
| 14 | A53_4 | Non Secure | Cortex A53 context 4 on Main island |
| 20 | C7X_0_0 | Non Secure | C7x_0 Context 0 on Main island |
| 30 | MCU_0_R5_0 | Non Secure | MCU R5 |
| 35 | MAIN_0_R5_0 | Secure | Cortex R5_0 context 0 on Main island(BOOT) |
| 36 | MAIN_0_R5_1 | Non Secure | Cortex R5_0 context 1 on Main island |
| 37 | MAIN_0_R5_2 | Secure | Cortex R5_0 context 2 on Main island |
| 38 | MAIN_0_R5_3 | Non Secure | Cortex R5_0 context 3 on Main island |
| 250 | DM2TIFS | Secure | DM to TIFS communication |
| 251 | TIFS2DM | Non Secure | TIFS to DM communication |
| 254 | DM | Non Secure | Device Management |
Note
- Description provides an intended purpose of the host ID, though on some systems, this might be used differently, backing memory and link allocations are made with the specified purpose in mind
- Security Status provides an intended purpose for the Host context