5.5. DCC Safety Example¶
5.5.1. Introduction¶
This example demonstrates how to configure the DCC and use it to monitor clocks in the two supported modes (continuous and single-shot modes). It also demonstrates how to receive errors generated by DCC in the MCU and Main domain.
This example displays:
Initializing the ESM to detect the DCC error event(s)
Registration of application callback for notification of ESM error events for the MCU ESM instance
Configuration of one MCU DCC instance to monitor a single clock in continuous mode
Forcing of an error to create a DCC error event
Using a single MCU DCC instance to monitor 3 different clocks by cycling through them in single-shot mode
The above will be done using first the backup clock source (RC OSC) as reference, and then with the primary clock source as reference (HFOSC0/1)
The above will be repeated for a Main domain DCC instance
The following methods can be used as a trigger for the DCC error event:
Change ratio criterion for stable clocks
Use Sciclient API to change clock dividers (with ratio criterion stable) to speed up clock
Use Sciclient API to change clock dividers (with ratio criterion stable) to slow down clock
Turn off power for the monitored input clock
5.5.2. Use Cases¶
Use Case
Description
DCC Inst
ESM
Input Event
Ref Clock
Input Clock
Mode
Input Trigger
Action
UC-1
Configuration of MCU DCC instance with Reference clock set to RC OSC and input clock is set to MCU_PLL1_HSDIV2_CLK0 (MCAN) Error event is forced.
MCU_DCC0
MCU_ESM0
MCU_DCC0_INTR_ERR_LEVEL_0
RC OSC
MCU_PLL1_HSDIV2_CLKO (MCAN)
Continuous
One of the possible methods detailed above.
Error event is logged by application. Print event to UART. Clock is reset by using Sciclient API to re-setup the clock, as needed.
Error event is cleared and execution continues.
UC-2
Configuration of MCU DCC instance with Reference clock set to RC OSC and inputs used as: MCU_PLL1_HSDIV2_CLK0 (MCAN) MCU_PLL1_HSDIV1_CLKOUT (ADC) MCU_SYSCLK/3 No error events.
MCU_DCC0
MCU_ESM0
MCU_DCC0_INTR_ERR_LEVEL_0
RC OSC
MCU_PLL1_HSDIV2_CLKO (MCAN) MCU_PLL1_HSDIV1_CLKOUT (ADC) MCU_SYSCLK/3
Single-shot
No errors, monitoring happens without issue.
Print pass to UART upon successful completion.
UC-3
Configuration of MCU DCC instance with Reference clock set to HFOSC0 and input clock is set to MCU_PLL1_HSDIV2_CLK0 (MCAN) Error event is forced.
MCU_DCC0
MCU_ESM0
MCU_DCC0_INTR_ERR_LEVEL_0
HFOSC0
MCU_PLL1_HSDIV2_CLKO (MCAN)
Continuous
One of the possible methods detailed above.
Error event is logged by application. Print event to UART. Clock is reset by using Sciclient API to re-setup the clock, as needed.
Error event is cleared and execution continues.
UC-4
Configuration of MCU DCC instance with Reference clock set to HFOSC0 and inputs used as: MCU_PLL1_HSDIV2_CLK0 (MCAN) MCU_PLL1_HSDIV1_CLKOUT (ADC) MCU_SYSCLK/3 No error events.
MCU_DCC0
MCU_ESM0
MCU_DCC0_INTR_ERR_LEVEL_0
HFOSC0
MCU_PLL1_HSDIV2_CLKO (MCAN) MCU_PLL1_HSDIV1_CLKOUT (ADC) MCU_SYSCLK/3
Single-shot
No errors, monitoring happens without issue.
Print pass to UART upon successful completion.
UC-5
Configuration of Main DCC instance with Reference clock set to RC OSC and input clock is set to MAIN_PLL0_HSDIV4_CLKOUT Error event is forced.
DCC0
ESM0
DCC0_INTR_ERR_LEVEL_0
RC OSC
MAIN_PLL0_HSDIV4_CLKOUT
Continuous
One of the possible methods detailed above.
Error event is logged by application. Print event to UART. Clock is reset by using Sciclient API to re-setup the clock, as needed.
Error event is cleared and execution continues.
UC-6
Configuration of Main DCC instance with Reference clock set to HFOSC0 and input clock is set to MAIN_PLL0_HSDIV4_CLKOUT Error event is forced.
DCC0
ESM0
DCC0_INTR_ERR_LEVEL_0
HFOSC0
MAIN_PLL0_HSDIV4_CLKOUT
Continuous
One of the possible methods detailed above.
Error event is logged by application. Print event to UART. Clock is reset by using Sciclient API to re-setup the clock, as needed.
Error event is cleared and execution continues.
UC-7
Configuration of Main DCC instance with Reference clock set to RC OSC and input clock is set to HFOSC1. No error events. Use case is stopped after some time.
DCC0
ESM0
DCC0_INTR_ERR_LEVEL_0
RC OSC
HFOSC1
Continuous
No errors. Monitoring happens without issue.
Print pass to UART upon successful completion.
UC-8
Configuration of MCU DCC instance with Reference clock set to RC OSC and input clock is set to HFOSC0. No error events. Use case is stopped after some time.
DCC0
MCU_ESM0
MCU_DCC0_INTR_ERR_LEVEL_0
RC OSC
HFOSC0
Continuous
No errors. Monitoring happens without issue.
Print pass to UART upon successful completion.
5.5.3. Example Details¶
The example should be loaded to the hardware using the Secondary Boot Loader (SBL) from the SDK.
Example Name |
Location |
Build Command |
|---|---|---|
dcc_app_uc1 |
[sdl_install_dir]/examples/dcc/UC1/ |
make dcc_app_uc1 PROFILE=release |
dcc_app_uc4_2 |
[sdl_install_dir]/examples/dcc/UC4_2/ |
make dcc_app_uc4_2 PROFILE=release |
dcc_app_uc3 |
[sdl_install_dir]/examples/dcc/UC3/ |
make dcc_app_uc3 PROFILE=release |
dcc_app_uc5 |
[sdl_install_dir]/examples/dcc/UC5/ |
make dcc_app_uc5 PROFILE=release |
dcc_app_uc6 |
[sdl_install_dir]/examples/dcc/UC6/ |
make dcc_app_uc6 PROFILE=release |
dcc_app_uc7 |
[sdl_install_dir]/examples/dcc/UC7/ |
make dcc_app_uc7 PROFILE=release |
dcc_app_uc8 |
[sdl_install_dir]/examples/dcc/UC8/ |
make dcc_app_uc8 PROFILE=release |
5.5.4. Expected Output¶
dcc_app_uc1:
DCC Example Test Application
DCC_Test_init: Init MCU ESM complete
SDL DCC EXAMPLE TEST: Start UC-1
INSTANCE: MCU_DCC0
Source clock: RC OSC
Test clock: MCAN
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Changing the clock ratios
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
S
Interrupt is generated to ESM
ESM Call back function called : instType 0x2, intType 0x1, grpChannel 0x2, index 0x16, intSrc 0x56
Take action
DL DCC EXAMPLE TEST: Changing the clock source
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
Test Name: DCC EXAMPLE TEST PASSED
All tests have passed.
ESM Example Application
dcc_app_uc2:
DCC EXAMPLE Test Application
DCC_Test_init: Init MCU ESM complete
SDL DCC TEST: Start UC-2
INSTANCE: MCU_DCC0
Source clock: RC OSC
Test clock source: CBASS
SDL DCC TEST: Seed values calculation done.
SDL DCC TEST: DCC configured
SDL DCC TEST: Enabling DCC and waiting for completion interrupt
SDL DCC TEST: DCC Generated completion interrupt
SDL DCC TEST: No Clock Drift was observed
Test clock source: MCAN
SDL DCC TEST: Seed values calculation done.
SDL DCC TEST: DCC configured
SDL DCC TEST: Enabling DCC and waiting for completion interrupt
SDL DCC TEST: DCC Generated completion interrupt
SDL DCC TEST: No Clock Drift was observed
Test clock source: ADC
SDL DCC TEST: Seed values calculation done.
SDL DCC TEST: DCC configured
SDL DCC TEST: Enabling DCC and waiting for completion interrupt
SDL DCC TEST: DCC Generated completion interrupt
SDL DCC TEST: No Clock Drift was observed
Test Name: DCC EXAMPLE TEST PASSED
All tests have passed.
dcc_app_uc3:
DCC Example Test Application
DCC_Test_init: Init MCU ESM complete
INSTANCE: MCU_DCC0
Source clock: HFOSC0
Test clock: MCAN
SDL DCC EXAMPLE TEST: Start UC-3
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Changing the clock ratios
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
Interrupt is generated to ESM
ESM Call back function called : instType 0x2, intType 0x1, grpChannel 0x2, index 0x16, intSrc 0x56
Take action
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
Test Name: DCC EXAMPLE TEST PASSED
All tests have passed.
dcc_app_uc4:
DCC Example Test Application
DCC_Test_init: Init MCU ESM complete
SDL DCC EXAMPLE TEST: Start UC-4
INSTANCE: MCU_DCC0
Source clock: HFOSC0
Test clock source: CBASS
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC configured
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for completion interrupt
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt
SDL DCC EXAMPLE TEST: No Clock Drift was observed
Test clock source: MCAN
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC configured
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for completion interrupt
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt
SDL DCC EXAMPLE TEST: No Clock Drift was observed
Test clock source: ADC
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC configured
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for completion interrupt
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt
SDL DCC EXAMPLE TEST: No Clock Drift was observed
Test Name: DCC EXAMPLE TEST PASSED
All tests have passed.
dcc_app_uc5:
DCC Example Test Application
DCC_Test_init: Init MCU ESM complete
INSTANCE: DCC0
Source clock: RC OSC
Test clock: MCAN
SDL DCC EXAMPLE TEST: Start UC-5
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Changing the clock ratios
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
Interrupt is generated to ESM
ESM Call back function called : instType 0x3, intType 0x1, grpChannel 0x3, index 0x8, intSrc 0x68
Take action
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
Test Name: DCC EXAMPLE TEST PASSED
All tests have passed.
dcc_app_uc6:
DCC Example Test Application
DCC_Test_init: Init MCU ESM complete
INSTANCE: DCC0
Source clock: HFOSC0
Test clock: MCAN
SDL DCC EXAMPLE TEST: Start UC-6
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Changing the clock ratios
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
Interrupt is generated to ESM
ESM Call back function called : instType 0x3, intType 0x1, grpChannel 0x3, index 0x8, intSrc 0x68
Take action
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
Test Name: DCC EXAMPLE TEST PASSED
All tests have passed.
dcc_app_uc7:
DCC Example Test Application
DCC_Test_init: Init MCU ESM complete
INSTANCE: DCC0
Source clock: RC OSC
Test clock: HFOSC1
SDL DCC EXAMPLE TEST: Start UC-7
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC configured
SDL DCC EXAMPLE TEST: Enabling DCC
SDL DCC EXAMPLE TEST: Waiting for some time to perform Continuous mode
SDL DCC EXAMPLE TEST: DCC module is disabled
Test Name: DCC EXAMPLE TEST PASSED
All tests have passed.
dcc_app_uc8:
DCC Example Test Application
DCC_Test_init: Init MCU ESM complete
INSTANCE: MCU_DCC0
Source clock: RC OSC
Test clock: HFOSC0
SDL DCC EXAMPLE TEST: Start UC-8
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC configured
SDL DCC EXAMPLE TEST: Enabling DCC
SDL DCC EXAMPLE TEST: Waiting for some time to perform Continuous mode
SDL DCC EXAMPLE TEST: DCC module is disabled
Test Name: DCC EXAMPLE TEST PASSED
All tests have passed.