SDL API Guide for J721E
sdl_dcc.h
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1 /*
2  * Copyright (c) Texas Instruments Incorporated 2021
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12  * notice, this list of conditions and the following disclaimer in the
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47 #ifndef SDL_DCC_H_
48 #define SDL_DCC_H_
49 
50 
51 
52 /* ========================================================================== */
53 /* Include Files */
54 /* ========================================================================== */
55 
56 #include <sdl_types.h>
57 #include <tistdtypes.h>
58 #include <stdint.h>
59 #include <stdbool.h>
60 #include <src/sdl/hw_types.h>
61 
62 #if defined (SOC_J721E)
64 #include <include/soc/j721e/sdlr_soc_baseaddress.h>
65 #endif /* SOC_J721E */
66 
67 #ifdef __cplusplus
68 extern "C" {
69 #endif
70 
91 /* ========================================================================== */
92 /* Macros & Typedefs */
93 /* ========================================================================== */
94 
104 #define DCC_SRC0_COUNT_MAX (0xFFFFFU)
105 
108 #define DCC_SRC0_VALID_MAX (0x0FFFFU)
109 
112 #define DCC_SRC1_COUNT_MAX (0xFFFFFU)
113 
114 #define MIN_CLK0_VLD_SEED (4u)
115 
137 typedef uint32_t SDL_DCC_mode;
138 
139 #define SDL_DCC_MODE_SINGLE_SHOT_1 (DCC_DCCGCTRL_SINGLESHOT_MODE1)
140 
141 #define SDL_DCC_MODE_SINGLE_SHOT_2 (DCC_DCCGCTRL_SINGLESHOT_MODE2)
142 
143 #define SDL_DCC_MODE_CONTINUOUS (DCC_DCCGCTRL_SINGLESHOT_DISABLE)
144 
145 /* @} */
146 
155 typedef uint32_t SDL_DCC_clkSrc0;
156 
157 #define SDL_DCC_CLK0_SRC_CLOCK0_0 (DCC_DCCCLKSRC0_CLKSRC0_0)
158 
159 #define SDL_DCC_CLK0_SRC_CLOCK0_1 (DCC_DCCCLKSRC0_CLKSRC0_1)
160 
161 #define SDL_DCC_CLK0_SRC_CLOCK0_2 (DCC_DCCCLKSRC0_CLKSRC0_2)
162 
163 /* @} */
164 
173 typedef uint32_t SDL_DCC_clkSrc1;
174 #define SDL_DCC_CLK1_SRC_CLOCK1 (DCC_DCCCLKSRC1_CLKSRC_0)
175 
176 #define SDL_DCC_CLK1_SRC_CLOCKSRC0 (DCC_DCCCLKSRC1_CLKSRC_1)
177 
178 #define SDL_DCC_CLK1_SRC_CLOCKSRC1 (DCC_DCCCLKSRC1_CLKSRC_2)
179 
180 #define SDL_DCC_CLK1_SRC_CLOCKSRC2 (DCC_DCCCLKSRC1_CLKSRC_3)
181 
182 #define SDL_DCC_CLK1_SRC_CLOCKSRC3 (DCC_DCCCLKSRC1_CLKSRC_4)
183 
184 #define SDL_DCC_CLK1_SRC_CLOCKSRC4 (DCC_DCCCLKSRC1_CLKSRC_5)
185 
186 #define SDL_DCC_CLK1_SRC_CLOCKSRC5 (DCC_DCCCLKSRC1_CLKSRC_6)
187 
188 #define SDL_DCC_CLK1_SRC_CLOCKSRC6 (DCC_DCCCLKSRC1_CLKSRC_7)
189 
190 #define SDL_DCC_CLK1_SRC_CLOCKSRC7 (DCC_DCCCLKSRC1_CLKSRC_8)
191 
192 #define SDL_DCC_CLK1_SRC_FICLK (DCC_DCCCLKSRC1_CLKSRC_OTHER)
193 
194 /* @} */
195 
204 typedef uint32_t SDL_DCC_intrType;
205 
206 #define SDL_DCC_INTERRUPT_ERR (0x0U)
207 
208 #define SDL_DCC_INTERRUPT_DONE (0x1U)
209 
210 /* @} */
211 
214 /* ========================================================================== */
215 /* Structures */
216 /* ========================================================================== */
217 
218 
227 typedef struct SDL_DCC_config_st
228 {
237  uint32_t clk1Src;
241  uint32_t clk0Seed;
243  uint32_t clk0ValidSeed;
245  uint32_t clk1Seed;
248 
249 
250 typedef struct SDL_DCC_status_st
251 {
252  bool doneIntr;
253  /* Indicates if a done interrupt is currently pending */
254  bool errIntr;
255  /* Indicates if an error interrupt is currently pending */
257  /* Pointer to DCC config structure */
258  uint32_t clk0Cnt;
259  /* Current COUNT0 value of clock source 0 */
260  uint32_t clk0Valid;
261  /* Current VALID0 value */
262  uint32_t clk1Cnt;
263  /* Current COUNT1 value of clock source 1 */
265 
266 
267 typedef struct SDL_DCC_staticRegs_st
268 {
269  uint32_t DCC_REV;
270  /* DCC revision register */
271  uint32_t DCC_CNTSEED0;
272  /* COUNT0 SEED register */
273  uint32_t DCC_VALIDSEED0;
274  /* VALID0 SEED register */
275  uint32_t DCC_CNTSEED1;
276  /* COUNT1 SEED register */
277  uint32_t DCC_CLKSRC1;
278  /* CLOCK SOURCE1 register */
279  uint32_t DCC_CLKSRC0;
280  /* CLOCK SOURCE0 register */
282 
286 /* ========================================================================== */
287 /* Global Variables */
288 /* ========================================================================== */
289 
290 /* None */
291 
292 /* ========================================================================== */
293 /* Function Declarations */
294 /* ========================================================================== */
295 
312 int32_t SDL_DCC_configure(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig);
313 
321 int32_t SDL_DCC_verifyConfig(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig);
327 int32_t SDL_DCC_enable(SDL_DCC_Inst instance);
333 int32_t SDL_DCC_disable(SDL_DCC_Inst instance);
341 int32_t SDL_DCC_getStatus(SDL_DCC_Inst instance, SDL_DCC_status *pStatus);
349 int32_t SDL_DCC_enableIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr);
357 int32_t SDL_DCC_clearIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr);
365 int32_t SDL_DCC_getStaticRegs(SDL_DCC_Inst instance, SDL_DCC_staticRegs *pStaticRegs);
366 
371 /****************************************************************************************************
372 * Register Definitions
373 ****************************************************************************************************/
374 
375 #define DCC_DCCGCTRL (0x0U)
376 #define DCC_DCCREV (0x4U)
377 #define DCC_DCCCNTSEED0 (0x8U)
378 #define DCC_DCCVALIDSEED0 (0xcU)
379 #define DCC_DCCCNTSEED1 (0x10U)
380 #define DCC_DCCSTAT (0x14U)
381 #define DCC_DCCCNT0 (0x18U)
382 #define DCC_DCCVALID0 (0x1cU)
383 #define DCC_DCCCNT1 (0x20U)
384 #define DCC_DCCCLKSRC1 (0x24U)
385 #define DCC_DCCCLKSRC0 (0x28U)
386 
387 /****************************************************************************************************
388 * Field Definition Macros
389 ****************************************************************************************************/
390 
391 #define DCC_DCCGCTRL_DCCENA_SHIFT (0U)
392 #define DCC_DCCGCTRL_DCCENA_MASK (0x0000000fU)
393 #define DCC_DCCGCTRL_DCCENA_ENABLE (0xFU)
394 #define DCC_DCCGCTRL_DCCENA_DISABLE (0x5U)
395 
396 #define DCC_DCCGCTRL_ERRENA_SHIFT (4U)
397 #define DCC_DCCGCTRL_ERRENA_MASK (0x000000f0U)
398 #define DCC_DCCGCTRL_ERRENA_ENABLE (0xFU)
399 #define DCC_DCCGCTRL_ERRENA_DISABLE (0x5U)
400 
401 #define DCC_DCCGCTRL_SINGLESHOT_SHIFT (8U)
402 #define DCC_DCCGCTRL_SINGLESHOT_MASK (0x00000f00U)
403 #define DCC_DCCGCTRL_SINGLESHOT_MODE1 (0xAU)
404 #define DCC_DCCGCTRL_SINGLESHOT_MODE2 (0xBU)
405 #define DCC_DCCGCTRL_SINGLESHOT_DISABLE (0x0U)
406 
407 #define DCC_DCCGCTRL_DONEENA_SHIFT (12U)
408 #define DCC_DCCGCTRL_DONEENA_MASK (0x0000f000U)
409 #define DCC_DCCGCTRL_DONEENA_ENABLE (0xFU)
410 #define DCC_DCCGCTRL_DONEENA_DISABLE (0x5U)
411 
412 #define DCC_DCCGCTRL_RES_SHIFT (16U)
413 #define DCC_DCCGCTRL_RES_MASK (0xffff0000U)
414 
415 #define DCC_DCCREV_MINOR_SHIFT (0U)
416 #define DCC_DCCREV_MINOR_MASK (0x0000003fU)
417 
418 #define DCC_DCCREV_CUSTOM_SHIFT (6U)
419 #define DCC_DCCREV_CUSTOM_MASK (0x000000c0U)
420 
421 #define DCC_DCCREV_MAJOR_SHIFT (8U)
422 #define DCC_DCCREV_MAJOR_MASK (0x00000700U)
423 
424 #define DCC_DCCREV_RTL_SHIFT (11U)
425 #define DCC_DCCREV_RTL_MASK (0x0000f800U)
426 
427 #define DCC_DCCREV_FUNC_SHIFT (16U)
428 #define DCC_DCCREV_FUNC_MASK (0x0fff0000U)
429 
430 #define DCC_DCCREV_RES_SHIFT (28U)
431 #define DCC_DCCREV_RES_MASK (0x30000000U)
432 
433 #define DCC_DCCREV_SCHEME_SHIFT (30U)
434 #define DCC_DCCREV_SCHEME_MASK (0xc0000000U)
435 
436 #define DCC_DCCCNTSEED0_COUNTSEED0_SHIFT (0U)
437 #define DCC_DCCCNTSEED0_COUNTSEED0_MASK (0x000fffffU)
438 
439 #define DCC_DCCCNTSEED0_RES_SHIFT (20U)
440 #define DCC_DCCCNTSEED0_RES_MASK (0xfff00000U)
441 
442 #define DCC_DCCVALIDSEED0_VALIDSEED0_SHIFT (0U)
443 #define DCC_DCCVALIDSEED0_VALIDSEED0_MASK (0x0000ffffU)
444 
445 #define DCC_DCCVALIDSEED0_RES_SHIFT (16U)
446 #define DCC_DCCVALIDSEED0_RES_MASK (0xffff0000U)
447 
448 #define DCC_DCCCNTSEED1_COUNTSEED1_SHIFT (0U)
449 #define DCC_DCCCNTSEED1_COUNTSEED1_MASK (0x000fffffU)
450 
451 #define DCC_DCCCNTSEED1_RES_SHIFT (20U)
452 #define DCC_DCCCNTSEED1_RES_MASK (0xfff00000U)
453 
454 #define DCC_DCCSTAT_ERRFLG_SHIFT (0U)
455 #define DCC_DCCSTAT_ERRFLG_MASK (0x00000001U)
456 
457 #define DCC_DCCSTAT_DONEFLG_SHIFT (1U)
458 #define DCC_DCCSTAT_DONEFLG_MASK (0x00000002U)
459 
460 #define DCC_DCCSTAT_RES_SHIFT (2U)
461 #define DCC_DCCSTAT_RES_MASK (0xfffffffcU)
462 
463 #define DCC_DCCCNT0_COUNT0_SHIFT (0U)
464 #define DCC_DCCCNT0_COUNT0_MASK (0x000fffffU)
465 
466 #define DCC_DCCCNT0_RES_SHIFT (20U)
467 #define DCC_DCCCNT0_RES_MASK (0xfff00000U)
468 
469 #define DCC_DCCVALID0_VALID0_SHIFT (0U)
470 #define DCC_DCCVALID0_VALID0_MASK (0x0000ffffU)
471 
472 #define DCC_DCCVALID0_RES_SHIFT (16U)
473 #define DCC_DCCVALID0_RES_MASK (0xffff0000U)
474 
475 #define DCC_DCCCNT1_COUNT1_SHIFT (0U)
476 #define DCC_DCCCNT1_COUNT1_MASK (0x000fffffU)
477 
478 #define DCC_DCCCNT1_RES_SHIFT (20U)
479 #define DCC_DCCCNT1_RES_MASK (0xfff00000U)
480 
481 #define DCC_DCCCLKSRC1_CLKSRC_SHIFT (0U)
482 #define DCC_DCCCLKSRC1_CLKSRC_MASK (0x0000000fU)
483 #define DCC_DCCCLKSRC1_CLKSRC_0 (0x0U)
484 #define DCC_DCCCLKSRC1_CLKSRC_1 (0x1U)
485 #define DCC_DCCCLKSRC1_CLKSRC_2 (0x2U)
486 #define DCC_DCCCLKSRC1_CLKSRC_3 (0x3U)
487 #define DCC_DCCCLKSRC1_CLKSRC_4 (0x4U)
488 #define DCC_DCCCLKSRC1_CLKSRC_5 (0x5U)
489 #define DCC_DCCCLKSRC1_CLKSRC_6 (0x6U)
490 #define DCC_DCCCLKSRC1_CLKSRC_7 (0x7U)
491 #define DCC_DCCCLKSRC1_CLKSRC_8 (0x8U)
492 #define DCC_DCCCLKSRC1_CLKSRC_OTHER (0xFU)
493 
494 #define DCC_DCCCLKSRC1_RES1_SHIFT (4U)
495 #define DCC_DCCCLKSRC1_RES1_MASK (0x00000ff0U)
496 
497 #define DCC_DCCCLKSRC1_KEY_SHIFT (12U)
498 #define DCC_DCCCLKSRC1_KEY_MASK (0x0000f000U)
499 #define DCC_DCCCLKSRC1_KEY_ENABLE (0xAU)
500 #define DCC_DCCCLKSRC1_KEY_DISABLE (0x0U)
501 
502 #define DCC_DCCCLKSRC1_RES0_SHIFT (16U)
503 #define DCC_DCCCLKSRC1_RES0_MASK (0xffff0000U)
504 
505 #define DCC_DCCCLKSRC0_CLKSRC0_SHIFT (0U)
506 #define DCC_DCCCLKSRC0_CLKSRC0_MASK (0x0000000fU)
507 #define DCC_DCCCLKSRC0_CLKSRC0_0 (0x0U)
508 #define DCC_DCCCLKSRC0_CLKSRC0_1 (0xAU)
509 #define DCC_DCCCLKSRC0_CLKSRC0_2 (0x5U)
510 
511 #define DCC_DCCCLKSRC0_RES1_SHIFT (4U)
512 #define DCC_DCCCLKSRC0_RES1_MASK (0x00000ff0U)
513 
514 #define DCC_DCCCLKSRC0_KEY_SHIFT (12U)
515 #define DCC_DCCCLKSRC0_KEY_MASK (0x0000f000U)
516 #define DCC_DCCCLKSRC0_KEY_ENABLE (0xAU)
517 #define DCC_DCCCLKSRC0_KEY_DISABLE (0x0U)
518 
519 #define DCC_DCCCLKSRC0_RES0_SHIFT (16U)
520 #define DCC_DCCCLKSRC0_RES0_MASK (0xffff0000U)
521 
522 #ifdef __cplusplus
523 }
524 
525 #endif /*extern "C" */
526 
527 #endif
uint32_t DCC_CLKSRC1
Definition: sdl_dcc.h:277
uint32_t clk0Cnt
Definition: sdl_dcc.h:258
SDL_DCC_Inst
Definition: sdl_soc_dcc.h:72
uint32_t DCC_CNTSEED0
Definition: sdl_dcc.h:271
uint32_t SDL_DCC_mode
Enum to select the DCC Operation Mode.
Definition: sdl_dcc.h:137
Definition: sdl_dcc.h:250
uint32_t SDL_DCC_clkSrc1
Enum to select the COUNT1 clock source.
Definition: sdl_dcc.h:173
uint32_t clk0Valid
Definition: sdl_dcc.h:260
int32_t SDL_DCC_getStaticRegs(SDL_DCC_Inst instance, SDL_DCC_staticRegs *pStaticRegs)
This API is used to get the value of static registers for DCC module.
uint32_t DCC_CNTSEED1
Definition: sdl_dcc.h:275
int32_t SDL_DCC_verifyConfig(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig)
This API is used to verify the configuration for DCC module.
Definition: sdl_dcc.h:267
uint32_t DCC_CLKSRC0
Definition: sdl_dcc.h:279
SDL_DCC_config * config
Definition: sdl_dcc.h:256
int32_t SDL_DCC_clearIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr)
This API is used to clear the interrupts.
SDL_DCC_mode mode
Definition: sdl_dcc.h:229
uint32_t SDL_DCC_intrType
Enum for DCC interrupts.
Definition: sdl_dcc.h:204
bool errIntr
Definition: sdl_dcc.h:254
SDL_DCC_clkSrc0 clk0Src
Definition: sdl_dcc.h:233
int32_t SDL_DCC_disable(SDL_DCC_Inst instance)
This API is used to disable the DCC module.
uint32_t clk1Src
Definition: sdl_dcc.h:237
int32_t SDL_DCC_getStatus(SDL_DCC_Inst instance, SDL_DCC_status *pStatus)
This API is used to get the stauts of DCC module.
uint32_t clk1Cnt
Definition: sdl_dcc.h:262
Structure containing parameters for DCC module configuration.
Definition: sdl_dcc.h:227
uint32_t DCC_VALIDSEED0
Definition: sdl_dcc.h:273
uint32_t DCC_REV
Definition: sdl_dcc.h:269
uint32_t clk0Seed
Definition: sdl_dcc.h:241
uint32_t clk0ValidSeed
Definition: sdl_dcc.h:243
uint32_t clk1Seed
Definition: sdl_dcc.h:245
int32_t SDL_DCC_enableIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr)
This API is used to Enable the interrupts.
bool doneIntr
Definition: sdl_dcc.h:252
int32_t SDL_DCC_configure(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig)
This API is used to configure DCC module.
uint32_t SDL_DCC_clkSrc0
Enum to select the COUNT0 clock source.
Definition: sdl_dcc.h:155
int32_t SDL_DCC_enable(SDL_DCC_Inst instance)
This API is used to enable the DCC module.