Introduction

The Ethernet PHY driver supports auto-negotiation and manual modes. The PHY driver uses an MDIO abstraction to perform register reads and writes. The MDIO abstraction can be implemented using Enet LLD's Enet Management Data I/O (MDIO) API or any other MDIO driver.

Sub Modules
	Generic PHY

	TI DP83822 PHY

	TI DP83867 PHY

	VSC8514 PHY

Data Structures
struct	EnetPhy_Version
	PHY version (ID). More...

struct	EnetPhy_LinkCfg
	Link speed and duplexity configuration. More...

struct	EnetPhy_FsmTimeoutCfg
	PHY State-Machine time-out values. More...

struct	EnetPhy_Cfg
	PHY configuration parameters. More...

struct	EnetPhy_Mdio
	MDIO driver. More...

struct	EnetPhy_State
	PHY driver FSM state. More...

struct	EnetPhy_Obj
	PHY driver object. More...

Functions
void	EnetPhy_initCfg (EnetPhy_Cfg *phyCfg)
	Initialize PHY config params. More...

void	EnetPhy_setExtendedCfg (EnetPhy_Cfg phyCfg, const void extendedCfg, uint32_t extendedCfgSize)
	Set PHY extended parameters. More...

EnetPhy_Handle	EnetPhy_open (const EnetPhy_Cfg phyCfg, EnetPhy_Mii mii, const EnetPhy_LinkCfg linkCfg, uint32_t macPortCaps, EnetPhy_MdioHandle hMdio, void *mdioArgs)
	Open the PHY driver. More...

void	EnetPhy_close (EnetPhy_Handle hPhy)
	Close the PHY driver. More...

EnetPhy_LinkStatus	EnetPhy_tick (EnetPhy_Handle hPhy)
	Run PHY state machine. More...

int32_t	EnetPhy_getId (EnetPhy_Handle hPhy, EnetPhy_Version *version)
	Get PHY id. More...

bool	EnetPhy_isAlive (EnetPhy_Handle hPhy)
	Get PHY alive status. More...

bool	EnetPhy_isLinked (EnetPhy_Handle hPhy)
	Get link status. More...

int32_t	EnetPhy_getLinkCfg (EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
	Get link configuration. More...

int32_t	EnetPhy_readReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
	Read PHY register. More...

int32_t	EnetPhy_writeReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
	Write PHY register. More...

int32_t	EnetPhy_rmwReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
	Read-modify-write PHY register. More...

int32_t	EnetPhy_readExtReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
	Read PHY extended register. More...

int32_t	EnetPhy_writeExtReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
	Write PHY extended register. More...

int32_t	EnetPhy_rmwExtReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
	Read-modify-write PHY extended register. More...

int32_t	EnetPhy_readC45Reg (EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
	Read PHY register using Clause-45 frame. More...

int32_t	EnetPhy_writeC45Reg (EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
	Write PHY register using Clause-45 frame. More...

int32_t	EnetPhy_rmwC45Reg (EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
	Read-modify-write PHY register using Clause-45 frame. More...

void	EnetPhy_printRegs (EnetPhy_Handle hPhy)
	Print all PHY registers. More...

Typedefs
typedef EnetPhy_Mdio *	EnetPhy_MdioHandle
	MDIO driver handle. More...

typedef struct EnetPhy_Drv_s *	EnetPhyDrv_Handle
	PHY specific driver handle. More...

typedef struct EnetPhy_Obj_s *	EnetPhy_Handle
	PHY driver object handle. More...

Enumerations
enum	EnetPhy_Magic { ENETPHY_MAGIC = 0xCADACADAU, ENETPHY_NO_MAGIC = 0x0U }
	EnetPhy driver magic value, used to indicate if driver is open or not. More...

enum	EnetPhy_Mii { ENETPHY_MAC_MII_MII = 0U, ENETPHY_MAC_MII_RMII, ENETPHY_MAC_MII_GMII, ENETPHY_MAC_MII_RGMII, ENETPHY_MAC_MII_SGMII, ENETPHY_MAC_MII_QSGMII }
	MAC Media-Independent Interface (MII). More...

enum	EnetPhy_Speed { ENETPHY_SPEED_10MBIT = 0U, ENETPHY_SPEED_100MBIT, ENETPHY_SPEED_1GBIT, ENETPHY_SPEED_AUTO }
	MAC interface speed. More...

enum	EnetPhy_Duplexity { ENETPHY_DUPLEX_HALF = 0U, ENETPHY_DUPLEX_FULL, ENETPHY_DUPLEX_AUTO }
	MAC interface duplexity. More...

enum	EnetPhy_LinkStatus { ENETPHY_GOT_LINK = 0U, ENETPHY_LINK_UP, ENETPHY_LOST_LINK, ENETPHY_LINK_DOWN }
	PHY link status. More...

enum	EnetPhy_FsmState { ENETPHY_FSM_STATE_INIT = 0U, ENETPHY_FSM_STATE_FINDING, ENETPHY_FSM_STATE_RESET_WAIT, ENETPHY_FSM_STATE_ENABLE, ENETPHY_FSM_STATE_FOUND, ENETPHY_FSM_STATE_NWAY_START, ENETPHY_FSM_STATE_NWAY_WAIT, ENETPHY_FSM_STATE_LINK_WAIT, ENETPHY_FSM_STATE_LINKED, ENETPHY_FSM_STATE_LOOPBACK }
	PHY driver state-machine states. More...

Macros
#define	ENETPHY_IS_ADDR_VALID(addr) ((addr) <= 31U)
	Check if PHY address is valid (0 - 31). More...

#define	ENETPHY_BIT(n) (1U << (n))
	Macro to set bit at given bit position. More...

#define	ENETPHY_IS_BIT_SET(val, n) (((val) & ENETPHY_BIT(n)) != 0U)
	Macro to check if bit at given bit position is set. More...

#define	ENETPHY_ARRAYSIZE(x) (sizeof(x) / sizeof(x[0]))
	Macro to get the size of an array. More...

#define	ENETPHY_EXTENDED_CFG_SIZE_MAX (128U)
	Max extended configuration size, arbitrarily chosen. More...

#define	ENETPHY_FSM_TICK_PERIOD_MS (100U)
	Enet PHY State Machine tick period. More...

#define	ENETPHY_INVALID_PHYADDR (~0U)
	Invalid PHY address indicator. More...

Ethernet PHY driver error codes
Error codes returned by the Ethernet PHY driver APIs.
#define	ENETPHY_SOK (CSL_PASS)
	Success. More...

#define	ENETPHY_EFAIL (CSL_EFAIL)
	Generic failure error condition (typically caused by hardware). More...

#define	ENETPHY_EBADARGS (CSL_EBADARGS)
	Bad arguments (i.e. NULL pointer). More...

#define	ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS)
	Invalid parameters (i.e. value out-of-range). More...

#define	ENETPHY_ETIMEOUT (CSL_ETIMEOUT)
	Time out while waiting for a given condition to happen. More...

#define	ENETPHY_EALLOC (CSL_EALLOC)
	Allocation failure. More...

#define	ENETPHY_EPERM (CSL_EALLOC - 4)
	Operation not permitted. More...

#define	ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5)
	Operation not supported. More...

Ethernet PHY link capability masks
Error codes returned by the Ethernet PHY driver APIs.
#define	ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1)
	10-Mbps, half-duplex capability mask. More...

#define	ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2)
	10-Mbps, full-duplex capability mask. More...

#define	ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3)
	100-Mbps, half-duplex capability mask. More...

#define	ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4)
	100-Mbps, full-duplex capability mask. More...

#define	ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5)
	1-Gbps, half-duplex capability mask. More...

#define	ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6)
	1-Gbps, full-duplex capability mask. More...

#define	ENETPHY_LINK_CAP_10
	10-Mbps, full and half-duplex capability mask. More...

#define	ENETPHY_LINK_CAP_100
	100-Mbps, full and half-duplex capability mask. More...

#define	ENETPHY_LINK_CAP_1000
	1-Gbps, full and half-duplex capability mask. More...

#define	ENETPHY_LINK_CAP_ALL
	Auto-negotiation mask with all duplexity and speed values set. More...

Macro Definition Documentation

◆ ENETPHY_IS_ADDR_VALID

#define ENETPHY_IS_ADDR_VALID ( addr ) ((addr) <= 31U)

Check if PHY address is valid (0 - 31).

◆ ENETPHY_BIT

#define ENETPHY_BIT ( n ) (1U << (n))

Macro to set bit at given bit position.

◆ ENETPHY_IS_BIT_SET

#define ENETPHY_IS_BIT_SET	(	val,
		n
	)	(((val) & ENETPHY_BIT(n)) != 0U)

Macro to check if bit at given bit position is set.

◆ ENETPHY_ARRAYSIZE

#define ENETPHY_ARRAYSIZE ( x ) (sizeof(x) / sizeof(x[0]))

Macro to get the size of an array.

◆ ENETPHY_SOK

#define ENETPHY_SOK (CSL_PASS)

Success.

◆ ENETPHY_EFAIL

#define ENETPHY_EFAIL (CSL_EFAIL)

Generic failure error condition (typically caused by hardware).

◆ ENETPHY_EBADARGS

#define ENETPHY_EBADARGS (CSL_EBADARGS)

Bad arguments (i.e. NULL pointer).

◆ ENETPHY_EINVALIDPARAMS

#define ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS)

Invalid parameters (i.e. value out-of-range).

◆ ENETPHY_ETIMEOUT

#define ENETPHY_ETIMEOUT (CSL_ETIMEOUT)

Time out while waiting for a given condition to happen.

◆ ENETPHY_EALLOC

#define ENETPHY_EALLOC (CSL_EALLOC)

Allocation failure.

◆ ENETPHY_EPERM

#define ENETPHY_EPERM (CSL_EALLOC - 4)

Operation not permitted.

◆ ENETPHY_ENOTSUPPORTED

#define ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5)

Operation not supported.

◆ ENETPHY_LINK_CAP_HD10

#define ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1)

10-Mbps, half-duplex capability mask.

◆ ENETPHY_LINK_CAP_FD10

#define ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2)

10-Mbps, full-duplex capability mask.

◆ ENETPHY_LINK_CAP_HD100

#define ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3)

100-Mbps, half-duplex capability mask.

◆ ENETPHY_LINK_CAP_FD100

#define ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4)

100-Mbps, full-duplex capability mask.

◆ ENETPHY_LINK_CAP_HD1000

#define ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5)

1-Gbps, half-duplex capability mask.

◆ ENETPHY_LINK_CAP_FD1000

#define ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6)

1-Gbps, full-duplex capability mask.

◆ ENETPHY_LINK_CAP_10

#define ENETPHY_LINK_CAP_10

Value:

(ENETPHY_LINK_CAP_HD10 | \

ENETPHY_LINK_CAP_FD10)

ENETPHY_LINK_CAP_HD10

#define ENETPHY_LINK_CAP_HD10

10-Mbps, half-duplex capability mask.

Definition: enetphy.h:139

10-Mbps, full and half-duplex capability mask.

◆ ENETPHY_LINK_CAP_100

#define ENETPHY_LINK_CAP_100

Value:

(ENETPHY_LINK_CAP_HD100 | \

ENETPHY_LINK_CAP_FD100)

ENETPHY_LINK_CAP_HD100

#define ENETPHY_LINK_CAP_HD100

100-Mbps, half-duplex capability mask.

Definition: enetphy.h:145

100-Mbps, full and half-duplex capability mask.

◆ ENETPHY_LINK_CAP_1000

#define ENETPHY_LINK_CAP_1000

Value:

(ENETPHY_LINK_CAP_HD1000 | \

ENETPHY_LINK_CAP_FD1000)

ENETPHY_LINK_CAP_HD1000

#define ENETPHY_LINK_CAP_HD1000

1-Gbps, half-duplex capability mask.

Definition: enetphy.h:151

1-Gbps, full and half-duplex capability mask.

◆ ENETPHY_LINK_CAP_ALL

#define ENETPHY_LINK_CAP_ALL

Value:

(ENETPHY_LINK_CAP_HD10 |   \
                                               ENETPHY_LINK_CAP_FD10 |   \
                                               ENETPHY_LINK_CAP_HD100 |  \
                                               ENETPHY_LINK_CAP_FD100 |  \
                                               ENETPHY_LINK_CAP_HD1000 | \
                                               ENETPHY_LINK_CAP_FD1000)

Auto-negotiation mask with all duplexity and speed values set.

◆ ENETPHY_EXTENDED_CFG_SIZE_MAX

#define ENETPHY_EXTENDED_CFG_SIZE_MAX (128U)

Max extended configuration size, arbitrarily chosen.

◆ ENETPHY_FSM_TICK_PERIOD_MS

#define ENETPHY_FSM_TICK_PERIOD_MS (100U)

Enet PHY State Machine tick period.

◆ ENETPHY_INVALID_PHYADDR

#define ENETPHY_INVALID_PHYADDR (~0U)

Invalid PHY address indicator.

Typedef Documentation

◆ EnetPhy_MdioHandle

typedef EnetPhy_Mdio* EnetPhy_MdioHandle

MDIO driver handle.

◆ EnetPhyDrv_Handle

typedef struct EnetPhy_Drv_s* EnetPhyDrv_Handle

PHY specific driver handle.

◆ EnetPhy_Handle

typedef struct EnetPhy_Obj_s* EnetPhy_Handle

PHY driver object handle.

PHY driver opaque handle used to call any PHY related APIs.

Enumeration Type Documentation

◆ EnetPhy_Magic

enum EnetPhy_Magic

EnetPhy driver magic value, used to indicate if driver is open or not.

Enumerator
ENETPHY_MAGIC	Magic number used to identify when driver has been opened.
ENETPHY_NO_MAGIC	Magic number used to identify when driver is closed.

◆ EnetPhy_Mii

enum EnetPhy_Mii

MAC Media-Independent Interface (MII).

Enumerator
ENETPHY_MAC_MII_MII	MII interface.
ENETPHY_MAC_MII_RMII	RMII interface.
ENETPHY_MAC_MII_GMII	GMII interface.
ENETPHY_MAC_MII_RGMII	RGMII interface.
ENETPHY_MAC_MII_SGMII	SGMII interface.
ENETPHY_MAC_MII_QSGMII	QSGMII interface.

◆ EnetPhy_Speed

enum EnetPhy_Speed

MAC interface speed.

Enumerator
ENETPHY_SPEED_10MBIT	10 Mbps
ENETPHY_SPEED_100MBIT	100 Mbps
ENETPHY_SPEED_1GBIT	1 Gbps
ENETPHY_SPEED_AUTO	Speed determined automatically

◆ EnetPhy_Duplexity

enum EnetPhy_Duplexity

MAC interface duplexity.

Enumerator
ENETPHY_DUPLEX_HALF	Half duplex
ENETPHY_DUPLEX_FULL	Full duplex
ENETPHY_DUPLEX_AUTO	Duplexity determined automatically

◆ EnetPhy_LinkStatus

enum EnetPhy_LinkStatus

PHY link status.

Enumerator
ENETPHY_GOT_LINK	PHY got link up
ENETPHY_LINK_UP	PHY link is still up
ENETPHY_LOST_LINK	PHY lost link
ENETPHY_LINK_DOWN	PHY link is still down

◆ EnetPhy_FsmState

enum EnetPhy_FsmState

PHY driver state-machine states.

Enumerator
ENETPHY_FSM_STATE_INIT	INIT state.
ENETPHY_FSM_STATE_FINDING	FINDING state.
ENETPHY_FSM_STATE_RESET_WAIT	RESET_WAIT state.
ENETPHY_FSM_STATE_ENABLE	ENABLE state.
ENETPHY_FSM_STATE_FOUND	FOUND state.
ENETPHY_FSM_STATE_NWAY_START	NWAY_START state (auto-negotiation path)
ENETPHY_FSM_STATE_NWAY_WAIT	NWAY_WAIT state (auto-negotiation path)
ENETPHY_FSM_STATE_LINK_WAIT	LINK_WAIT state.
ENETPHY_FSM_STATE_LINKED	LINKED state.
ENETPHY_FSM_STATE_LOOPBACK	LOOPBACK state.

Function Documentation

◆ EnetPhy_initCfg()

void EnetPhy_initCfg ( EnetPhy_Cfg * phyCfg )

Initialize PHY config params.

Initializes PHY driver configuration parameters.

Parameters

phyCfg PHY configuration params

◆ EnetPhy_setExtendedCfg()

void EnetPhy_setExtendedCfg	(	EnetPhy_Cfg *	phyCfg,
		const void *	extendedCfg,
		uint32_t	extendedCfgSize
	)

Set PHY extended parameters.

Sets the PHY-specific extended parameters to the PHY config structure.

Parameters

phyCfg	Pointer to the PHY config
extendedCfg	Pointer to the PHY extended config
extendedCfgSize	Size of the PHY extended config

◆ EnetPhy_open()

EnetPhy_Handle EnetPhy_open	(	const EnetPhy_Cfg *	phyCfg,
		EnetPhy_Mii	mii,
		const EnetPhy_LinkCfg *	linkCfg,
		uint32_t	macPortCaps,
		EnetPhy_MdioHandle	hMdio,
		void *	mdioArgs
	)

Open the PHY driver.

Open the Ethernet PHY driver for the given MAC port number. The PHY driver takes PHY specific configuration parameters, the MAC port type connection and the desired link configuration (auto or manual).

Parameters

phyCfg	PHY configuration params
mii	PHY MII interface type
linkCfg	Link configuration (speed and duplexity)
macPortCaps	MAC port speed/duplex capabilities. It's a bit mask of EnetPhy_LinkCaps
hMdio	MDIO driver to be used for PHY register read/write
mdioArgs	Private data passed to the MDIO driver functions

Returns: PHY device handle if successful, NULL otherwise.

◆ EnetPhy_close()

void EnetPhy_close ( EnetPhy_Handle hPhy )

Close the PHY driver.

Closes the Ethernet PHY driver.

Parameters

hPhy	PHY device handle

◆ EnetPhy_tick()

EnetPhy_LinkStatus EnetPhy_tick ( EnetPhy_Handle hPhy )

Run PHY state machine.

Runs the PHY FSM.

Parameters

hPhy	PHY device handle

Returns: Whether PHY got or lost link, or no change.

◆ EnetPhy_getId()

int32_t EnetPhy_getId	(	EnetPhy_Handle	hPhy,
		EnetPhy_Version *	version
	)

Get PHY id.

Gets the device ID of a PHY, read from IDR1 and IDR2 registers.

Parameters

hPhy	PHY device handle
version	Pointer to PHY version.

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_isAlive()

bool EnetPhy_isAlive ( EnetPhy_Handle hPhy )

Get PHY alive status.

Gets the PHY alive status. Whether PHY is responding to read accesses.

Parameters

hPhy	PHY device handle

Returns: true if PHY is alive, false otherwise

◆ EnetPhy_isLinked()

bool EnetPhy_isLinked ( EnetPhy_Handle hPhy )

Get link status.

Gets the link status: linked or not, based on driver's state machine. The PHY driver state machine can take a little longer to detect link up because it runs on tick period intervals and need to traverse few states to reach link up FSM state.

Parameters

hPhy	PHY device handle

Returns: true if PHY is linked, false otherwise

◆ EnetPhy_getLinkCfg()

int32_t EnetPhy_getLinkCfg	(	EnetPhy_Handle	hPhy,
		EnetPhy_LinkCfg *	linkCfg
	)

Get link configuration.

Gets the link configuration, that is, the configuration that the PHY has negotiated with the link partner or the manual link configuration it was set to.

Parameters

hPhy	PHY device handle
linkCfg	Link configuration

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_readReg()

int32_t EnetPhy_readReg	(	EnetPhy_Handle	hPhy,
		uint32_t	reg,
		uint16_t *	val
	)

Read PHY register.

Reads a PHY register. It's not meant for extended registers.

Parameters

hPhy	PHY device handle
reg	Register number
val	Pointer to the read value

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_writeReg()

int32_t EnetPhy_writeReg	(	EnetPhy_Handle	hPhy,
		uint32_t	reg,
		uint16_t	val
	)

Write PHY register.

Writes a PHY register. It's not meant for extended registers.

Parameters

hPhy	PHY device handle
reg	Register number
val	Value to be written

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_rmwReg()

int32_t EnetPhy_rmwReg	(	EnetPhy_Handle	hPhy,
		uint32_t	reg,
		uint16_t	mask,
		uint16_t	val
	)

Read-modify-write PHY register.

Read-modify-write a PHY register. It's not meant for extended registers.

Parameters

hPhy	PHY device handle
reg	Register number
mask	Bitmask to be applied on read value and value to be written
val	Value to be written

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_readExtReg()

int32_t EnetPhy_readExtReg	(	EnetPhy_Handle	hPhy,
		uint32_t	reg,
		uint16_t *	val
	)

Read PHY extended register.

Reads a PHY extended register.

Parameters

hPhy	PHY device handle
reg	Register number
val	Pointer to the read value

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_writeExtReg()

int32_t EnetPhy_writeExtReg	(	EnetPhy_Handle	hPhy,
		uint32_t	reg,
		uint16_t	val
	)

Write PHY extended register.

Writes a PHY extended register.

Parameters

hPhy	PHY device handle
reg	Register number
val	Value to be written

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_rmwExtReg()

int32_t EnetPhy_rmwExtReg	(	EnetPhy_Handle	hPhy,
		uint32_t	reg,
		uint16_t	mask,
		uint16_t	val
	)

Read-modify-write PHY extended register.

Read-modify-write a PHY extended register.

Parameters

hPhy	PHY device handle
reg	Register number
mask	Bitmask to be applied on read value and value to be written
val	Value to be written

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_readC45Reg()

int32_t EnetPhy_readC45Reg	(	EnetPhy_Handle	hPhy,
		uint8_t	mmd,
		uint32_t	reg,
		uint16_t *	val
	)

Read PHY register using Clause-45 frame.

Reads a PHY register using Clause-45 frame.

Parameters

hPhy	PHY device handle
mmd	MMD
reg	Register number
val	Pointer to the read value

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_writeC45Reg()

int32_t EnetPhy_writeC45Reg	(	EnetPhy_Handle	hPhy,
		uint8_t	mmd,
		uint32_t	reg,
		uint16_t	val
	)

Write PHY register using Clause-45 frame.

Writes a PHY register using Clause-45 frame.

Parameters

hPhy	PHY device handle
mmd	MMD
reg	Register number
val	Value to be written

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_rmwC45Reg()

int32_t EnetPhy_rmwC45Reg	(	EnetPhy_Handle	hPhy,
		uint8_t	mmd,
		uint32_t	reg,
		uint16_t	mask,
		uint16_t	val
	)

Read-modify-write PHY register using Clause-45 frame.

Read-modify-write a PHY register using Clause-45 frame.

Parameters

hPhy	PHY device handle
mmd	MMD
reg	Register number
mask	Bitmask to be applied on read value and value to be written
val	Value to be written

Returns: EnetPhy_ErrorCodes

◆ EnetPhy_printRegs()

void EnetPhy_printRegs ( EnetPhy_Handle hPhy )

Print all PHY registers.

Prints all registers of a PHY.

Parameters

hPhy	PHY device handle

Introduction

Sub Modules

Data Structures

Functions

Typedefs

Enumerations

Macros

Ethernet PHY driver error codes

Ethernet PHY link capability masks

Macro Definition Documentation

◆ ENETPHY_IS_ADDR_VALID

◆ ENETPHY_BIT

◆ ENETPHY_IS_BIT_SET

◆ ENETPHY_ARRAYSIZE

◆ ENETPHY_SOK

◆ ENETPHY_EFAIL

◆ ENETPHY_EBADARGS

◆ ENETPHY_EINVALIDPARAMS

◆ ENETPHY_ETIMEOUT

◆ ENETPHY_EALLOC

◆ ENETPHY_EPERM

◆ ENETPHY_ENOTSUPPORTED

◆ ENETPHY_LINK_CAP_HD10

◆ ENETPHY_LINK_CAP_FD10

◆ ENETPHY_LINK_CAP_HD100

◆ ENETPHY_LINK_CAP_FD100

◆ ENETPHY_LINK_CAP_HD1000

◆ ENETPHY_LINK_CAP_FD1000

◆ ENETPHY_LINK_CAP_10

◆ ENETPHY_LINK_CAP_100

◆ ENETPHY_LINK_CAP_1000

◆ ENETPHY_LINK_CAP_ALL

◆ ENETPHY_EXTENDED_CFG_SIZE_MAX

◆ ENETPHY_FSM_TICK_PERIOD_MS

◆ ENETPHY_INVALID_PHYADDR

Typedef Documentation

◆ EnetPhy_MdioHandle

◆ EnetPhyDrv_Handle

◆ EnetPhy_Handle

Enumeration Type Documentation

◆ EnetPhy_Magic

◆ EnetPhy_Mii

◆ EnetPhy_Speed

◆ EnetPhy_Duplexity

◆ EnetPhy_LinkStatus

◆ EnetPhy_FsmState

Function Documentation

◆ EnetPhy_initCfg()

◆ EnetPhy_setExtendedCfg()

◆ EnetPhy_open()

◆ EnetPhy_close()

◆ EnetPhy_tick()

◆ EnetPhy_getId()

◆ EnetPhy_isAlive()

◆ EnetPhy_isLinked()

◆ EnetPhy_getLinkCfg()

◆ EnetPhy_readReg()

◆ EnetPhy_writeReg()

◆ EnetPhy_rmwReg()

◆ EnetPhy_readExtReg()

◆ EnetPhy_writeExtReg()

◆ EnetPhy_rmwExtReg()

◆ EnetPhy_readC45Reg()

◆ EnetPhy_writeC45Reg()

◆ EnetPhy_rmwC45Reg()

◆ EnetPhy_printRegs()