1. J721E Datasheet¶

1.1.2.4.1. TCP (IP stack) Performance¶

1.1.2.4.2. UDP (IP stack) Performance¶

Not executed due to known issue ETHFW-1904.

Note:

1. TCP/IP throughput results are measured using Enet LLD lwIP example application built with the following modifications which are not PDK’s default settings:
   • lwIP example app built with performance optimizations (OPTIMIZATION=PERFORMANCE passed to make command)
   • Enable Thumb2 mode (CFLAGS_INTERNAL += -mthumb)
2. Current performance numbers are preliminary as throughput profiling is not done in optimized environment (i.e. putting frequently used functions in fast memory, use of pacing using ring monitor, tuning of descriptors, etc.)

1.1.2.5.1. DMA Parameters¶

• Ring Order ID: 0
• Channel Order ID: 0
• Channel DMA Priority: 1
• Channel Bus Priority: 4
• Channel BUS QOS: 4
• Channel TX FIFO depth: 128
• Channel Fetch Word Size: 16
• Channel Burst Size: 64 bytes for normal channel, 128 bytes for HC and UHC channels

1.1.2.5.2. Test Parameters¶

• Type: TR15 Block copy
• TR: one TR per TRPD in PBR mode
• TR Memory: Same as buffer memory (DDR, MSMC or OCMC depends on the test performed)
• Transfer Size: 1 MB read and 1MB write
• 1MB means 1000x1000 bytes and 1KB means 1000 bytes

Note: Throughput numbers mentioned is the combined memory throughput of both read and write operations

1.1.2.5.3. DRU Blockcopy¶

DRU channel performance with TR submitted through ring

1.1.2.5.4. Main NAVSS Blockcopy (Normal Channel)¶

Main NAVSS normal channel performance with TR submitted through ring

1.1.2.5.5. MCU NAVSS Blockcopy (Normal Channel)¶

MCU NAVSS normal channel performance with TR submitted through ring

1.1.2.6.1. Test Set-up¶

• Release build binaries are used for measurement

• Ring Buffer : Uncached DDR

• Buffer to be sent (RPMSG) – Cached DDR

• C66x - L2 Cache 128K

• C7x - L2 Cache 128K

• Software/Application Used : ipc_multicore_perf_test loaded through SBL. Output is printed to UART.

• R5F/MPU config : DDR config

  • bufferable - 1
  • cacheable - 1
  • shareable - 0

Capturing Round trip time in us with different data sizes

1.1.2.6.2. Performance - Host Core A72, Bios, 2 GHz¶

1.1.2.6.3. Performance - Host Core MCU R5F0, 1 GHz¶

1.1.2.6.4. Performance - Host Core MAIN R5F0, 1 GHz¶

1.1.2.6.5. Performance - Host Core C66X1, 1.35 GHz¶

1.1.2.6.6. Performance - Host Core C7x, 1GHz¶

1.1.2.7.1. OSPI Memory Non Cached Test Set-up¶

• Platform: J721e EVM.
• OS Type: Baremetal/Sysbios
• Core : R5F_0 at 1 GHz, A72_0 at 2 GHz.
• Software/Application Used: OSPI_Flash_TestApp/OSPI_Flash_Dma_TestApp/OSPI_Baremetal_Flash_TestApp/OSPI_Baremetal_Flash_Dma_TestApp
• System Configuration: Cache OFF, Read/Write Buffer in DDR. DMA Enabled/Disabled, Interrupts ON.

1.1.2.7.2. OSPI Read/Write Performance (DDR Octal Mode)¶

1.1.2.7.3. OSPI Memory Cached Test Set-up¶

• Platform: J721e EVM.
• OS Type: Baremetal/Sysbios
• Core : R5F_0 at 1 GHz, A72_0 at 2 GHz.
• Software/Application Used: OSPI_Flash_Cache_TestApp/OSPI_Flash_Dma_Cache_TestApp/OSPI_Baremetal_Flash_Cache_TestApp/OSPI_Baremetal_Flash_Dma_Cache_TestApp
• System Configuration: Cache ON, Read/Write Buffer in DDR. DMA Enabled/Disabled, Interrupts ON.

1.1.2.7.4. OSPI Read/Write Performance (DDR Octal Mode)¶

1.1.2.8.1. Test Set-up¶

• Platform: J721e EVM.
• OS Type: Sysbios
• Core : A72_0, 2 GHz.
• Software/Application Used: MMCSD_<EMMC>_Regression_TestApp (A menu based application which outputs the benchmark numbers on UART)
• System Configuration: Cache ON, Read/Write Buffer in DDR. ADMA enabled, Interrupts ON.
• SD Card used: Sandisk 16GB, Class 10. FAT32 formatted with allocation size = 4K (for optimal FAT32 throughput & compatibility with various cards)
• EMMC: EMMC on J721E EVM. Please refer to the EVM data sheet for details

1.1.2.8.2. SD Card Performance¶

1.1.2.8.3. EMMC Performance¶

1.1.2.9.1. CPU Mode - Test Set-up¶

• Platform: J721e EVM.

• OS Type: Baremetal

• Core : R5F_0 at 1 GHz

• Software/Application Used: csl_ospi_flash_app

• System Configuration:

  • RCLK 133/166 MHz
  • Cache ON,
  • Buffer & Critical Fxn’s in TCMB,
  • DMA Disabled,
  • Interrupts OFF.

• Theoretical Max Throughput:

  • 133 MHz :- 253.67 MB/s
  • 166 MHz :- 316.62 MB/s

1.1.2.9.2. DAC Mode OSPI Read Performance (Dual Data Rate - Octal Mode)¶

1.1.2.9.3. DMA Mode - Test Set-up¶

• Platform: J721e EVM.

• OS Type: Baremetal

• Core : R5F_0 at 1 GHz

• Software/Application Used: udma_baremetal_ospi_flash_testapp

• System Configuration:

  • RCLK 133/166 MHz
  • Cache ON,
  • Buffer & Critical Fxn’s in TCMB,
  • DMA Enabled - SW Trigger mode,
  • Interrupts OFF.

• Theoretical Max Throughput:

  • 133 MHz :- 253.67 MB/s
  • 166 MHz :- 316.62 MB/s

1.1.2.9.4. DAC DMA Mode OSPI Read Performance (Dual Data Rate - Octal Mode)¶

1.1.2.10.1. Test Set-up¶

• Platform: J721e EVM.
• OS Type: Baremetal
• Core : R5F_0 at 1 GHz
• Software/Application Used: sbl_cust_img (with custom flags) and sbl_boot_perf_test appimage

1.1.2.10.2. GP EVM Performance¶

1.1.2.12.1. Test Set-up¶

• Platform: J721e EVM.
• OS Type: Sysbios
• Core – MCU Domain R5_0 (MCU1_0) & Main Domain R5_0 (MCU2_0)
• Software/Application Used: sbl_ospi_img and memory_benchmarking_app appimage

1.1.2.12.2. MCU Domain Single Core Execution¶

• Cache miss rate of 3M/sec is between memcpy sizes of 200 and 500 bytes.

1.1.2.12.3. MAIN Domain Single Core Execution¶

• Cache miss rate of 3M/sec is at memcpy size of ~50 bytes.

1.1.2.12.4. MCU Domain Multi-Core Execution¶

• Cache miss rate of 3M/sec is between memcpy sizes of 200 and 500 bytes.

1.1.2.12.5. MAIN Domain Multi-Core Execution¶

• Cache miss rate of 3M/sec is at memcpy size of ~50 bytes.

1.1.2.12.6. Extra OCMC Baseline Details - MCU Domain¶

• View ICM/sec row to see that cache miss rate of 3M/sec is between memcpy sizes of 200 and 500 bytes.

1.1.2.12.7. Extra OCMC Baseline Details - MAIN Domain¶

• View ICM/sec row to see that cache miss rate of 3M/sec is at memcpy size of ~50 bytes.