TIOVX Supported Kernels

Table of Contents

• Legend
• OpenVX Standard Kernels
• TI Extension Kernels

Legend

Meaning of terms in the following tables,

• DMA: Kernel implemented and memory access done using DMA (NOTE: Not enabled in this release)
• Cache: Kernel implemented and memory access done using CPU Cache
• [empty]: Kernel is not supported on target

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OpenVX Standard Kernels

This table lists the mapping of standard OpenVX kernels to compute targets on the Jacinto7 platform. When mapped to C66x DSP, it indicates if it is implemented using BAM DMA acceleration, or cache only.

All of the below kernels default to running on the C66x DSP 1. If a different target is needed, it can be selected from the available targets indicated below by using the vxSetNodeTarget() API.

Kernel	C66x 1	C66x 2	HWA
Absolute Difference	Cache	Cache
Accumulate	Cache	Cache
Accumulate Squared	Cache	Cache
Accumulate Weighted	Cache	Cache
Arithmetic Addition	Cache	Cache
Arithmetic Subtraction	Cache	Cache
Bitwise AND	Cache	Cache
Bitwise EXCLUSIVE OR	Cache	Cache
Bitwise INCLUSIVE OR	Cache	Cache
Bitwise NOT	Cache	Cache
Box Filter	Cache	Cache
Canny Edge Detector	Cache	Cache
Channel Combine	Cache	Cache
Channel Extract	Cache	Cache
Color Convert	Cache	Cache
Convert Bit depth	Cache	Cache
Custom Convolution	Cache	Cache
Dilate Image	Cache	Cache
Equalize Histogram	Cache	Cache
Erode Image	Cache	Cache
Fast Corners	Cache	Cache
Gaussian Filter	Cache	Cache
Non Linear Filter	Cache	Cache
Harris Corners	Cache	Cache
Histogram	Cache	Cache
Gaussian Image Pyramid	Cache	Cache	VPAC_MSC*
Laplacian Image Pyramid	Cache	Cache
Reconstruction from a Laplacian Image Pyramid	Cache	Cache
Integral Image	Cache	Cache
Magnitude	Cache	Cache
Mean and Standard Deviation	Cache	Cache
Median Filter	Cache	Cache
Min, Max Location	Cache	Cache
Optical Flow Pyramid (LK)	Cache	Cache
Phase	Cache	Cache
Pixel-wise Multiplication	Cache	Cache
Remap	Cache	Cache
Scale Image	Cache	Cache	VPAC_MSC*
Sobel 3x3	Cache	Cache
TableLookup	Cache	Cache
Thresholding	Cache	Cache
Warp Affine	Cache	Cache
Warp Perspective	Cache	Cache

• Subset of configuration options and or accuracy tradeoff to speed is to be considered for this HWA implementation.

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TI Extension Kernels

Kernel	Target
tivxCaptureNode	CSIRX
tivxDisplayNode	DSS
tivxTIDLNode	C7x + MMA
tivxVpacVissNode	VPAC_VISS
tivxVpacLdcNode	VPAC_LDC
tivxVpacNfGenericNode	VPAC_NF
tivxVpacNfBilateralNode	VPAC_NF
tivxVpacMscScaleNode	VPAC_MSC
tivxVpacMscPyramidNode	VPAC_MSC
tivxDmpacSdeNode	DMPAC_SDE
tivxDmpacDofNode	DMPAC_DOF
tivxCsitxNode	CSITX
tivxDisplayM2MNode	DSS