65 #define UDMA_INST_ID_MAIN_0 (UDMA_INST_ID_0) 67 #define UDMA_INST_ID_MCU_0 (UDMA_INST_ID_1) 69 #define UDMA_INST_ID_START (UDMA_INST_ID_0) 71 #define UDMA_INST_ID_MAX (UDMA_INST_ID_1) 73 #define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U) 85 #define UDMA_SOC_CFG_UDMAP_PRESENT (1U) 88 #define UDMA_SOC_CFG_LCDMA_PRESENT (0U) 91 #define UDMA_SOC_CFG_PROXY_PRESENT (1U) 94 #define UDMA_SOC_CFG_CLEC_PRESENT (1U) 97 #define UDMA_SOC_CFG_RA_NORMAL_PRESENT (1U) 100 #define UDMA_SOC_CFG_RA_LCDMA_PRESENT (0U) 103 #define UDMA_SOC_CFG_RING_MON_PRESENT (1U) 106 #define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U) 118 #define UDMA_TX_UHC_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_UHC_CHANS_FDEPTH) 120 #define UDMA_TX_HC_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_HC_CHANS_FDEPTH) 122 #define UDMA_TX_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_CHANS_FDEPTH) 134 #define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR (0U) 138 #define UDMA_RING_MODE_INVALID (CSL_RINGACC_RING_MODE_INVALID) 141 #define UDMA_NUM_MAPPED_TX_GROUP (0U) 154 #define UDMA_NUM_MAPPED_RX_GROUP (0U) 167 #define UDMA_NUM_UTC_INSTANCE (CSL_NAVSS_UTC_CNT) 177 #define UDMA_UTC_ID_MSMC_DRU0 (UDMA_UTC_ID0) 178 #define UDMA_UTC_ID_VPAC_TC0 (UDMA_UTC_ID1) 179 #define UDMA_UTC_ID_VPAC_TC1 (UDMA_UTC_ID2) 180 #define UDMA_UTC_ID_DMPAC_TC0 (UDMA_UTC_ID3) 184 #define UDMA_UTC_START_CH_DRU0 (0U) 186 #define UDMA_UTC_NUM_CH_DRU0 (CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_CNT) 188 #define UDMA_UTC_START_THREAD_ID_DRU0 (CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILD_THREAD_OFFSET) 191 #define UDMA_UTC_START_CH_VPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_OFFSET - CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_OFFSET) 193 #define UDMA_UTC_NUM_CH_VPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_CNT) 195 #define UDMA_UTC_START_THREAD_ID_VPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_OFFSET) 198 #define UDMA_UTC_START_CH_VPAC_TC1 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_OFFSET - CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_OFFSET) 200 #define UDMA_UTC_NUM_CH_VPAC_TC1 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_CNT) 202 #define UDMA_UTC_START_THREAD_ID_VPAC_TC1 (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILD_THREAD_OFFSET) 205 #define UDMA_UTC_START_CH_DMPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_OFFSET - CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_OFFSET) 207 #define UDMA_UTC_NUM_CH_DMPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_CNT) 209 #define UDMA_UTC_START_THREAD_ID_DMPAC_TC0 (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILD_THREAD_OFFSET) 224 #define UDMA_CORE_ID_MPU1_0 (0U) 225 #define UDMA_CORE_ID_MCU2_0 (1U) 226 #define UDMA_CORE_ID_MCU2_1 (2U) 227 #define UDMA_CORE_ID_MCU3_0 (3U) 228 #define UDMA_CORE_ID_MCU3_1 (4U) 229 #define UDMA_CORE_ID_C7X_1 (5U) 230 #define UDMA_CORE_ID_C66X_1 (6U) 231 #define UDMA_CORE_ID_C66X_2 (7U) 232 #define UDMA_NUM_MAIN_CORE (8U) 234 #define UDMA_CORE_ID_MCU1_0 (UDMA_NUM_MAIN_CORE + 0U) 235 #define UDMA_CORE_ID_MCU1_1 (UDMA_NUM_MAIN_CORE + 1U) 236 #define UDMA_NUM_MCU_CORE (2U) 238 #define UDMA_NUM_CORE (UDMA_NUM_MAIN_CORE + UDMA_NUM_MCU_CORE) 257 #define UDMA_DRU_CORE_ID_MPU1_0 (CSL_DRU_CORE_ID_2) 258 #define UDMA_DRU_CORE_ID_MCU2_0 (CSL_DRU_CORE_ID_2) 259 #define UDMA_DRU_CORE_ID_MCU2_1 (CSL_DRU_CORE_ID_2) 260 #define UDMA_DRU_CORE_ID_MCU3_0 (CSL_DRU_CORE_ID_2) 261 #define UDMA_DRU_CORE_ID_MCU3_1 (CSL_DRU_CORE_ID_2) 262 #define UDMA_DRU_CORE_ID_C7X_1 (CSL_DRU_CORE_ID_0) 263 #define UDMA_DRU_CORE_ID_C66X_1 (CSL_DRU_CORE_ID_1) 264 #define UDMA_DRU_CORE_ID_C66X_2 (CSL_DRU_CORE_ID_2) 265 #define UDMA_DRU_CORE_ID_MCU1_0 (CSL_DRU_CORE_ID_2) 266 #define UDMA_DRU_CORE_ID_MCU1_1 (CSL_DRU_CORE_ID_2) 278 #define UDMA_RM_RES_ID_TX_UHC (0U) 280 #define UDMA_RM_RES_ID_TX_HC (1U) 282 #define UDMA_RM_RES_ID_TX (2U) 284 #define UDMA_RM_RES_ID_RX_UHC (3U) 286 #define UDMA_RM_RES_ID_RX_HC (4U) 288 #define UDMA_RM_RES_ID_RX (5U) 290 #define UDMA_RM_RES_ID_UTC (6U) 292 #define UDMA_RM_RES_ID_RX_FLOW (7U) 294 #define UDMA_RM_RES_ID_RING (8U) 296 #define UDMA_RM_RES_ID_GLOBAL_EVENT (9U) 298 #define UDMA_RM_RES_ID_VINTR (10U) 300 #define UDMA_RM_RES_ID_IR_INTR (11U) 302 #define UDMA_RM_RES_ID_PROXY (12U) 304 #define UDMA_RM_RES_ID_RING_MON (13U) 306 #define UDMA_RM_NUM_RES (14U) 311 #define UDMA_RM_NUM_SHARED_RES (4U) 314 #define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE) 320 #define UDMA_C7X_CORE_INTR_OFFSET (48U) 322 #define UDMA_C66X_CORE_INTR_OFFSET (32U) 341 #define UDMA_PSIL_CH_MAIN_SAUL0_TX (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILD_THREAD_OFFSET) 342 #define UDMA_PSIL_CH_MAIN_ICSS_G0_TX (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET) 343 #define UDMA_PSIL_CH_MAIN_ICSS_G1_TX (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET) 344 #define UDMA_PSIL_CH_MAIN_VPAC_TC0_TX (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_OFFSET) 345 #define UDMA_PSIL_CH_MAIN_VPAC_TC1_TX (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILD_THREAD_OFFSET) 346 #define UDMA_PSIL_CH_MAIN_DMPAC_TC0_TX (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILD_THREAD_OFFSET) 347 #define UDMA_PSIL_CH_MAIN_CSI_TX (CSL_PSILCFG_NAVSS_MAIN_CSI_PSILD_THREAD_OFFSET) 348 #define UDMA_PSIL_CH_MAIN_CPSW9_TX (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILD_THREAD_OFFSET) 350 #define UDMA_PSIL_CH_MAIN_SAUL0_RX (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILS_THREAD_OFFSET) 351 #define UDMA_PSIL_CH_MAIN_ICSS_G0_RX (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILS_THREAD_OFFSET) 352 #define UDMA_PSIL_CH_MAIN_ICSS_G1_RX (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILS_THREAD_OFFSET) 353 #define UDMA_PSIL_CH_MAIN_VPAC_TC0_RX (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_OFFSET) 354 #define UDMA_PSIL_CH_MAIN_VPAC_TC1_RX (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_OFFSET) 355 #define UDMA_PSIL_CH_MAIN_DMPAC_TC0_RX (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_OFFSET) 356 #define UDMA_PSIL_CH_MAIN_CSI_RX (CSL_PSILCFG_NAVSS_MAIN_CSI_PSILS_THREAD_OFFSET) 357 #define UDMA_PSIL_CH_MAIN_CPSW9_RX (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILS_THREAD_OFFSET) 359 #define UDMA_PSIL_CH_MAIN_SAUL0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILD_THREAD_CNT) 360 #define UDMA_PSIL_CH_MAIN_ICSS_G0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_CNT) 361 #define UDMA_PSIL_CH_MAIN_ICSS_G1_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_CNT) 362 #define UDMA_PSIL_CH_MAIN_VPAC_TC0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_CNT) 363 #define UDMA_PSIL_CH_MAIN_VPAC_TC1_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILD_THREAD_CNT) 364 #define UDMA_PSIL_CH_MAIN_DMPAC_TC0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILD_THREAD_CNT) 365 #define UDMA_PSIL_CH_MAIN_VPAC_TC1_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC1_CC_PSILS_THREAD_CNT) 366 #define UDMA_PSIL_CH_MAIN_DMPAC_TC0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_DMPAC_TC0_CC_PSILS_THREAD_CNT) 368 #define UDMA_PSIL_CH_MAIN_SAUL0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILS_THREAD_CNT) 369 #define UDMA_PSIL_CH_MAIN_ICSS_G0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILS_THREAD_CNT) 370 #define UDMA_PSIL_CH_MAIN_ICSS_G1_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILS_THREAD_CNT) 371 #define UDMA_PSIL_CH_MAIN_VPAC_TC0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_CNT) 372 #define UDMA_PSIL_CH_MAIN_CSI_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_CSI_PSILD_THREAD_CNT) 373 #define UDMA_PSIL_CH_MAIN_CPSW9_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILD_THREAD_CNT) 374 #define UDMA_PSIL_CH_MAIN_CSI_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_CSI_PSILS_THREAD_CNT) 375 #define UDMA_PSIL_CH_MAIN_CPSW9_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILS_THREAD_CNT) 386 #define UDMA_PSIL_CH_MCU_CPSW0_TX (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_OFFSET) 387 #define UDMA_PSIL_CH_MCU_SAUL0_TX (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILD_THREAD_OFFSET) 389 #define UDMA_PSIL_CH_MCU_CPSW0_RX (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_OFFSET) 390 #define UDMA_PSIL_CH_MCU_SAUL0_RX (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILS_THREAD_OFFSET) 392 #define UDMA_PSIL_CH_MCU_CPSW0_TX_CNT (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_CNT) 393 #define UDMA_PSIL_CH_MCU_SAUL0_TX_CNT (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILD_THREAD_CNT) 395 #define UDMA_PSIL_CH_MCU_CPSW0_RX_CNT (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_CNT) 396 #define UDMA_PSIL_CH_MCU_SAUL0_RX_CNT (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILS_THREAD_CNT) 421 #define UDMA_PDMA_CH_MAIN_MCASP0_TX (CSL_PDMA_CH_MAIN_MCASP0_CH0_TX) 422 #define UDMA_PDMA_CH_MAIN_MCASP1_TX (CSL_PDMA_CH_MAIN_MCASP1_CH0_TX) 423 #define UDMA_PDMA_CH_MAIN_MCASP2_TX (CSL_PDMA_CH_MAIN_MCASP2_CH0_TX) 424 #define UDMA_PDMA_CH_MAIN_MCASP3_TX (CSL_PDMA_CH_MAIN_MCASP3_CH0_TX) 425 #define UDMA_PDMA_CH_MAIN_MCASP4_TX (CSL_PDMA_CH_MAIN_MCASP4_CH0_TX) 426 #define UDMA_PDMA_CH_MAIN_MCASP5_TX (CSL_PDMA_CH_MAIN_MCASP5_CH0_TX) 427 #define UDMA_PDMA_CH_MAIN_MCASP6_TX (CSL_PDMA_CH_MAIN_MCASP6_CH0_TX) 428 #define UDMA_PDMA_CH_MAIN_MCASP7_TX (CSL_PDMA_CH_MAIN_MCASP7_CH0_TX) 429 #define UDMA_PDMA_CH_MAIN_MCASP8_TX (CSL_PDMA_CH_MAIN_MCASP8_CH0_TX) 430 #define UDMA_PDMA_CH_MAIN_MCASP9_TX (CSL_PDMA_CH_MAIN_MCASP9_CH0_TX) 431 #define UDMA_PDMA_CH_MAIN_MCASP10_TX (CSL_PDMA_CH_MAIN_MCASP10_CH0_TX) 432 #define UDMA_PDMA_CH_MAIN_MCASP11_TX (CSL_PDMA_CH_MAIN_MCASP11_CH0_TX) 436 #define UDMA_PDMA_CH_MAIN_AASRC0_CH0_TX (CSL_PDMA_CH_MAIN_AASRC0_CH0_TX) 437 #define UDMA_PDMA_CH_MAIN_AASRC0_CH1_TX (CSL_PDMA_CH_MAIN_AASRC0_CH1_TX) 438 #define UDMA_PDMA_CH_MAIN_AASRC0_CH2_TX (CSL_PDMA_CH_MAIN_AASRC0_CH2_TX) 439 #define UDMA_PDMA_CH_MAIN_AASRC0_CH3_TX (CSL_PDMA_CH_MAIN_AASRC0_CH3_TX) 440 #define UDMA_PDMA_CH_MAIN_AASRC0_CH4_TX (CSL_PDMA_CH_MAIN_AASRC0_CH4_TX) 441 #define UDMA_PDMA_CH_MAIN_AASRC0_CH5_TX (CSL_PDMA_CH_MAIN_AASRC0_CH5_TX) 442 #define UDMA_PDMA_CH_MAIN_AASRC0_CH6_TX (CSL_PDMA_CH_MAIN_AASRC0_CH6_TX) 443 #define UDMA_PDMA_CH_MAIN_AASRC0_CH7_TX (CSL_PDMA_CH_MAIN_AASRC0_CH7_TX) 447 #define UDMA_PDMA_CH_MAIN_UART0_TX (CSL_PDMA_CH_MAIN_UART0_CH0_TX) 448 #define UDMA_PDMA_CH_MAIN_UART1_TX (CSL_PDMA_CH_MAIN_UART1_CH0_TX) 449 #define UDMA_PDMA_CH_MAIN_UART2_TX (CSL_PDMA_CH_MAIN_UART2_CH0_TX) 450 #define UDMA_PDMA_CH_MAIN_UART3_TX (CSL_PDMA_CH_MAIN_UART3_CH0_TX) 451 #define UDMA_PDMA_CH_MAIN_UART4_TX (CSL_PDMA_CH_MAIN_UART4_CH0_TX) 452 #define UDMA_PDMA_CH_MAIN_UART5_TX (CSL_PDMA_CH_MAIN_UART5_CH0_TX) 453 #define UDMA_PDMA_CH_MAIN_UART6_TX (CSL_PDMA_CH_MAIN_UART6_CH0_TX) 454 #define UDMA_PDMA_CH_MAIN_UART7_TX (CSL_PDMA_CH_MAIN_UART7_CH0_TX) 455 #define UDMA_PDMA_CH_MAIN_UART8_TX (CSL_PDMA_CH_MAIN_UART8_CH0_TX) 456 #define UDMA_PDMA_CH_MAIN_UART9_TX (CSL_PDMA_CH_MAIN_UART9_CH0_TX) 460 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_TX) 461 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_TX) 462 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_TX) 463 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_TX) 464 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_TX) 465 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_TX) 466 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_TX) 467 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_TX) 468 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_TX) 469 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_TX) 470 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_TX) 471 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_TX) 472 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_TX) 473 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_TX) 474 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_TX) 475 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_TX) 476 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_TX) 477 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_TX) 478 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_TX) 479 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_TX) 480 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH0_TX) 481 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH1_TX) 482 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH2_TX) 483 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH3_TX) 484 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH0_TX) 485 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH1_TX) 486 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH2_TX) 487 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH3_TX) 488 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH0_TX) 489 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH1_TX) 490 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH2_TX) 491 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH3_TX) 495 #define UDMA_PDMA_CH_MAIN_MCAN0_CH0_TX (CSL_PDMA_CH_MAIN_MCAN0_CH0_TX) 496 #define UDMA_PDMA_CH_MAIN_MCAN0_CH1_TX (CSL_PDMA_CH_MAIN_MCAN0_CH1_TX) 497 #define UDMA_PDMA_CH_MAIN_MCAN0_CH2_TX (CSL_PDMA_CH_MAIN_MCAN0_CH2_TX) 498 #define UDMA_PDMA_CH_MAIN_MCAN1_CH0_TX (CSL_PDMA_CH_MAIN_MCAN1_CH0_TX) 499 #define UDMA_PDMA_CH_MAIN_MCAN1_CH1_TX (CSL_PDMA_CH_MAIN_MCAN1_CH1_TX) 500 #define UDMA_PDMA_CH_MAIN_MCAN1_CH2_TX (CSL_PDMA_CH_MAIN_MCAN1_CH2_TX) 501 #define UDMA_PDMA_CH_MAIN_MCAN2_CH0_TX (CSL_PDMA_CH_MAIN_MCAN2_CH0_TX) 502 #define UDMA_PDMA_CH_MAIN_MCAN2_CH1_TX (CSL_PDMA_CH_MAIN_MCAN2_CH1_TX) 503 #define UDMA_PDMA_CH_MAIN_MCAN2_CH2_TX (CSL_PDMA_CH_MAIN_MCAN2_CH2_TX) 504 #define UDMA_PDMA_CH_MAIN_MCAN3_CH0_TX (CSL_PDMA_CH_MAIN_MCAN3_CH0_TX) 505 #define UDMA_PDMA_CH_MAIN_MCAN3_CH1_TX (CSL_PDMA_CH_MAIN_MCAN3_CH1_TX) 506 #define UDMA_PDMA_CH_MAIN_MCAN3_CH2_TX (CSL_PDMA_CH_MAIN_MCAN3_CH2_TX) 507 #define UDMA_PDMA_CH_MAIN_MCAN4_CH0_TX (CSL_PDMA_CH_MAIN_MCAN4_CH0_TX) 508 #define UDMA_PDMA_CH_MAIN_MCAN4_CH1_TX (CSL_PDMA_CH_MAIN_MCAN4_CH1_TX) 509 #define UDMA_PDMA_CH_MAIN_MCAN4_CH2_TX (CSL_PDMA_CH_MAIN_MCAN4_CH2_TX) 510 #define UDMA_PDMA_CH_MAIN_MCAN5_CH0_TX (CSL_PDMA_CH_MAIN_MCAN5_CH0_TX) 511 #define UDMA_PDMA_CH_MAIN_MCAN5_CH1_TX (CSL_PDMA_CH_MAIN_MCAN5_CH1_TX) 512 #define UDMA_PDMA_CH_MAIN_MCAN5_CH2_TX (CSL_PDMA_CH_MAIN_MCAN5_CH2_TX) 513 #define UDMA_PDMA_CH_MAIN_MCAN6_CH0_TX (CSL_PDMA_CH_MAIN_MCAN6_CH0_TX) 514 #define UDMA_PDMA_CH_MAIN_MCAN6_CH1_TX (CSL_PDMA_CH_MAIN_MCAN6_CH1_TX) 515 #define UDMA_PDMA_CH_MAIN_MCAN6_CH2_TX (CSL_PDMA_CH_MAIN_MCAN6_CH2_TX) 516 #define UDMA_PDMA_CH_MAIN_MCAN7_CH0_TX (CSL_PDMA_CH_MAIN_MCAN7_CH0_TX) 517 #define UDMA_PDMA_CH_MAIN_MCAN7_CH1_TX (CSL_PDMA_CH_MAIN_MCAN7_CH1_TX) 518 #define UDMA_PDMA_CH_MAIN_MCAN7_CH2_TX (CSL_PDMA_CH_MAIN_MCAN7_CH2_TX) 519 #define UDMA_PDMA_CH_MAIN_MCAN8_CH0_TX (CSL_PDMA_CH_MAIN_MCAN8_CH0_TX) 520 #define UDMA_PDMA_CH_MAIN_MCAN8_CH1_TX (CSL_PDMA_CH_MAIN_MCAN8_CH1_TX) 521 #define UDMA_PDMA_CH_MAIN_MCAN8_CH2_TX (CSL_PDMA_CH_MAIN_MCAN8_CH2_TX) 522 #define UDMA_PDMA_CH_MAIN_MCAN9_CH0_TX (CSL_PDMA_CH_MAIN_MCAN9_CH0_TX) 523 #define UDMA_PDMA_CH_MAIN_MCAN9_CH1_TX (CSL_PDMA_CH_MAIN_MCAN9_CH1_TX) 524 #define UDMA_PDMA_CH_MAIN_MCAN9_CH2_TX (CSL_PDMA_CH_MAIN_MCAN9_CH2_TX) 525 #define UDMA_PDMA_CH_MAIN_MCAN10_CH0_TX (CSL_PDMA_CH_MAIN_MCAN10_CH0_TX) 526 #define UDMA_PDMA_CH_MAIN_MCAN10_CH1_TX (CSL_PDMA_CH_MAIN_MCAN10_CH1_TX) 527 #define UDMA_PDMA_CH_MAIN_MCAN10_CH2_TX (CSL_PDMA_CH_MAIN_MCAN10_CH2_TX) 528 #define UDMA_PDMA_CH_MAIN_MCAN11_CH0_TX (CSL_PDMA_CH_MAIN_MCAN11_CH0_TX) 529 #define UDMA_PDMA_CH_MAIN_MCAN11_CH1_TX (CSL_PDMA_CH_MAIN_MCAN11_CH1_TX) 530 #define UDMA_PDMA_CH_MAIN_MCAN11_CH2_TX (CSL_PDMA_CH_MAIN_MCAN11_CH2_TX) 531 #define UDMA_PDMA_CH_MAIN_MCAN12_CH0_TX (CSL_PDMA_CH_MAIN_MCAN12_CH0_TX) 532 #define UDMA_PDMA_CH_MAIN_MCAN12_CH1_TX (CSL_PDMA_CH_MAIN_MCAN12_CH1_TX) 533 #define UDMA_PDMA_CH_MAIN_MCAN12_CH2_TX (CSL_PDMA_CH_MAIN_MCAN12_CH2_TX) 534 #define UDMA_PDMA_CH_MAIN_MCAN13_CH0_TX (CSL_PDMA_CH_MAIN_MCAN13_CH0_TX) 535 #define UDMA_PDMA_CH_MAIN_MCAN13_CH1_TX (CSL_PDMA_CH_MAIN_MCAN13_CH1_TX) 536 #define UDMA_PDMA_CH_MAIN_MCAN13_CH2_TX (CSL_PDMA_CH_MAIN_MCAN13_CH2_TX) 550 #define UDMA_PDMA_CH_MCU_MCSPI0_CH0_TX (CSL_PDMA_CH_MCU_MCSPI0_CH0_TX) 551 #define UDMA_PDMA_CH_MCU_MCSPI0_CH1_TX (CSL_PDMA_CH_MCU_MCSPI0_CH1_TX) 552 #define UDMA_PDMA_CH_MCU_MCSPI0_CH2_TX (CSL_PDMA_CH_MCU_MCSPI0_CH2_TX) 553 #define UDMA_PDMA_CH_MCU_MCSPI0_CH3_TX (CSL_PDMA_CH_MCU_MCSPI0_CH3_TX) 554 #define UDMA_PDMA_CH_MCU_MCSPI1_CH0_TX (CSL_PDMA_CH_MCU_MCSPI1_CH0_TX) 555 #define UDMA_PDMA_CH_MCU_MCSPI1_CH1_TX (CSL_PDMA_CH_MCU_MCSPI1_CH1_TX) 556 #define UDMA_PDMA_CH_MCU_MCSPI1_CH2_TX (CSL_PDMA_CH_MCU_MCSPI1_CH2_TX) 557 #define UDMA_PDMA_CH_MCU_MCSPI1_CH3_TX (CSL_PDMA_CH_MCU_MCSPI1_CH3_TX) 558 #define UDMA_PDMA_CH_MCU_MCSPI2_CH0_TX (CSL_PDMA_CH_MCU_MCSPI2_CH0_TX) 559 #define UDMA_PDMA_CH_MCU_MCSPI2_CH1_TX (CSL_PDMA_CH_MCU_MCSPI2_CH1_TX) 560 #define UDMA_PDMA_CH_MCU_MCSPI2_CH2_TX (CSL_PDMA_CH_MCU_MCSPI2_CH2_TX) 561 #define UDMA_PDMA_CH_MCU_MCSPI2_CH3_TX (CSL_PDMA_CH_MCU_MCSPI2_CH3_TX) 565 #define UDMA_PDMA_CH_MCU_MCAN0_CH0_TX (CSL_PDMA_CH_MCU_MCAN0_CH0_TX) 566 #define UDMA_PDMA_CH_MCU_MCAN0_CH1_TX (CSL_PDMA_CH_MCU_MCAN0_CH1_TX) 567 #define UDMA_PDMA_CH_MCU_MCAN0_CH2_TX (CSL_PDMA_CH_MCU_MCAN0_CH2_TX) 568 #define UDMA_PDMA_CH_MCU_MCAN1_CH0_TX (CSL_PDMA_CH_MCU_MCAN1_CH0_TX) 569 #define UDMA_PDMA_CH_MCU_MCAN1_CH1_TX (CSL_PDMA_CH_MCU_MCAN1_CH1_TX) 570 #define UDMA_PDMA_CH_MCU_MCAN1_CH2_TX (CSL_PDMA_CH_MCU_MCAN1_CH2_TX) 574 #define UDMA_PDMA_CH_MCU_UART0_TX (CSL_PDMA_CH_MCU_UART0_CH0_TX) 588 #define UDMA_PDMA_CH_MAIN_MCASP0_RX (CSL_PDMA_CH_MAIN_MCASP0_CH0_RX) 589 #define UDMA_PDMA_CH_MAIN_MCASP1_RX (CSL_PDMA_CH_MAIN_MCASP1_CH0_RX) 590 #define UDMA_PDMA_CH_MAIN_MCASP2_RX (CSL_PDMA_CH_MAIN_MCASP2_CH0_RX) 591 #define UDMA_PDMA_CH_MAIN_MCASP3_RX (CSL_PDMA_CH_MAIN_MCASP3_CH0_RX) 592 #define UDMA_PDMA_CH_MAIN_MCASP4_RX (CSL_PDMA_CH_MAIN_MCASP4_CH0_RX) 593 #define UDMA_PDMA_CH_MAIN_MCASP5_RX (CSL_PDMA_CH_MAIN_MCASP5_CH0_RX) 594 #define UDMA_PDMA_CH_MAIN_MCASP6_RX (CSL_PDMA_CH_MAIN_MCASP6_CH0_RX) 595 #define UDMA_PDMA_CH_MAIN_MCASP7_RX (CSL_PDMA_CH_MAIN_MCASP7_CH0_RX) 596 #define UDMA_PDMA_CH_MAIN_MCASP8_RX (CSL_PDMA_CH_MAIN_MCASP8_CH0_RX) 597 #define UDMA_PDMA_CH_MAIN_MCASP9_RX (CSL_PDMA_CH_MAIN_MCASP9_CH0_RX) 598 #define UDMA_PDMA_CH_MAIN_MCASP10_RX (CSL_PDMA_CH_MAIN_MCASP10_CH0_RX) 599 #define UDMA_PDMA_CH_MAIN_MCASP11_RX (CSL_PDMA_CH_MAIN_MCASP11_CH0_RX) 603 #define UDMA_PDMA_CH_MAIN_AASRC0_CH0_RX (CSL_PDMA_CH_MAIN_AASRC0_CH0_RX) 604 #define UDMA_PDMA_CH_MAIN_AASRC0_CH1_RX (CSL_PDMA_CH_MAIN_AASRC0_CH1_RX) 605 #define UDMA_PDMA_CH_MAIN_AASRC0_CH2_RX (CSL_PDMA_CH_MAIN_AASRC0_CH2_RX) 606 #define UDMA_PDMA_CH_MAIN_AASRC0_CH3_RX (CSL_PDMA_CH_MAIN_AASRC0_CH3_RX) 607 #define UDMA_PDMA_CH_MAIN_AASRC0_CH4_RX (CSL_PDMA_CH_MAIN_AASRC0_CH4_RX) 608 #define UDMA_PDMA_CH_MAIN_AASRC0_CH5_RX (CSL_PDMA_CH_MAIN_AASRC0_CH5_RX) 609 #define UDMA_PDMA_CH_MAIN_AASRC0_CH6_RX (CSL_PDMA_CH_MAIN_AASRC0_CH6_RX) 610 #define UDMA_PDMA_CH_MAIN_AASRC0_CH7_RX (CSL_PDMA_CH_MAIN_AASRC0_CH7_RX) 614 #define UDMA_PDMA_CH_MAIN_UART0_RX (CSL_PDMA_CH_MAIN_UART0_CH0_RX) 615 #define UDMA_PDMA_CH_MAIN_UART1_RX (CSL_PDMA_CH_MAIN_UART1_CH0_RX) 616 #define UDMA_PDMA_CH_MAIN_UART2_RX (CSL_PDMA_CH_MAIN_UART2_CH0_RX) 617 #define UDMA_PDMA_CH_MAIN_UART3_RX (CSL_PDMA_CH_MAIN_UART3_CH0_RX) 618 #define UDMA_PDMA_CH_MAIN_UART4_RX (CSL_PDMA_CH_MAIN_UART4_CH0_RX) 619 #define UDMA_PDMA_CH_MAIN_UART5_RX (CSL_PDMA_CH_MAIN_UART5_CH0_RX) 620 #define UDMA_PDMA_CH_MAIN_UART6_RX (CSL_PDMA_CH_MAIN_UART6_CH0_RX) 621 #define UDMA_PDMA_CH_MAIN_UART7_RX (CSL_PDMA_CH_MAIN_UART7_CH0_RX) 622 #define UDMA_PDMA_CH_MAIN_UART8_RX (CSL_PDMA_CH_MAIN_UART8_CH0_RX) 623 #define UDMA_PDMA_CH_MAIN_UART9_RX (CSL_PDMA_CH_MAIN_UART9_CH0_RX) 627 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_RX) 628 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_RX) 629 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_RX) 630 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_RX) 631 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_RX) 632 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_RX) 633 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_RX) 634 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_RX) 635 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_RX) 636 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_RX) 637 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_RX) 638 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_RX) 639 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_RX) 640 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_RX) 641 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_RX) 642 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_RX) 643 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_RX) 644 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_RX) 645 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_RX) 646 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_RX) 647 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH0_RX) 648 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH1_RX) 649 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH2_RX) 650 #define UDMA_PDMA_CH_MAIN_MCSPI5_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH3_RX) 651 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH0_RX) 652 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH1_RX) 653 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH2_RX) 654 #define UDMA_PDMA_CH_MAIN_MCSPI6_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH3_RX) 655 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH0_RX) 656 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH1_RX) 657 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH2_RX) 658 #define UDMA_PDMA_CH_MAIN_MCSPI7_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH3_RX) 662 #define UDMA_PDMA_CH_MAIN_MCAN0_CH0_RX (CSL_PDMA_CH_MAIN_MCAN0_CH0_RX) 663 #define UDMA_PDMA_CH_MAIN_MCAN0_CH1_RX (CSL_PDMA_CH_MAIN_MCAN0_CH1_RX) 664 #define UDMA_PDMA_CH_MAIN_MCAN0_CH2_RX (CSL_PDMA_CH_MAIN_MCAN0_CH2_RX) 665 #define UDMA_PDMA_CH_MAIN_MCAN1_CH0_RX (CSL_PDMA_CH_MAIN_MCAN1_CH0_RX) 666 #define UDMA_PDMA_CH_MAIN_MCAN1_CH1_RX (CSL_PDMA_CH_MAIN_MCAN1_CH1_RX) 667 #define UDMA_PDMA_CH_MAIN_MCAN1_CH2_RX (CSL_PDMA_CH_MAIN_MCAN1_CH2_RX) 668 #define UDMA_PDMA_CH_MAIN_MCAN2_CH0_RX (CSL_PDMA_CH_MAIN_MCAN2_CH0_RX) 669 #define UDMA_PDMA_CH_MAIN_MCAN2_CH1_RX (CSL_PDMA_CH_MAIN_MCAN2_CH1_RX) 670 #define UDMA_PDMA_CH_MAIN_MCAN2_CH2_RX (CSL_PDMA_CH_MAIN_MCAN2_CH2_RX) 671 #define UDMA_PDMA_CH_MAIN_MCAN3_CH0_RX (CSL_PDMA_CH_MAIN_MCAN3_CH0_RX) 672 #define UDMA_PDMA_CH_MAIN_MCAN3_CH1_RX (CSL_PDMA_CH_MAIN_MCAN3_CH1_RX) 673 #define UDMA_PDMA_CH_MAIN_MCAN3_CH2_RX (CSL_PDMA_CH_MAIN_MCAN3_CH2_RX) 674 #define UDMA_PDMA_CH_MAIN_MCAN4_CH0_RX (CSL_PDMA_CH_MAIN_MCAN4_CH0_RX) 675 #define UDMA_PDMA_CH_MAIN_MCAN4_CH1_RX (CSL_PDMA_CH_MAIN_MCAN4_CH1_RX) 676 #define UDMA_PDMA_CH_MAIN_MCAN4_CH2_RX (CSL_PDMA_CH_MAIN_MCAN4_CH2_RX) 677 #define UDMA_PDMA_CH_MAIN_MCAN5_CH0_RX (CSL_PDMA_CH_MAIN_MCAN5_CH0_RX) 678 #define UDMA_PDMA_CH_MAIN_MCAN5_CH1_RX (CSL_PDMA_CH_MAIN_MCAN5_CH1_RX) 679 #define UDMA_PDMA_CH_MAIN_MCAN5_CH2_RX (CSL_PDMA_CH_MAIN_MCAN5_CH2_RX) 680 #define UDMA_PDMA_CH_MAIN_MCAN6_CH0_RX (CSL_PDMA_CH_MAIN_MCAN6_CH0_RX) 681 #define UDMA_PDMA_CH_MAIN_MCAN6_CH1_RX (CSL_PDMA_CH_MAIN_MCAN6_CH1_RX) 682 #define UDMA_PDMA_CH_MAIN_MCAN6_CH2_RX (CSL_PDMA_CH_MAIN_MCAN6_CH2_RX) 683 #define UDMA_PDMA_CH_MAIN_MCAN7_CH0_RX (CSL_PDMA_CH_MAIN_MCAN7_CH0_RX) 684 #define UDMA_PDMA_CH_MAIN_MCAN7_CH1_RX (CSL_PDMA_CH_MAIN_MCAN7_CH1_RX) 685 #define UDMA_PDMA_CH_MAIN_MCAN7_CH2_RX (CSL_PDMA_CH_MAIN_MCAN7_CH2_RX) 686 #define UDMA_PDMA_CH_MAIN_MCAN8_CH0_RX (CSL_PDMA_CH_MAIN_MCAN8_CH0_RX) 687 #define UDMA_PDMA_CH_MAIN_MCAN8_CH1_RX (CSL_PDMA_CH_MAIN_MCAN8_CH1_RX) 688 #define UDMA_PDMA_CH_MAIN_MCAN8_CH2_RX (CSL_PDMA_CH_MAIN_MCAN8_CH2_RX) 689 #define UDMA_PDMA_CH_MAIN_MCAN9_CH0_RX (CSL_PDMA_CH_MAIN_MCAN9_CH0_RX) 690 #define UDMA_PDMA_CH_MAIN_MCAN9_CH1_RX (CSL_PDMA_CH_MAIN_MCAN9_CH1_RX) 691 #define UDMA_PDMA_CH_MAIN_MCAN9_CH2_RX (CSL_PDMA_CH_MAIN_MCAN9_CH2_RX) 692 #define UDMA_PDMA_CH_MAIN_MCAN10_CH0_RX (CSL_PDMA_CH_MAIN_MCAN10_CH0_RX) 693 #define UDMA_PDMA_CH_MAIN_MCAN10_CH1_RX (CSL_PDMA_CH_MAIN_MCAN10_CH1_RX) 694 #define UDMA_PDMA_CH_MAIN_MCAN10_CH2_RX (CSL_PDMA_CH_MAIN_MCAN10_CH2_RX) 695 #define UDMA_PDMA_CH_MAIN_MCAN11_CH0_RX (CSL_PDMA_CH_MAIN_MCAN11_CH0_RX) 696 #define UDMA_PDMA_CH_MAIN_MCAN11_CH1_RX (CSL_PDMA_CH_MAIN_MCAN11_CH1_RX) 697 #define UDMA_PDMA_CH_MAIN_MCAN11_CH2_RX (CSL_PDMA_CH_MAIN_MCAN11_CH2_RX) 698 #define UDMA_PDMA_CH_MAIN_MCAN12_CH0_RX (CSL_PDMA_CH_MAIN_MCAN12_CH0_RX) 699 #define UDMA_PDMA_CH_MAIN_MCAN12_CH1_RX (CSL_PDMA_CH_MAIN_MCAN12_CH1_RX) 700 #define UDMA_PDMA_CH_MAIN_MCAN12_CH2_RX (CSL_PDMA_CH_MAIN_MCAN12_CH2_RX) 701 #define UDMA_PDMA_CH_MAIN_MCAN13_CH0_RX (CSL_PDMA_CH_MAIN_MCAN13_CH0_RX) 702 #define UDMA_PDMA_CH_MAIN_MCAN13_CH1_RX (CSL_PDMA_CH_MAIN_MCAN13_CH1_RX) 703 #define UDMA_PDMA_CH_MAIN_MCAN13_CH2_RX (CSL_PDMA_CH_MAIN_MCAN13_CH2_RX) 717 #define UDMA_PDMA_CH_MCU_ADC0_CH0_RX (CSL_PDMA_CH_MCU_ADC0_CH0_RX) 718 #define UDMA_PDMA_CH_MCU_ADC0_CH1_RX (CSL_PDMA_CH_MCU_ADC0_CH1_RX) 719 #define UDMA_PDMA_CH_MCU_ADC1_CH0_RX (CSL_PDMA_CH_MCU_ADC1_CH0_RX) 720 #define UDMA_PDMA_CH_MCU_ADC1_CH1_RX (CSL_PDMA_CH_MCU_ADC1_CH1_RX) 724 #define UDMA_PDMA_CH_MCU_MCSPI0_CH0_RX (CSL_PDMA_CH_MCU_MCSPI0_CH0_RX) 725 #define UDMA_PDMA_CH_MCU_MCSPI0_CH1_RX (CSL_PDMA_CH_MCU_MCSPI0_CH1_RX) 726 #define UDMA_PDMA_CH_MCU_MCSPI0_CH2_RX (CSL_PDMA_CH_MCU_MCSPI0_CH2_RX) 727 #define UDMA_PDMA_CH_MCU_MCSPI0_CH3_RX (CSL_PDMA_CH_MCU_MCSPI0_CH3_RX) 728 #define UDMA_PDMA_CH_MCU_MCSPI1_CH0_RX (CSL_PDMA_CH_MCU_MCSPI1_CH0_RX) 729 #define UDMA_PDMA_CH_MCU_MCSPI1_CH1_RX (CSL_PDMA_CH_MCU_MCSPI1_CH1_RX) 730 #define UDMA_PDMA_CH_MCU_MCSPI1_CH2_RX (CSL_PDMA_CH_MCU_MCSPI1_CH2_RX) 731 #define UDMA_PDMA_CH_MCU_MCSPI1_CH3_RX (CSL_PDMA_CH_MCU_MCSPI1_CH3_RX) 732 #define UDMA_PDMA_CH_MCU_MCSPI2_CH0_RX (CSL_PDMA_CH_MCU_MCSPI2_CH0_RX) 733 #define UDMA_PDMA_CH_MCU_MCSPI2_CH1_RX (CSL_PDMA_CH_MCU_MCSPI2_CH1_RX) 734 #define UDMA_PDMA_CH_MCU_MCSPI2_CH2_RX (CSL_PDMA_CH_MCU_MCSPI2_CH2_RX) 735 #define UDMA_PDMA_CH_MCU_MCSPI2_CH3_RX (CSL_PDMA_CH_MCU_MCSPI2_CH3_RX) 739 #define UDMA_PDMA_CH_MCU_MCAN0_CH0_RX (CSL_PDMA_CH_MCU_MCAN0_CH0_RX) 740 #define UDMA_PDMA_CH_MCU_MCAN0_CH1_RX (CSL_PDMA_CH_MCU_MCAN0_CH1_RX) 741 #define UDMA_PDMA_CH_MCU_MCAN0_CH2_RX (CSL_PDMA_CH_MCU_MCAN0_CH2_RX) 742 #define UDMA_PDMA_CH_MCU_MCAN1_CH0_RX (CSL_PDMA_CH_MCU_MCAN1_CH0_RX) 743 #define UDMA_PDMA_CH_MCU_MCAN1_CH1_RX (CSL_PDMA_CH_MCU_MCAN1_CH1_RX) 744 #define UDMA_PDMA_CH_MCU_MCAN1_CH2_RX (CSL_PDMA_CH_MCU_MCAN1_CH2_RX) 748 #define UDMA_PDMA_CH_MCU_UART0_RX (CSL_PDMA_CH_MCU_UART0_CH0_RX) uint32_t Udma_isCacheCoherent(void)
Returns TRUE if the memory is cache coherent.
uint32_t Udma_getCoreId(void)
Returns the core ID.
uint16_t Udma_getCoreSciDevId(void)
Returns the core tisci device ID.