61 #define TISCI_MSG_VALUE_RM_RING_ADDR_LO_VALID (1u << 0u) 65 #define TISCI_MSG_VALUE_RM_RING_ADDR_HI_VALID (1u << 1u) 69 #define TISCI_MSG_VALUE_RM_RING_COUNT_VALID (1u << 2u) 73 #define TISCI_MSG_VALUE_RM_RING_MODE_VALID (1u << 3u) 77 #define TISCI_MSG_VALUE_RM_RING_SIZE_VALID (1u << 4u) 81 #define TISCI_MSG_VALUE_RM_RING_ORDER_ID_VALID (1u << 5u) 85 #define TISCI_MSG_VALUE_RM_RING_VIRTID_VALID (1u << 6u) 90 #define TISCI_MSG_VALUE_RM_RING_ASEL_VALID (1U << 7U) 95 #define TISCI_MSG_VALUE_RM_RING_MODE_RING (0x0u) 99 #define TISCI_MSG_VALUE_RM_RING_MODE_MESSAGE (0x1u) 103 #define TISCI_MSG_VALUE_RM_RING_MODE_CREDENTIALS (0x2u) 107 #define TISCI_MSG_VALUE_RM_RING_MODE_QM (0x3u) 112 #define TISCI_MSG_VALUE_RM_RING_SIZE_4B (0x0u) 116 #define TISCI_MSG_VALUE_RM_RING_SIZE_8B (0x1u) 120 #define TISCI_MSG_VALUE_RM_RING_SIZE_16B (0x2u) 124 #define TISCI_MSG_VALUE_RM_RING_SIZE_32B (0x3u) 128 #define TISCI_MSG_VALUE_RM_RING_SIZE_64B (0x4u) 132 #define TISCI_MSG_VALUE_RM_RING_SIZE_128B (0x5u) 136 #define TISCI_MSG_VALUE_RM_RING_SIZE_256B (0x6u) 141 #define TISCI_MSG_VALUE_RM_MON_SOURCE_VALID (1u << 0U) 145 #define TISCI_MSG_VALUE_RM_MON_MODE_VALID (1u << 1U) 149 #define TISCI_MSG_VALUE_RM_MON_QUEUE_VALID (1u << 2U) 153 #define TISCI_MSG_VALUE_RM_MON_DATA0_VAL_VALID (1u << 3U) 157 #define TISCI_MSG_VALUE_RM_MON_DATA1_VAL_VALID (1u << 4U) 162 #define TISCI_MSG_VALUE_RM_MON_SRC_ELEM_CNT (0U) 166 #define TISCI_MSG_VALUE_RM_MON_SRC_HEAD_PKT_SIZE (1U) 170 #define TISCI_MSG_VALUE_RM_MON_SRC_ACCUM_Q_SIZE (2U) 175 #define TISCI_MSG_VALUE_RM_MON_MODE_DISABLED (0U) 179 #define TISCI_MSG_VALUE_RM_MON_MODE_PUSH_POP (1U) 183 #define TISCI_MSG_VALUE_RM_MON_MODE_THRESHOLD (2U) 187 #define TISCI_MSG_VALUE_RM_MON_MODE_WATERMARK (3U) 191 #define TISCI_MSG_VALUE_RM_MON_MODE_STARVATION (4U) uint16_t queue
Definition: tisci_rm_ra.h:404
uint16_t index
Definition: tisci_rm_ra.h:303
struct tisci_header hdr
Definition: tisci_rm_ra.h:398
uint16_t index
Definition: tisci_rm_ra.h:401
uint32_t data0_val
Definition: tisci_rm_ra.h:405
uint32_t count
Definition: tisci_rm_ra.h:306
uint8_t mode
Definition: tisci_rm_ra.h:403
uint32_t addr_lo
Definition: tisci_rm_ra.h:304
Response to configuring a ring monitor.
Definition: tisci_rm_ra.h:415
uint8_t order_id
Definition: tisci_rm_ra.h:309
uint16_t nav_id
Definition: tisci_rm_ra.h:302
struct tisci_header hdr
Definition: tisci_rm_ra.h:300
uint32_t valid_params
Definition: tisci_rm_ra.h:399
Configures a Navigator Subsystem ring monitor. Configures the real-time registers of a Navigator Subs...
Definition: tisci_rm_ra.h:397
Response to configuring a ring.
Definition: tisci_rm_ra.h:320
uint32_t valid_params
Definition: tisci_rm_ra.h:301
uint16_t virtid
Definition: tisci_rm_ra.h:310
uint32_t data1_val
Definition: tisci_rm_ra.h:406
uint8_t mode
Definition: tisci_rm_ra.h:307
uint8_t asel
Definition: tisci_rm_ra.h:311
uint8_t size
Definition: tisci_rm_ra.h:308
Configures a Navigator Subsystem ring.
Definition: tisci_rm_ra.h:299
struct tisci_header hdr
Definition: tisci_rm_ra.h:416
struct tisci_header hdr
Definition: tisci_rm_ra.h:321
uint8_t source
Definition: tisci_rm_ra.h:402
struct tisci_msg_rm_ring_cfg_req __attribute__((__packed__))
uint32_t addr_hi
Definition: tisci_rm_ra.h:305
uint16_t nav_id
Definition: tisci_rm_ra.h:400