csirx_soc.h

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/*
 *  Copyright (c) Texas Instruments Incorporated 2018-2019
 *  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef CSIRX_SOC_H_
#define CSIRX_SOC_H_

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

/* None */

#ifdef __cplusplus
extern "C" {
#endif

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
#define CSIRX_INSTANCE_ID_0                         ((uint32_t) 0x0U)

#define CSIRX_INSTANCE_ID_1                         ((uint32_t) 0x1U)

#define CSIRX_INSTANCE_ID_MAX                       ((uint32_t) 0x2U)
/* @} */

#define CSIRX_NUM_VIRTUAL_CONTEXT                   (8U)

/* TODO: This should be 'CSIRX_MAX_NUM_OF_STREAMS' when OTF and LPBK are supported */
#define CSIRX_NUM_STREAM                             (1U)

#define CSIRX_NUM_STRMS_CAPT                     ((uint32_t) 2U)

#define CSIRX_NUM_STRMS_OTF                      ((uint32_t) 1U)

#define CSIRX_NUM_STRMS_LPBK                     ((uint32_t) 2U)

#define CSIRX_NUM_CH_CAPT                        ((uint32_t) 32U)

#define CSIRX_NUM_CH_CAPT_MAX         ((uint32_t) (CSIRX_NUM_CH_CAPT *\
                                                        CSIRX_INSTANCE_ID_MAX))

#define CSIRX_NUM_CH_OTF_MAX                   ((uint32_t) 1U)

#define CSIRX_NUM_CH_LPBK_MAX                  ((uint32_t) 1U)

#define CSIRX_NUM_CH_MAX         ((uint32_t) (CSIRX_NUM_CH_CAPT +\
                                              CSIRX_NUM_CH_OTF_MAX +\
                                              CSIRX_NUM_CH_LPBK_MAX))

#define CSIRX_CAPT_DATA_LANES_MAX                  ((uint32_t)4U)
/* @} */

#define CSIRX_LANE_BAND_SPEED_80_TO_100_MBPS              ((uint32_t) 0x00U)

#define CSIRX_LANE_BAND_SPEED_100_TO_120_MBPS             ((uint32_t) 0x01U)

#define CSIRX_LANE_BAND_SPEED_120_TO_160_MBPS             ((uint32_t) 0x02U)

#define CSIRX_LANE_BAND_SPEED_160_TO_200_MBPS             ((uint32_t) 0x03U)

#define CSIRX_LANE_BAND_SPEED_200_TO_240_MBPS             ((uint32_t) 0x04U)

#define CSIRX_LANE_BAND_SPEED_240_TO_280_MBPS             ((uint32_t) 0x05U)

#define CSIRX_LANE_BAND_SPEED_280_TO_320_MBPS             ((uint32_t) 0x06U)

#define CSIRX_LANE_BAND_SPEED_320_TO_360_MBPS             ((uint32_t) 0x07U)

#define CSIRX_LANE_BAND_SPEED_360_TO_400_MBPS             ((uint32_t) 0x08U)

#define CSIRX_LANE_BAND_SPEED_400_TO_480_MBPS             ((uint32_t) 0x09U)

#define CSIRX_LANE_BAND_SPEED_480_TO_560_MBPS             ((uint32_t) 0x0AU)

#define CSIRX_LANE_BAND_SPEED_560_TO_640_MBPS             ((uint32_t) 0x0BU)

#define CSIRX_LANE_BAND_SPEED_640_TO_720_MBPS             ((uint32_t) 0x0CU)

#define CSIRX_LANE_BAND_SPEED_720_TO_800_MBPS             ((uint32_t) 0x0DU)

#define CSIRX_LANE_BAND_SPEED_800_TO_880_MBPS             ((uint32_t) 0x0EU)

#define CSIRX_LANE_BAND_SPEED_880_TO_1040_MBPS            ((uint32_t) 0x0FU)

#define CSIRX_LANE_BAND_SPEED_1040_TO_1200_MBPS           ((uint32_t) 0x10U)

#define CSIRX_LANE_BAND_SPEED_1200_TO_1350_MBPS           ((uint32_t) 0x11U)

#define CSIRX_LANE_BAND_SPEED_1350_TO_1500_MBPS           ((uint32_t) 0x12U)

#define CSIRX_LANE_BAND_SPEED_1500_TO_1750_MBPS           ((uint32_t) 0x13U)

#define CSIRX_LANE_BAND_SPEED_1750_TO_2000_MBPS           ((uint32_t) 0x14U)

#define CSIRX_LANE_BAND_SPEED_2000_TO_2250_MBPS           ((uint32_t) 0x15U)

#define CSIRX_LANE_BAND_SPEED_2250_TO_2500_MBPS           ((uint32_t) 0x16U)

#define CSIRX_LANE_BAND_SPEED_RESERVED                    ((uint32_t) 0x17U)
/* @} */

#if defined (BUILD_MCU2_0) || defined (BUILD_MCU2_1)

#define CSIRX_CORE_INTR_NUM_MOD_0_ERR_INTR                \
                            (CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF0_CSI_ERR_IRQ_0)

#define CSIRX_CORE_INTR_NUM_MOD_0_INFO_INTR               \
                            (CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF0_CSI_IRQ_0)

#define CSIRX_CORE_INTR_NUM_MOD_0_LEVEL_INTR              \
                            (CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF0_CSI_LEVEL_0)

#define CSIRX_CORE_INTR_NUM_MOD_1_ERR_INTR                \
                            (CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF1_CSI_ERR_IRQ_0)

#define CSIRX_CORE_INTR_NUM_MOD_1_INFO_INTR               \
                            (CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF1_CSI_IRQ_0)

#define CSIRX_CORE_INTR_NUM_MOD_1_LEVEL_INTR              \
                            (CSLR_R5FSS0_CORE0_INTR_CSI_RX_IF1_CSI_LEVEL_0)
#endif
#if defined (BUILD_MPU1_0)

#define CSIRX_CORE_INTR_NUM_MOD_0_ERR_INTR                \
                (CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_CSI_RX_IF0_CSI_ERR_IRQ_0)

#define CSIRX_CORE_INTR_NUM_MOD_0_INFO_INTR               \
                (CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_CSI_RX_IF0_CSI_IRQ_0)

#define CSIRX_CORE_INTR_NUM_MOD_0_LEVEL_INTR              \
                (CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_CSI_RX_IF0_CSI_LEVEL_0)

#define CSIRX_CORE_INTR_NUM_MOD_1_ERR_INTR                \
                (CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_CSI_RX_IF1_CSI_ERR_IRQ_0)

#define CSIRX_CORE_INTR_NUM_MOD_1_INFO_INTR               \
                (CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_CSI_RX_IF1_CSI_IRQ_0)

#define CSIRX_CORE_INTR_NUM_MOD_1_LEVEL_INTR              \
                (CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_CSI_RX_IF1_CSI_LEVEL_0)
#endif
/* @} */


#define CSIRX_CORE_PIXEL_OUTPUT_BUS_WIDTH                    (32U)
/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */
typedef struct
{
    uint32_t inst;
    uint32_t psmClkFreqDiv;
    uint32_t leftLaneBandSpeed;
    uint32_t rightLaneBandSpeed;
    uint32_t bandGapTimerVal;
} Csirx_DPhyCfg;

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
static inline void Csirx_initDPhyCfg(Csirx_DPhyCfg *dphyCfg);

void CsirxDrv_dphyrxWrapPsmClockConfig(uint32_t addr, uint32_t value);

void CsirxDrv_dphyrxCorePpiClockConfig(uint32_t addr,
                                       const Csirx_DPhyCfg *dphyCfg);

void CsirxDrv_dphyrxCoreLaneReady(uint32_t addr, uint32_t numLanes);

void CsirxDrv_dphyrxCoreCommonReady(uint32_t addr);

int32_t CsirxDrv_checkDphyrxConfig(const Csirx_DPhyCfg *programmedCfg,
                                   const Csirx_DPhyCfg *newCfg);
/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */
static inline void Csirx_initDPhyCfg(Csirx_DPhyCfg *dphyCfg)
{
    dphyCfg->inst               = CSIRX_INSTANCE_ID_0;
    dphyCfg->psmClkFreqDiv      = 0x53;
    dphyCfg->leftLaneBandSpeed  = CSIRX_LANE_BAND_SPEED_1350_TO_1500_MBPS;
    dphyCfg->rightLaneBandSpeed = CSIRX_LANE_BAND_SPEED_1350_TO_1500_MBPS;
    dphyCfg->bandGapTimerVal     = 0x14;
}

#ifdef __cplusplus
}
#endif

#endif /* #ifndef CSIRX_SOC_H_ */

/* @} */