1. J721E Datasheet

1.1. Introduction

This section provides the performance numbers of device drivers supported in PDK

1.1.1. Setup Details

SOC Details Values
Core R5F
Core Operating Speed 1GHz
DDR Speed 4266 MTs
VPAC Frequency 650 MHz
DMPAC Frequency 520 MHz
Cache status Enabled
Optimization Details Values
Profile Release
Compile Options for R5F -g -ms -DMAKEFILE_BUILD -c -qq -pdsw225 –endian=little -mv7R5 –abi=eabi -eo.oer5f -ea.ser5f –symdebug:dwarf –embed_inline_assembly –float_support=vfpv3d16 –emit_warnings_as_errors
Linker Options for R5F –emit_warnings_as_errors -w -q -u _c_int00 -c -mv7R5 –diag_suppress=10063 -x –zero_init=on
Code Placement DDR
Data Placement DDR

1.1.2. Software Performance Numbers

1.1.2.1. VHWA

VHWA Driver Configuration Measured Throughput (MPix/S)
DOF 2MP (2048x1024), 12b Packed, 6 Levels, SR191x96 158.65
DOF 1MP (1312x736), 12b Packed, 5 Levels, SR170x124 150.93
MSC 1080P, 8b YUV420, 10 Scales output 609.46
NF 720P, 8b YUV420, Bilateral filter 615.54
SDE 2MP (2048x1024), 12b Packed, SR 192, LR Enabled 84.22
SDE 720P, 12b Packed, SR 192, LR Disabled 98.92
LDC 1080P, 8b YUV420, Single region 632.98
VISS 1080P, Raw 12 input, 2 frame Merge, YUV420 12b and 8b output 603.25

1.1.2.2. DSS

Display Type Configuration CPU Load
HDMI 1080P60 RGB888 1.0% (MCU2_0)

1.1.2.3. CSI-Rx

Capture Type Configuration CPU Load
CSI2Rx Inst 0 4CH 1080P30 IMX390 Sensor Raw12 1.2% (MCU2_0)

1.1.2.4. CPSW

1.1.2.4.1. Test Set-up
  • Core – Main domain R5_0 (MCU2_0)
  • Frequency - 1000MHz
1.1.2.4.2. TCP/UDP (IP stack) Performance
Test Measured Throughput (Mbps) CPU Load (%)
TCP TX 85.55 80
TCP RX 374.37 63
1.1.2.4.3. RAW (L2) Performance
Test Measured Throughput (Mbps) CPU Load (%)
RAW TX 870 90
RAW RX 800 90

Note:

  1. Current performance numbers are preliminary as throughput profiling is not done in optimized environment (putting frequently used functions in fast memory, use of pacing using ring monitor, tuning of descriptors etc.)
  2. TCP/IP numbers are measured with TI NDK stack. The optimized handling of packets with NDK stack is work in progress.

1.1.2.5. UDMA

1.1.2.5.1. DMA Parameters
  • Ring Order ID: 0
  • Channel Order ID: 0
  • Channel DMA Priority: 1
  • Channel Bus Priority: 4
  • Channel BUS QOS: 4
  • Channel TX FIFO depth: 128
  • Channel Fetch Word Size: 16
  • Channel Burst Size: 64 bytes for normal channel, 128 bytes for HC and UHC channels
1.1.2.5.2. Test Parameters
  • Type: TR15 Block copy
  • TR: one TR per TRPD in PBR mode
  • TR Memory: Same as buffer memory (DDR, MSMC or OCMC depends on the test performed)
  • Transfer Size: 1 MB read and 1MB write
  • 1MB means 1000x1000 bytes and 1KB means 1000 bytes

Note: Throughput numbers mentioned is the combined memory throughput of both read and write operations

1.1.2.5.3. DRU Blockcopy

DRU channel performance with TR submitted through ring

Test Description Throughput (MCU2) CPU Load (MCU2) Throughput (C66x_1/2) CPU Load (C66x_1/2)
[PDK-3501] 1CH DDR 1MB to DDR 1MB 12185 MB/sec 25% 12228 MB/sec 12%
[PDK-3502] 1CH MSMC 1KB Circular to DDR 1MB 18910 MB/sec 6% 18741 MB/sec 7%
[PDK-3503] 1CH DDR 1MB to MSMC circular 1KB 22501 MB/sec 7% 22405 MB/sec 8%
[PDK-3504] 1CH MSMC 1KB to MSMC circular 1KB (1MB per TR) 29662 MB/sec 5% 29208 MB/sec 8%
[PDK-3505] Multi CH DDR 1MB to DDR 1MB 12606 MB/sec (2CH) 44% 13013 MB/sec (4CH) 89%
[PDK-3506] Multi CH MSMC 1KB to MSMC circular 1KB (1 MB per TR) 33581 MB/sec (2CH) 16% 33581 MB/sec (4CH) 26%
1.1.2.5.5. MCU NAVSS Blockcopy (Normal Channel)

MCU NAVSS normal channel performance with TR submitted through ring

Test Description Throughput (MCU1) CPU Load (MCU1)
[PDK-3490] 1CH DDR 1MB to DDR 1MB 654 MB/sec 1%
[PDK-3491] 1CH MSMC 1KB Circular to DDR 1MB 986 MB/sec 1%
[PDK-3492] 1CH DDR 1MB to MSMC circular 1KB 720 MB/sec 1%
[PDK-3493] 1CH MSMC 1KB to MSMC circular 1KB (1MB per TR) 965 MB/sec 1%
[PDK-3489] 1CH OCMC 1KB to OCMC circular 1KB (1MB per TR) 2481 MB/sec 1%
[PDK-3495] Multi CH DDR 1MB to DDR 1MB 1177 MB/sec (2CH) 2%
[PDK-3497] Multi CH MSMC 1KB to MSMC circular 1KB (1 MB per TR) 1645 MB/sec (2CH) 2%

1.1.2.6. IPC

1.1.2.6.1. Test Set-up

  • Release build binaries are used for measurement

  • Ring Buffer : Uncached DDR

  • Buffer to be sent (RPMSG) – Cached DDR

  • C66x - L2 Cache 128K

  • C7x - L2 Cache 128K

  • Software/Application Used : ipc_multicore_perf_test loaded through SBL. Output is printed to UART.

  • R5F/MPU config : DDR config

    • bufferable - 1
    • cacheable - 1
    • shareable - 0

Capturing Round trip time in us with different data sizes

1.1.2.6.2. Performance - Host Core A72, Bios, 2 GHz
Remote Core 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes 256 Bytes
MCU R5F0 20 20 22 25 32 44 70
Main R5F0 18 19 20 24 29 41 65
C66x1 17 16 17 16 18 20 25
C7x 20 20 20 20 23 24 25
1.1.2.6.3. Performance - Host Core MCU R5F0, 1 GHz
Remote Core 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes 256 Bytes
A72 (bios) 21 21 23 26 32 43 68
Main R5F0 17 18 19 22 28 39 65
C66x1 17 17 19 22 28 40 64
C7x 18 18 20 23 29 40 66
1.1.2.6.4. Performance - Host Core MAIN R5F0, 1 GHz
Remote Core 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes 256 Bytes
A72 (Bios) 17 17 18 21 26 37 59
MCU R5F0 16 15 17 20 25 35 58
Main R5F1 16 16 17 21 26 36 59
C66x1 16 15 17 20 25 36 58
C7x 16 16 17 20 25 36 58
1.1.2.6.5. Performance - Host Core C66X1, 1.35 GHz
Remote Core 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes 256 Bytes
A72 (Bios) 19 18 18 18 18 22 26
MCU R5F0 26 26 28 30 37 52 81
Main R5F0 25 25 27 29 35 48 75
C66x2 23 22 22 21 23 28 35
C7x 30 29 29 28 31 34 37
1.1.2.6.6. Performance - Host Core C7x, 1GHz
Remote Core 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes 256 Bytes
A72 (Bios) 21 21 21 21 24 23 25
Mcu R5F0 32 32 34 37 45 55 82
Main R5F0 28 29 30 34 42 51 75
C66x1 29 28 28 27 20 31 36

1.1.2.7. OSPI

1.1.2.7.1. OSPI Memory Non Cached Test Set-up
  • Platform: J721e EVM.
  • OS Type: Baremetal/Sysbios
  • Core : R5F_0 at 1 GHz, A72_0 at 2 GHz.
  • Software/Application Used: OSPI_Flash_TestApp/OSPI_Flash_Dma_TestApp/OSPI_Baremetal_Flash_TestApp/OSPI_Baremetal_Flash_Dma_TestApp
  • System Configuration: Cache OFF, Read/Write Buffer in DDR. DMA Enabled/Disabled, Interrupts ON.
1.1.2.7.2. OSPI Read/Write Performance (DDR Octal Mode)
OSPI RCLK OS CPU Mode Write Tput (MB/s) Write CPU Load Read Tput (MB/s) Read CPU Load
133 MHz Baremetal R5F_0 DAC 0.209 100% 7.125 100%
DAC DMA 1.501 100% 218 100%
INDAC 1.493 100% 8.25 100%
A72_0 DAC 0.075 100% 5.625 100%
DAC DMA 1.501 100% 208.875 100%
INDAC 1.505 100% 8.25 100%
RTOS R5F_0 DAC 0.209 100% 7.125 100%
DAC DMA 1.501 0% 217.625 19%
INDAC 1.498 8% 8.25 59%
A72_0 DAC 0.075 100% 5.625 100%
DAC DMA 1.501 0% 209 22%
INDAC 1.499 4% 8.25 97%
166 MHz Baremetal R5F_0 DAC 0.238 100% 8 100%
DAC DMA 1.581 100% 197 100%
INDAC 1.577 100% 10.375 100%
A72_0 DAC 0.078 100% 4.875 100%
DAC DMA 1.581 100% 171.75 100%
INDAC 1.586 100% 10.375 100%
RTOS R5F_0 DAC 0.237 100% 8 100%
DAC DMA 1.581 0% 197.375 41%
INDAC 1.583 8% 10.375 68%
A72_0 DAC 0.078 100% 6.25 100%
DAC DMA 1.581 0% 173.375 48%
INDAC 1.584 5% 10.375 100%
1.1.2.7.3. OSPI Memory Cached Test Set-up
  • Platform: J721e EVM.
  • OS Type: Baremetal/Sysbios
  • Core : R5F_0 at 1 GHz, A72_0 at 2 GHz.
  • Software/Application Used: OSPI_Flash_Cache_TestApp/OSPI_Flash_Dma_Cache_TestApp/OSPI_Baremetal_Flash_Cache_TestApp/OSPI_Baremetal_Flash_Dma_Cache_TestApp
  • System Configuration: Cache ON, Read/Write Buffer in DDR. DMA Enabled/Disabled, Interrupts ON.
1.1.2.7.4. OSPI Read/Write Performance (DDR Octal Mode)
OSPI RCLK OS CPU Mode Write Tput (MB/s) Write CPU Load Read Tput (MB/s) Read CPU Load
133 MHz Baremetal R5F_0 DAC 0.299 100% 45 100%
DAC DMA 1.501 100% 218.25 100%
INDAC 1.491 100% 8.25 100%
A72_0 DAC   100%   100%
DAC DMA   100%   100%
INDAC   100%   100%
RTOS R5F_0 DAC 0.301 100% 45.125 100%
DAC DMA 1.501 0% 218.75 18%
INDAC 1.498 8% 8.25 59%
A72_0 DAC 0.074 100% 5.5 100%
DAC DMA 0.898 100% 209 22%
INDAC 1.497 4% 8.25 98%
166 MHz Baremetal R5F_0 DAC 0.336 100% 51.25 100%
DAC DMA 1.581 100% 196.625 100%
INDAC 1.576 100% 10.375 100%
A72_0 DAC   100%   100%
DAC DMA   100%   100%
INDAC   100%   100%
RTOS R5F_0 DAC 0.337 100% 51.625 100%
DAC DMA 1.581 0% 198 41%
INDAC 1.583 8% 10.375 68%
A72_0 DAC 0.077 100% 6.125 100%
DAC DMA 0.978 0% 171.875 48%
INDAC 1.583 5% 10.375 100%

1.1.2.8. MMCSD

1.1.2.8.1. Test Set-up
  • Platform: J721e EVM.
  • OS Type: Sysbios
  • Core : A72_0, 2 GHz.
  • Software/Application Used: MMCSD_<EMMC>_Regression_TestApp (A menu based application which outputs the benchmark numbers on UART)
  • System Configuration: Cache ON, Read/Write Buffer in DDR. ADMA enabled, Interrupts ON.
  • SD Card used: Sandisk 16GB, Class 10. FAT32 formatted with allocation size = 4K (for optimal FAT32 throughput & compatibility with various cards)
  • EMMC: EMMC on J721E EVM. Please refer to the EVM data sheet for details
1.1.2.8.2. SD Card Performance
1.1.2.8.2.1. DS Mode (25 Mhz, 4-bit) Theoretical Max: 12.5 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s) FATFS Write Throughput (MB/s) FATFS Read Throughput (MB/s)
256 9.1059 9.4340 4.1804 7.5307
512 9.8377 10.4257 4.5550 8.0084
1024 10.0432 10.7388 4.9630 8.2052
2048 10.4119 10.9066 5.8666 8.0361
5120 10.0376 10.9829 4.7683 8.3273
1.1.2.8.2.2. HS Mode (50 Mhz, 4-bit) Theoretical Max: 50 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s) FATFS Write Throughput (MB/s) FATFS Read Throughput (MB/s)
256 15.9483 16.4356 4.3909 11.8113
512 18.5548 19.6683 6.2893 12.6380
1024 19.9566 20.8116 6.5560 13.1697
2048 19.9830 21.4463 6.5847 13.4176
5120 20.0178 21.8337 6.2207 13.4776
1.1.2.8.2.3. SDR12 Mode (25 Mhz, 4-bit) Theoretical Max: 12.5 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s) FATFS Write Throughput (MB/s) FATFS Read Throughput (MB/s)
256 9.0146 9.4187 4.2206 7.4148
512 9.7703 10.4165 4.9643 8.0081
1024 10.0714 10.7345 4.7311 8.2015
2048 9.6667 10.8930 5.0503 8.3087
5120 10.0025 11.0095 4.8343 8.3287
1.1.2.8.2.4. SDR25 Mode (50 Mhz, 4-bit) Theoretical Max: 25 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s) FATFS Write Throughput (MB/s) FATFS Read Throughput (MB/s)
256 16.2732 16.4143 5.6652 11.2796
512 18.3847 19.6669 6.3413 12.6358
1024 19.0623 20.8100 6.5959 13.1657
2048 17.4704 21.3765 6.3836 13.4073
5120 19.6133 21.8508 6.0397 12.5147
1.1.2.8.2.5. SDR50 Mode (50 Mhz, 4-bit) Theoretical Max: 50 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s) FATFS Write Throughput (MB/s) FATFS Read Throughput (MB/s)
256 24.6037 26.1130 4.5208 7.6322
512 29.9576 35.3214 4.9401 7.9848
1024 32.6505 39.1811 4.9564 8.1912
2048 30.3629 41.3373 4.9362 8.2954
5120 34.7683 43.0374 4.8785 8.3285
1.1.2.8.2.6. DDR50 Mode (50 Mhz, 4-bit) Theoretical Max: 50 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s) FATFS Write Throughput (MB/s) FATFS Read Throughput (MB/s)
256 23.4774 25.6365 4.2197 7.5511
512 26.2276 34.4773 4.4524 7.9936
1024 34.0707 38.1547 4.9994 8.2083
2048 29.2400 40.1979 5.0277 8.3036
5120 32.5992 41.6822 4.8337 8.3316
1.1.2.8.3. EMMC Performance
1.1.2.8.3.1. DS Mode (25 Mhz, 8-bit) Theoretical Max: 25 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s)
256 15.9600 18.5776
512 18.1068 20.1941
1024 19.4310 21.1389
2048 20.1785 21.6574
5120 20.6573 21.9851
1.1.2.8.3.2. HS-SDR Mode (50 Mhz, 8-bit) Theoretical Max: 50 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s)
256 25.6862 31.8970
512 31.7678 36.9522
1024 36.0882 40.2272
2048 38.7699 42.1508
5120 39.6647 43.3818
1.1.2.8.3.3. HS-DDR Mode (50 Mhz, 8-bit) Theoretical Max: 100 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s)
256 34.8107 47.9176
512 41.8965 60.3240
1024 48.6215 69.5793
2048 53.9672 75.5317
5120 56.1397 79.6654
1.1.2.8.3.4. HS-200 Mode (200 Mhz, 8-bit) Theoretical Max: 200 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s)
256 37.8881 68.9168
512 46.4331 97.8488
1024 50.7672 124.6944
2048 54.6804 145.1625
5120 55.0597 160.8638
1.1.2.8.3.5. HS-400 Mode (200 Mhz, 8-bit) Theoretical Max: 400 MB/s
Size of transfer (KB) RAW Write Throughput (MB/s) RAW Read Throughput (MB/s)
256 36.2206 84.0709
512 47.7269 130.8260
1024 51.6706 184.4708
2048 55.3375 203.5146
5120 56.7088 208.5778

1.1.2.9. CSL-FL based Optimized OSPI Example

1.1.2.9.1. CPU Mode - Test Set-up

  • Platform: J721e EVM.

  • OS Type: Baremetal

  • Core : R5F_0 at 1 GHz

  • Software/Application Used: csl_ospi_flash_app

  • System Configuration:
    • RCLK 133/166 MHz
    • Cache ON,
    • Buffer & Critical Fxn’s in TCMB,
    • DMA Disabled,
    • Interrupts OFF.
  • Theoretical Max Throughput:
    • 133 MHz :- 253.67 MB/s
    • 166 MHz :- 316.62 MB/s
1.1.2.9.2. DAC Mode OSPI Read Performance (Dual Data Rate - Octal Mode)
OSPI RCLK Size of transfer (B) Read Time (ns) Throughput (MB/s)
133 MHz 16 815 19.6
32 1445 22.1
64 2700 23.7
128 5225 24.5
256 10265 24.9
512 20360 25.1
1024 40510 25.3
166 MHz 16 945 16.9
32 2330 13.7
64 4580 14.0
128 9105 14.1
256 18145 14.1
512 36185 14.1
1024 72295 14.2
1.1.2.9.3. DMA Mode - Test Set-up

  • Platform: J721e EVM.

  • OS Type: Baremetal

  • Core : R5F_0 at 1 GHz

  • Software/Application Used: udma_baremetal_ospi_flash_testapp

  • System Configuration:
    • RCLK 133/166 MHz
    • Cache ON,
    • Buffer & Critical Fxn’s in TCMB,
    • DMA Enabled - SW Trigger mode,
    • Interrupts OFF.
  • Theoretical Max Throughput:
    • 133 MHz :- 253.67 MB/s
    • 166 MHz :- 316.62 MB/s
1.1.2.9.4. DAC DMA Mode OSPI Read Performance (Dual Data Rate - Octal Mode)
OSPI RCLK Size of transfer (B) Read Time (ns) Throughput (MB/s)
133 MHz 16 800 20
32 805 39.8
64 970 66
128 1315 97.3
256 1955 130.9
512 3120 164.1
1024 5450 187.9
166 MHz 16 675 23.7
32 805 39.8
64 850 75.3
128 1180 108.5
256 1685 151.9
512 2730 187.5
1024 4670 219.3

1.1.2.10. SBL OSPI Boot Performance App

1.1.2.10.1. Test Set-up
  • Platform: J721e EVM.
  • OS Type: Baremetal
  • Core : R5F_0 at 1 GHz
  • Software/Application Used: sbl_cust_img (with custom flags) and sbl_boot_perf_test appimage
1.1.2.10.2. GP EVM Performance
SBL Boot Time Breakdown Time (ms)
MCU_PORZ_OUT to MCU_RESETSTATz 0.63
ROM : init + SBL load from OSPI 14.00
SBL : Board_init (PINMUX) 2.90
SBL: SPI_init 0.15
SBL : SBL_SciClientInit: ReadSysfwImage 6.08
Load/Start SYSFW 7.83
Board Config 2.00
PM Config 2.00
RM Config 0.78
Security Config 0.65
SBL: SoC Late-Init
SBL : Board_init (PLL) 1.52
SBL: Board_init (CLOCKS) 0.55
SBL: OSPI init 0.05
SBL: Misc (Sciclient_pmSetModule)
SBL: App copy to MCU SRAM & Jump to App 3.90
MCUSW: CAN response 1.00
TOTAL time 44.0