PDK Documentation
csirx_regs.h
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1 /* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c99-2 "C99 - limits" parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits" */
2 /* parasoft-begin-suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure, DRV-3667" */
3 
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34 
35 #ifndef REG_CSIRX_REGS_H_
36 #define REG_CSIRX_REGS_H_
37 
38 
39 
40 typedef struct __attribute__((packed)) CSIRX_Regs_s {
41  volatile uint32_t device_config;
42  volatile uint32_t soft_reset;
43  volatile uint32_t static_cfg;
44  volatile char pad__0[0x4U];
45  volatile uint32_t error_bypass_cfg;
46  volatile char pad__1[0x4U];
47  volatile uint32_t monitor_irqs;
48  volatile uint32_t monitor_irqs_mask_cfg;
49  volatile uint32_t info_irqs;
50  volatile uint32_t info_irqs_mask_cfg;
51  volatile uint32_t error_irqs;
52  volatile uint32_t error_irqs_mask_cfg;
53  volatile char pad__2[0x10U];
54  volatile uint32_t dphy_lane_control;
55  volatile char pad__3[0x4U];
56  volatile uint32_t dphy_status;
57  volatile uint32_t dphy_err_status_irq;
58  volatile uint32_t dphy_err_irq_mask_cfg;
59  volatile char pad__4[0xCU];
60  volatile uint32_t integration_debug;
61  volatile char pad__5[0x10U];
62  volatile uint32_t error_debug;
63  volatile char pad__6[0x8U];
64  volatile uint32_t test_generic;
65  volatile char pad__7[0x7CU];
66  volatile uint32_t stream0_ctrl;
67  volatile uint32_t stream0_status;
68  volatile uint32_t stream0_data_cfg;
69  volatile uint32_t stream0_cfg;
70  volatile uint32_t stream0_monitor_ctrl;
71  volatile uint32_t stream0_monitor_frame;
72  volatile uint32_t stream0_monitor_lb;
73  volatile uint32_t stream0_timer;
74  volatile uint32_t stream0_fcc_cfg;
75  volatile uint32_t stream0_fcc_ctrl;
76  volatile uint32_t stream0_fifo_fill_lvl;
77  volatile char pad__8[0xD4U];
78  volatile uint32_t stream1_ctrl;
79  volatile uint32_t stream1_status;
80  volatile uint32_t stream1_data_cfg;
81  volatile uint32_t stream1_cfg;
82  volatile uint32_t stream1_monitor_ctrl;
83  volatile uint32_t stream1_monitor_frame;
84  volatile uint32_t stream1_monitor_lb;
85  volatile uint32_t stream1_timer;
86  volatile uint32_t stream1_fcc_cfg;
87  volatile uint32_t stream1_fcc_ctrl;
88  volatile uint32_t stream1_fifo_fill_lvl;
89  volatile char pad__9[0xD4U];
90  volatile uint32_t stream2_ctrl;
91  volatile uint32_t stream2_status;
92  volatile uint32_t stream2_data_cfg;
93  volatile uint32_t stream2_cfg;
94  volatile uint32_t stream2_monitor_ctrl;
95  volatile uint32_t stream2_monitor_frame;
96  volatile uint32_t stream2_monitor_lb;
97  volatile uint32_t stream2_timer;
98  volatile uint32_t stream2_fcc_cfg;
99  volatile uint32_t stream2_fcc_ctrl;
100  volatile uint32_t stream2_fifo_fill_lvl;
101  volatile char pad__10[0xD4U];
102  volatile uint32_t stream3_ctrl;
103  volatile uint32_t stream3_status;
104  volatile uint32_t stream3_data_cfg;
105  volatile uint32_t stream3_cfg;
106  volatile uint32_t stream3_monitor_ctrl;
107  volatile uint32_t stream3_monitor_frame;
108  volatile uint32_t stream3_monitor_lb;
109  volatile uint32_t stream3_timer;
110  volatile uint32_t stream3_fcc_cfg;
111  volatile uint32_t stream3_fcc_ctrl;
112  volatile uint32_t stream3_fifo_fill_lvl;
113  volatile char pad__11[0x4D4U];
114  volatile uint32_t asf_int_status;
115  volatile uint32_t asf_int_raw_status;
116  volatile uint32_t asf_int_mask;
117  volatile uint32_t asf_int_test;
118  volatile uint32_t asf_fatal_nonfatal_select;
119  volatile char pad__12[0xCU];
120  volatile uint32_t asf_sram_corr_fault_status;
121  volatile uint32_t asf_sram_uncorr_fault_status;
122  volatile uint32_t asf_sram_fault_stats;
123  volatile char pad__13[0x4U];
124  volatile uint32_t asf_trans_to_ctrl;
125  volatile uint32_t asf_trans_to_fault_mask;
126  volatile uint32_t asf_trans_to_fault_status;
127  volatile char pad__14[0x4U];
128  volatile uint32_t asf_protocol_fault_mask;
129  volatile uint32_t asf_protocol_fault_status;
130  volatile char pad__15[0x6B4U];
131  volatile uint32_t id_prod_ver;
132 } CSIRX_Regs;
133 
134 #endif /* REG_CSIRX_REGS_H_ */
135 
136 /* parasoft-end-suppress MISRA2012-RULE-1_1_a_c99-2 "C99 - limits" */
137 /* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits" */
138 /* parasoft-end-suppress MISRA2012-DIR-4_8 "Consider hiding implementation of structure, DRV-3667" */
139 
__attribute__
This structure contains board specific information.
Definition: board.h:214
CSIRX_Regs
CSIRX_Regs
Definition: csirx_regs.h:132