From f8a54344b1307962e56c95f62fb2e766a1e50fb9 Mon Sep 17 00:00:00 2001 From: Misael Lopez Cruz Date: Wed, 20 Jul 2022 19:23:36 -0500 Subject: [PATCH] utils: j784s4: Workaround: Skip rate configuration of CPSW RGMII clocks Temporary workaround to skip setting RGMII clocks (5/50/250MHz) as parent PLL will not be able to provide the require clock. RGMII clocks are anyways not needed in J784S4 CPSW9G as all ports are SGMII, there is no RGMII port support. Signed-off-by: Misael Lopez Cruz --- examples/utils/enet_apputils_k3.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/examples/utils/enet_apputils_k3.c b/examples/utils/enet_apputils_k3.c index 63830669..af521edf 100644 --- a/examples/utils/enet_apputils_k3.c +++ b/examples/utils/enet_apputils_k3.c @@ -478,6 +478,7 @@ void EnetAppUtils_enableClocks(Enet_Type enetType, uint32_t instId) uint32_t rgmii250MHzClkId; uint32_t rgmii50MHzClkId; uint32_t rgmii5MHzClkId; + bool isRgmiiSupported = true; if ((enetType == ENET_CPSW_2G) && (instId == 0U)) { @@ -537,6 +538,7 @@ void EnetAppUtils_enableClocks(Enet_Type enetType, uint32_t instId) rgmii50MHzClkId = TISCI_DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_50_CLK; rgmii5MHzClkId = TISCI_DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_5_CLK; clkSelMux = ENET_CPSW0_CPTS_CLKSEL_MAIN_SYSCLK0; + isRgmiiSupported = false; #else EnetAppUtils_assert(false); #endif @@ -596,9 +598,13 @@ void EnetAppUtils_enableClocks(Enet_Type enetType, uint32_t instId) EnetAppUtils_assert(cppiClkFreqHz != 0U); EnetAppUtils_clkRateSet(moduleId, cppiClkId, cppiClkFreqHz); - EnetAppUtils_clkRateSet(moduleId, rgmii250MHzClkId, CPSW_SOC_RGMII_MHZ_250_CLK_VAL); - EnetAppUtils_clkRateSet(moduleId, rgmii50MHzClkId, CPSW_SOC_RGMII_MHZ_50_CLK_VAL); - EnetAppUtils_clkRateSet(moduleId, rgmii5MHzClkId, CPSW_SOC_RGMII_MHZ_5_CLK_VAL); + + if (isRgmiiSupported) + { + EnetAppUtils_clkRateSet(moduleId, rgmii250MHzClkId, CPSW_SOC_RGMII_MHZ_250_CLK_VAL); + EnetAppUtils_clkRateSet(moduleId, rgmii50MHzClkId, CPSW_SOC_RGMII_MHZ_50_CLK_VAL); + EnetAppUtils_clkRateSet(moduleId, rgmii5MHzClkId, CPSW_SOC_RGMII_MHZ_5_CLK_VAL); + } EnetAppUtils_selectCptsClock(enetType, instId, clkSelMux); } @@ -614,6 +620,7 @@ void EnetAppUtils_disableClocks(Enet_Type enetType, uint32_t instId) uint32_t rgmii250MHzClkId; uint32_t rgmii50MHzClkId; uint32_t rgmii5MHzClkId; + bool isRgmiiSupported = true; if ((enetType == ENET_CPSW_2G) && (instId == 0U)) { @@ -668,6 +675,7 @@ void EnetAppUtils_disableClocks(Enet_Type enetType, uint32_t instId) rgmii250MHzClkId = TISCI_DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_250_CLK; rgmii50MHzClkId = TISCI_DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_50_CLK; rgmii5MHzClkId = TISCI_DEV_CPSW_9XUSS_J7AM0_RGMII_MHZ_5_CLK; + isRgmiiSupported = false; #else EnetAppUtils_assert(false); #endif @@ -725,9 +733,12 @@ void EnetAppUtils_disableClocks(Enet_Type enetType, uint32_t instId) { /* set clock set to auto so when module is disabled, clocks shuts off */ EnetAppUtils_clkRateSetState(moduleId, cppiClkId, 0, TISCI_MSG_VALUE_CLOCK_SW_STATE_AUTO); - EnetAppUtils_clkRateSetState(moduleId, rgmii250MHzClkId, 0, TISCI_MSG_VALUE_CLOCK_SW_STATE_AUTO); - EnetAppUtils_clkRateSetState(moduleId, rgmii50MHzClkId, 0, TISCI_MSG_VALUE_CLOCK_SW_STATE_AUTO); - EnetAppUtils_clkRateSetState(moduleId, rgmii5MHzClkId, 0, TISCI_MSG_VALUE_CLOCK_SW_STATE_AUTO); + if (isRgmiiSupported) + { + EnetAppUtils_clkRateSetState(moduleId, rgmii250MHzClkId, 0, TISCI_MSG_VALUE_CLOCK_SW_STATE_AUTO); + EnetAppUtils_clkRateSetState(moduleId, rgmii50MHzClkId, 0, TISCI_MSG_VALUE_CLOCK_SW_STATE_AUTO); + EnetAppUtils_clkRateSetState(moduleId, rgmii5MHzClkId, 0, TISCI_MSG_VALUE_CLOCK_SW_STATE_AUTO); + } } /* Set module set to HW AUTO */ -- 2.17.1