J722S MCU+ SDK  10.00.00
PMU

Performance Monitoring Unit (PMU) consists of three event counting registers, one cycle counting register and 12 CP15 registers for controlling and interrogating the counters.

The performance monitoring registers are always accessible in Privileged mode. Control registers can be used to enable or disable each of the event counters individually, and read and reset the overflow flag for each counter. All three event counters are read and written through the same CP15 register. The counters can be enabled to assert an interrupt request when the processor is in Debug halt state. PMU only counts events when non-invasive debug is enabled, that is, when either DBGEN or NIDEN inputs are asserted. The Cycle Count (CCNT) Register is always enabled regardless of whether non-invasive debug is enabled, unless the DP bit of the PMNC register is set.

SysConfig Features

  • None

Features NOT Supported

  • None

Important Usage Guidelines

  • None

Example Usage

The following shows an example of SDL PMU API.

Include the below file to access the APIs

Configure the PMU

SDL_R5PMU_cfg(cycleCntDiv, exportEvents, userEnable);
retValue= SDL_R5PMU_verifyCfg(cycleCntDiv,exportEvents);

Configure PMU Counters

/* I-Cache */
/* D-Cache */
/* Branch */
SDL_R5PMU_resetCycleCnt (); /* Set PMCR C-bit */
SDL_R5PMU_enableCntr (PMU_CNTR_NUM_BRANCH, 1);
SDL_R5PMU_enableCntr (PMU_CNTR_NUM_ICACHE_MISS, 1);
SDL_R5PMU_enableCntr (PMU_CNTR_NUM_DCAHCE_MISS, 1);
SDL_R5PMU_enableCntrOverflowIntr (PMU_CNTR_NUM_BRANCH, 1U);
SDL_R5PMU_enableCntrOverflowIntr (PMU_CNTR_NUM_BRANCH, 0U);

Get the number of PMU counters supported

/* Report number of counters implemented */
numCntrs = SDL_R5PMU_getNumCntrs();

Get the number of branch, icache misses and dcache misses

/* Report number of branch, icache miss and dcache miss */
dCacheMissCnt = sdl_pmu_test_get_dCache_miss();
iCacheMissCnt = sdl_pmu_test_get_iCache_miss();
branchCnt = sdl_pmu_test_get_branch();
cycleCnt = sdl_pmu_test_get_cycle();

Reconfigure PMU with new values

SDL_R5PMU_cfg(cycleCntDiv, exportEvents, userEnable);

Check if static registers values are as expected

Set all PMU counters to new values

/* Set and Read the Counter */
SDL_R5PMU_setResetCntr(PMU_CNTR_NUM_ICACHE_MISS, 1U );
SDL_R5PMU_setResetCntr(PMU_CNTR_NUM_DCAHCE_MISS, 1U );
SDL_R5PMU_setResetCntr(PMU_CNTR_NUM_BRANCH, 1U );
dCacheMissCnt = sdl_pmu_test_get_dCache_miss();
iCacheMissCnt = sdl_pmu_test_get_iCache_miss();
branchCnt = sdl_pmu_test_get_branch();
cycleCnt = sdl_pmu_test_get_cycle();

API

R5 PMU API

SDL_R5PMU_setResetCntr
void SDL_R5PMU_setResetCntr(uint32_t cntrNum, uint32_t cntrVal)
Set a PMU counter.
SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_MISS
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_MISS
Definition: sdl_arm_r5_pmu.h:98
SDL_R5PMU_getNumCntrs
uint32_t SDL_R5PMU_getNumCntrs(void)
Get the number of PMU counters supported.
SDL_R5PMU_resetCycleCnt
void SDL_R5PMU_resetCycleCnt(void)
Reset the cycle counter to zero.
SDL_R5PMU_enableCntrOverflowIntr
void SDL_R5PMU_enableCntrOverflowIntr(uint32_t cntrNum, uint32_t enable)
Enable/disable overflow interrupt generation for a PMU counter.
SDL_R5PMU_verifyCfg
int32_t SDL_R5PMU_verifyCfg(uint32_t cycleCntDiv, uint32_t exportEvents)
Configure the Performance Management Unit (PMU)
SDL_R5PMU_cfg
void SDL_R5PMU_cfg(uint32_t cycleCntDiv, uint32_t exportEvents, uint32_t userEnable)
Configure the Performance Management Unit (PMU)
SDL_R5PMU_cfgCntr
void SDL_R5PMU_cfgCntr(uint32_t cntrNum, SDL_R5PmuEventType eventType)
Configure a PMU counter.
SDL_ARM_R5_PMU_EVENT_TYPE_CYCLE_CNT
@ SDL_ARM_R5_PMU_EVENT_TYPE_CYCLE_CNT
Definition: sdl_arm_r5_pmu.h:163
SDL_ARM_R5_PMU_EVENT_TYPE_B_IMMEDIATE
@ SDL_ARM_R5_PMU_EVENT_TYPE_B_IMMEDIATE
Definition: sdl_arm_r5_pmu.h:109
SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_MISS
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_MISS
Definition: sdl_arm_r5_pmu.h:99
SDL_R5PMU_enableCntr
void SDL_R5PMU_enableCntr(uint32_t cntrNum, uint32_t enable)
Enable/disable a PMU counter.
sdl_arm_r5_pmu.h
This file contains the prototypes of the APIs present in the device abstraction layer file of POK....
SDL_R5PMU_enableAllCntrs
void SDL_R5PMU_enableAllCntrs(uint32_t enable)
Enable/disable all PMU counters.
SDL_ARM_R5_PMU_CYCLE_COUNTER_NUM
#define SDL_ARM_R5_PMU_CYCLE_COUNTER_NUM
Definition: sdl_arm_r5_pmu.h:199
SDL_R5PMU_resetCntrs
void SDL_R5PMU_resetCntrs(void)
Reset all counters to zero.
SDL_R5PMU_readStaticRegisters
void SDL_R5PMU_readStaticRegisters(SDL_PMU_staticRegs *pStaticRegs)
PMU API to Read the Static Registers. This function reads the values of the static registers such as ...