Performance Monitoring Unit (PMU) consists of three event counting registers, one cycle counting register and 12 CP15 registers for controlling and interrogating the counters.
The performance monitoring registers are always accessible in Privileged mode. Control registers can be used to enable or disable each of the event counters individually, and read and reset the overflow flag for each counter. All three event counters are read and written through the same CP15 register. The counters can be enabled to assert an interrupt request when the processor is in Debug halt state. PMU only counts events when non-invasive debug is enabled, that is, when either DBGEN or NIDEN inputs are asserted. The Cycle Count (CCNT) Register is always enabled regardless of whether non-invasive debug is enabled, unless the DP bit of the PMNC register is set.
The following shows an example of SDL PMU API.
Include the below file to access the APIs
Configure the PMU
Configure PMU Counters
Get the number of PMU counters supported
Get the number of branch, icache misses and dcache misses
Reconfigure PMU with new values
Check if static registers values are as expected
Set all PMU counters to new values