J722S MCU+ SDK  09.02.00
sciclient_fmwMsgParams.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2023 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, SCICLIENT_PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
33 
41 #ifndef SCICLIENT_FMWMSGPARAMS_H_
42 #define SCICLIENT_FMWMSGPARAMS_H_
43 
44 /* ========================================================================== */
45 /* Include Files */
46 /* ========================================================================== */
47 
48 #include <stdint.h>
49 
50 #ifdef __cplusplus
51 extern "C" {
52 #endif
53 
54 /* ========================================================================== */
55 /* Macros & Typedefs */
56 /* ========================================================================== */
57 
59 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU)
60 
67 /* ABI Major revision - Major revision changes
68 * indicate backward compatibility breakage */
69 #define SCICLIENT_FIRMWARE_ABI_MAJOR (3U)
70 /* ABI Minor revision - Minor revision changes
71 * indicate backward compatibility is maintained,
72 * however, new messages OR extensions to existing
73 * messages might have been adde */
74 #define SCICLIENT_FIRMWARE_ABI_MINOR (1U)
75 
84 #define SCICLIENT_CONTEXT_WKUP_R5_SEC_0 (0U)
85 
86 #define SCICLIENT_CONTEXT_WKUP_R5_NONSEC_0 (1U)
87 
88 #define SCICLIENT_CONTEXT_MAIN_R5_SEC_0 (2U)
89 
90 #define SCICLIENT_CONTEXT_MAIN_R5_NONSEC_0 (3U)
91 
92 #define SCICLIENT_CONTEXT_A53_SEC_0 (4U)
93 
94 #define SCICLIENT_CONTEXT_A53_SEC_1 (5U)
95 
96 #define SCICLIENT_CONTEXT_A53_NONSEC_0 (6U)
97 
98 #define SCICLIENT_CONTEXT_A53_NONSEC_1 (7U)
99 
100 #define SCICLIENT_CONTEXT_A53_NONSEC_2 (8U)
101 
102 #define SCICLIENT_CONTEXT_MCU_R5_0_NONSEC_0 (9U)
103 
104 #define SCICLIENT_CONTEXT_C7X_NONSEC_0 (10U)
105 
106 #define SCICLIENT_CONTEXT_C7X_NONSEC_1 (11U)
107 
108 #define SCICLIENT_CONTEXT_GPU_NONSEC_0 (12U)
109 
110 #define SCICLIENT_CONTEXT_GPU_NONSEC_1 (13U)
111 
113 #define SCICLIENT_CONTEXT_MAX_NUM (14U)
114 
125 #define SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)
126 
130 #define SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)
131 
135 #define SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)
136 
140 #define SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)
141 
145 #define SCICLIENT_PROC_ID_C7X256V0_C7XV_CORE_0 (0x30U)
146 
150 #define SCICLIENT_PROC_ID_C7X256V1_C7XV_CORE_0 (0x31U)
151 
155 #define SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)
156 
160 #define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0 (0x03U)
161 
165 #define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x04U)
166 
170 #define SCICLIENT_PROC_ID_WKUP_R5FSS0_CORE0 (0x01U)
171 
175 #define SCICLIENT_SOC_NUM_PROCESSORS (0x0AU)
176 
180 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)
181 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)
182 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)
183 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)
184 
189 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)
190 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)
191 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)
192 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)
193 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)
194 
217 #define TISCI_ISC_CC_ID (160U)
218 
219 
226 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U)
227 #define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START (4096U)
228 #define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)
229 #define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START (5120U)
230 #define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)
231 #define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U)
232 #define TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START (6656U)
233 #define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (8192U)
234 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)
235 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)
236 #define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (9728U)
237 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)
238 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)
239 #define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (11264U)
240 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)
241 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)
242 #define TISCI_BCDMA1_TX_EOES_IRQ_SRC_IDX_START (1536U)
243 #define TISCI_BCDMA1_TX_DC_OES_IRQ_SRC_IDX_START (2048U)
244 #define TISCI_BCDMA1_TX_RC_OES_IRQ_SRC_IDX_START (2560U)
245 #define TISCI_BCDMA1_RX_EOES_IRQ_SRC_IDX_START (3072U)
246 #define TISCI_BCDMA1_RX_DC_OES_IRQ_SRC_IDX_START (3584U)
247 #define TISCI_BCDMA1_RX_RC_OES_IRQ_SRC_IDX_START (4096U)
248 
251 #define SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U)
252 #define SCICLIENT_C7X_SECURE_INTERRUPT_NUM (10U)
253 #define SCICLIENT_C7X_0_CLEC_EVENT_IN (CSLR_C7X256V0_CLEC_SOC_EVENTS_IN_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_84)
254 #define SCICLIENT_C7X_1_CLEC_EVENT_IN (CSLR_C7X256V1_CLEC_SOC_EVENTS_IN_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_100)
255 
262 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0)
263 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0)
264 
272 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID \
273  (SCICLIENT_PROC_ID_WKUP_R5FSS0_CORE0)
274 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID \
275  (SCICLIENT_PROC_ID_WKUP_R5FSS0_CORE0)
276 
279 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1
280 
281 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFF
282 
283 /* ========================================================================== */
284 /* Structure Declarations */
285 /* ========================================================================== */
286 
287 /* None */
288 
289 #ifdef __cplusplus
290 }
291 #endif
292 
293 #endif /* #ifndef SCICLIENT_FMWMSGPARAMS_H_ */
tisci_clocks.h
tisci_devices.h