J722S MCU+ SDK  09.02.00
sdl_arm_r5_pmu.h File Reference

Introduction

This file contains the prototypes of the APIs present in the device abstraction layer file of POK. This also contains some related macros.

Go to the source code of this file.

Data Structures

struct  SDL_PMU_staticRegs
 PMU Static Registers structure. More...
 

Macros

#define SDL_ARM_R5_PMU_CYCLE_COUNTER_NUM   (31U)
 
#define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_MASK   (0x000000FFU)
 
#define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_SHIFT   (0x00000000U)
 
#define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_RESETVAL   (0x00000000U)
 
#define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_MAX   (0x000000FFU)
 

Enumerations

enum  SDL_R5PmuEventType {
  SDL_ARM_R5_PMU_EVENT_TYPE_SWINC = 0, SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_MISS = 0x01U, SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_MISS = 0x03U, SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_ACCESS = 0x04U,
  SDL_ARM_R5_PMU_EVENT_TYPE_D_RD = 0x06U, SDL_ARM_R5_PMU_EVENT_TYPE_D_WR = 0x07U, SDL_ARM_R5_PMU_EVENT_TYPE_I_X = 0x08U, SDL_ARM_R5_PMU_EVENT_TYPE_PI_X = 0x5EU,
  SDL_ARM_R5_PMU_EVENT_TYPE_EXCEPTION = 0x09U, SDL_ARM_R5_PMU_EVENT_TYPE_EXCEPTION_RET = 0x0AU, SDL_ARM_R5_PMU_EVENT_TYPE_CID_CHANGE = 0x0BU, SDL_ARM_R5_PMU_EVENT_TYPE_SW_PC = 0x0CU,
  SDL_ARM_R5_PMU_EVENT_TYPE_B_IMMEDIATE = 0x0DU, SDL_ARM_R5_PMU_EVENT_TYPE_PROC_RET = 0x0EU, SDL_ARM_R5_PMU_EVENT_TYPE_UNALIGNED_ACCESS = 0x0FU, SDL_ARM_R5_PMU_EVENT_TYPE_BRANCH_TAKEN = 0x10U,
  SDL_ARM_R5_PMU_EVENT_TYPE_BRANCH_PRED = 0x12U, SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_STALL = 0x40U, SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_STALL = 0x41U, SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_WB = 0x42U,
  SDL_ARM_R5_PMU_EVENT_TYPE_MEM_REQ = 0x43U, SDL_ARM_R5_PMU_EVENT_TYPE_LSU_BUSY_STALL = 0x44U, SDL_ARM_R5_PMU_EVENT_TYPE_SB_DRAIN = 0x45U, SDL_ARM_R5_PMU_EVENT_TYPE_FIQ_DISABLED_CYCLES = 0x46U,
  SDL_ARM_R5_PMU_EVENT_TYPE_IRQ_DISABLED_CYCLES = 0x47U, SDL_ARM_R5_PMU_EVENT_TYPE_ETMEXTOUTM0 = 0x48U, SDL_ARM_R5_PMU_EVENT_TYPE_ETMEXTOUTM1 = 0x49U, SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_TAG_CECC = 0x4AU,
  SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_DATA_CECC = 0x4BU, SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_TAG_CECC = 0x4CU, SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_DATA_CECC = 0x4DU, SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_PF = 0x4EU,
  SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_LS = 0x4FU, SDL_ARM_R5_PMU_EVENT_TYPE_SB_MERGE = 0x50U, SDL_ARM_R5_PMU_EVENT_TYPE_LSU_SB_STALL = 0x51U, SDL_ARM_R5_PMU_EVENT_TYPE_LSU_QF_STALL = 0x52U,
  SDL_ARM_R5_PMU_EVENT_TYPE_INT_DIV = 0x53U, SDL_ARM_R5_PMU_EVENT_TYPE_INT_DIV_STALL = 0x54U, SDL_ARM_R5_PMU_EVENT_TYPE_PLD_LINEFILL = 0x55U, SDL_ARM_R5_PMU_EVENT_TYPE_PLD_NO_LINEFILL = 0x56U,
  SDL_ARM_R5_PMU_EVENT_TYPE_NONCACHEABLE_ACCESS = 0x57U, SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_ACCESS = 0x58U, SDL_ARM_R5_PMU_EVENT_TYPE_SB_ATTR = 0x59U, SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_A = 0x5AU,
  SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_B = 0x5BU, SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_OTHER = 0x5CU, SDL_ARM_R5_PMU_EVENT_TYPE_DOUBLE_FP = 0x5DU, SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_DATA_FECC = 0x60U,
  SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_TAG_FECC = 0x61U, SDL_ARM_R5_PMU_EVENT_TYPE_LIVELOCK = 0x62U, SDL_ARM_R5_PMU_EVENT_TYPE_ATCM_MB_ECC = 0x64U, SDL_ARM_R5_PMU_EVENT_TYPE_B0TCM_MB_ECC = 0x65U,
  SDL_ARM_R5_PMU_EVENT_TYPE_B1TCM_MB_ECC = 0x66U, SDL_ARM_R5_PMU_EVENT_TYPE_ATCM_SB_ECC = 0x67U, SDL_ARM_R5_PMU_EVENT_TYPE_B0TCM_SB_ECC = 0x68U, SDL_ARM_R5_PMU_EVENT_TYPE_B1TCM_SB_ECC = 0x69U,
  SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_LS = 0x6AU, SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_PF = 0x6BU, SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_AXI = 0x6CU, SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_AXI = 0x6DU,
  SDL_ARM_R5_PMU_EVENT_TYPE_CORRECTABLE_EVENTS = 0x6EU, SDL_ARM_R5_PMU_EVENT_TYPE_FATAL_EVENTS = 0x6FU, SDL_ARM_R5_PMU_EVENT_TYPE_CORRECTABLE_BUS_FAULTS = 0x70U, SDL_ARM_R5_PMU_EVENT_TYPE_FATAL_BUS_FAULTS = 0x71U,
  SDL_ARM_R5_PMU_EVENT_TYPE_ACP_DCACHE_ACCESS = 0x72U, SDL_ARM_R5_PMU_EVENT_TYPE_ACP_DCACHE_INVALIDATE = 0x73U, SDL_ARM_R5_PMU_EVENT_TYPE_CYCLE_CNT = 0xFFU
}
 This enumerator defines PMU event types. More...
 

Functions

void SDL_R5PMU_cfg (uint32_t cycleCntDiv, uint32_t exportEvents, uint32_t userEnable)
 Configure the Performance Management Unit (PMU) More...
 
int32_t SDL_R5PMU_verifyCfg (uint32_t cycleCntDiv, uint32_t exportEvents)
 Configure the Performance Management Unit (PMU) More...
 
void SDL_R5PMU_enableAllCntrs (uint32_t enable)
 Enable/disable all PMU counters. More...
 
uint32_t SDL_R5PMU_getNumCntrs (void)
 Get the number of PMU counters supported. More...
 
void SDL_R5PMU_cfgCntr (uint32_t cntrNum, SDL_R5PmuEventType eventType)
 Configure a PMU counter. More...
 
void SDL_R5PMU_enableCntrOverflowIntr (uint32_t cntrNum, uint32_t enable)
 Enable/disable overflow interrupt generation for a PMU counter. More...
 
void SDL_R5PMU_enableCntr (uint32_t cntrNum, uint32_t enable)
 Enable/disable a PMU counter. More...
 
uint32_t SDL_R5PMU_readCntr (uint32_t cntrNum)
 Read a PMU counter. More...
 
void SDL_R5PMU_setResetCntr (uint32_t cntrNum, uint32_t cntrVal)
 Set a PMU counter. More...
 
uint32_t SDL_R5PMU_readCntrOverflowStatus (void)
 Read the overflow status for all of the counters. More...
 
void SDL_R5PMU_clearCntrOverflowStatus (uint32_t cntrMask)
 Clear the overflow flag for the specified counter(s) More...
 
void SDL_R5PMU_resetCycleCnt (void)
 Reset the cycle counter to zero. More...
 
void SDL_R5PMU_resetCntrs (void)
 Reset all counters to zero. More...
 
void SDL_R5PMU_readStaticRegisters (SDL_PMU_staticRegs *pStaticRegs)
 PMU API to Read the Static Registers. This function reads the values of the static registers such as cycleCntDiv, exportEvents and userEnable status. More...