Advance Signal Configuration for the LCD.
Data Fields | |
uint32_t | vpId |
uint32_t | hVAlign |
uint32_t | hVClkControl |
uint32_t | hVClkRiseFall |
uint32_t | acBI |
uint32_t | acB |
uint32_t | vSyncGated |
uint32_t | hSyncGated |
uint32_t | pixelClockGated |
uint32_t | pixelDataGated |
uint32_t | pixelGated |
uint32_t app_dctrl_adv_vp_params_t::vpId |
Video port Id. See App_DssVpId for values
uint32_t app_dctrl_adv_vp_params_t::hVAlign |
Defines the alignment between HSYNC and VSYNC assertion. For valid values see App_DctrlSyncAlign
uint32_t app_dctrl_adv_vp_params_t::hVClkControl |
HSYNC/VSYNC pixel clock control on/off. For valid values see App_DctrlSyncPclkControl
uint32_t app_dctrl_adv_vp_params_t::hVClkRiseFall |
Program HSYNC/VSYNC rise or fall For valid values see App_DctrlEdgePolarity
uint32_t app_dctrl_adv_vp_params_t::acBI |
AC bias pin transitions per interrupt. Value (from 0 to 15) used to specify the number of AC bias pin transitions
uint32_t app_dctrl_adv_vp_params_t::acB |
AC bias pin frequency RW 0x00 Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge buildup within the display
uint32_t app_dctrl_adv_vp_params_t::vSyncGated |
VSYNC gated enabled UFALSE: VSYNC gated disabled UTRUE: VSYNC gated enabled
uint32_t app_dctrl_adv_vp_params_t::hSyncGated |
HSYNC gated enabled UFALSE: HSYNC gated disabled UTRUE: HSYNC gated enabled
uint32_t app_dctrl_adv_vp_params_t::pixelClockGated |
Pixel clock gated enabled UFALSE: Pixel clock gated disabled UTRUE: Pixel clock gated enabled
uint32_t app_dctrl_adv_vp_params_t::pixelDataGated |
Pixel data gated enabled UFALSE: Pixel data gated disabled UTRUE: Pixel data gated enabled
uint32_t app_dctrl_adv_vp_params_t::pixelGated |
Pixel gated enable (only for TFT) UFALSE: Pixel clock always toggles (only in TFT mode) UTRUE: Pixel clock toggles only when there is valid data to display (only in TFT mode)