J722S MCU+ SDK  09.02.00
udma_soc.h
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1 /*
2  * Copyright (C) 2023 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
39 #ifndef UDMA_SOC_H_
40 #define UDMA_SOC_H_
41 
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
45 
46 /* None */
47 
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51 
52 /* ========================================================================== */
53 /* Macros & Typedefs */
54 /* ========================================================================== */
55 
65 #define UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2)
66 
67 #define UDMA_INST_ID_PKTDMA_0 (UDMA_INST_ID_3)
68 
69 #define UDMA_INST_ID_BCDMA_1 (UDMA_INST_ID_4)
70 #if defined(BUILD_C75X)
71 
72 #define UDMA_INST_ID_C7X_DRU_0 (UDMA_INST_ID_5)
73 
74 #define UDMA_INST_ID_C7X_DRU_1 (UDMA_INST_ID_6)
75 
76 #define UDMA_INST_ID_C7X_DRU_START (UDMA_INST_ID_5)
77 
78 #define UDMA_INST_ID_C7X_DRU_MAX (UDMA_INST_ID_6)
79 
80 #define UDMA_NUM_INST_ID_C7X_DRU (UDMA_INST_ID_C7X_DRU_MAX - UDMA_INST_ID_C7X_DRU_START + 1)
81 #endif
82 
83 #define UDMA_INST_ID_START (UDMA_INST_ID_2)
84 
85 #define UDMA_INST_ID_MAX (UDMA_INST_ID_4)
86 
87 #define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U)
88 
99 #define UDMA_SOC_CFG_LCDMA_PRESENT (1U)
100 
102 #define UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U)
103 
104 #define UDMA_SOC_CFG_UDMAP_PRESENT (0U)
105 
107 #define UDMA_SOC_CFG_PROXY_PRESENT (0U)
108 
110 #define UDMA_SOC_CFG_CLEC_PRESENT (0U)
111 
113 #define UDMA_SOC_CFG_RA_NORMAL_PRESENT (0U)
114 
116 #define UDMA_SOC_CFG_RING_MON_PRESENT (0U)
117 
118 #if defined(BUILD_C75X)
119 /* Flag to indicate DRU local to C7X cores is present or not in the SoC */
120 #define UDMA_LOCAL_C7X_DRU_PRESENT (1U)
121 #endif
122 
124 #define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U)
125 
137 #define UDMA_TX_UHC_CHANS_FDEPTH (0U)
138 
139 #define UDMA_TX_HC_CHANS_FDEPTH (0U)
140 
141 #define UDMA_TX_CHANS_FDEPTH (192U)
142 
153 #define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR ((uint32_t) 0U)
154 
155 #define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0 ((uint32_t) 1U)
156 
157 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC ((uint32_t) 14U)
158 
159 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC ((uint32_t) 15U)
160 
163 #define UDMA_NUM_MAPPED_TX_GROUP (4U)
164 
172 #define UDMA_MAPPED_TX_GROUP_CPSW (UDMA_MAPPED_GROUP0)
173 #define UDMA_MAPPED_TX_GROUP_SAUL (UDMA_MAPPED_GROUP1)
174 #define UDMA_MAPPED_TX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP2)
175 #define UDMA_MAPPED_TX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP3)
176 
179 #define UDMA_NUM_MAPPED_RX_GROUP (4U)
180 
188 #define UDMA_MAPPED_RX_GROUP_CPSW (UDMA_MAPPED_GROUP4)
189 #define UDMA_MAPPED_RX_GROUP_SAUL (UDMA_MAPPED_GROUP5)
190 #define UDMA_MAPPED_RX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP6)
191 #define UDMA_MAPPED_RX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP7)
192 
202 /*
203  * Locally used core ID to define default RM configuration.
204  * Not to be used by caller
205  */
206 #define UDMA_CORE_ID_MPU1_0 (0U)
207 #define UDMA_CORE_ID_MCU2_0 (1U)
208 #define UDMA_CORE_ID_MCU2_1 (2U)
209 #define UDMA_CORE_ID_MCU1_0 (3U)
210 #define UDMA_CORE_ID_MCU1_1 (4U)
211 #define UDMA_CORE_ID_C7X_1 (5U)
212 #define UDMA_CORE_ID_C7X_2 (6U)
213 /* Total number of cores */
214 #define UDMA_NUM_C7X_CORE (2U)
215 #define UDMA_NUM_CORE (5U)
216 
227 #define UDMA_RM_RES_ID_BC_UHC (0U)
228 
229 #define UDMA_RM_RES_ID_BC_HC (1U)
230 
231 #define UDMA_RM_RES_ID_BC (2U)
232 
233 #define UDMA_RM_RES_ID_TX_UHC (3U)
234 
235 #define UDMA_RM_RES_ID_TX_HC (4U)
236 
237 #define UDMA_RM_RES_ID_TX (5U)
238 
239 #define UDMA_RM_RES_ID_RX_UHC (6U)
240 
241 #define UDMA_RM_RES_ID_RX_HC (7U)
242 
243 #define UDMA_RM_RES_ID_RX (8U)
244 
245 #define UDMA_RM_RES_ID_GLOBAL_EVENT (9U)
246 
247 #define UDMA_RM_RES_ID_VINTR (10U)
248 
249 #define UDMA_RM_RES_ID_MAPPED_TX_CPSW (11U)
250 
251 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_0 (12U)
252 
253 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_1 (13U)
254 
255 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0 (14U)
256 
257 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1 (15U)
258 
259 #define UDMA_RM_RES_ID_MAPPED_RX_CPSW (16U)
260 
261 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_0 (17U)
262 
263 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_1 (18U)
264 
265 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_2 (19U)
266 
267 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_3 (20U)
268 
269 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0 (21U)
270 
271 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1 (22U)
272 
273 #define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW (23U)
274 
275 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0 (24U)
276 
277 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1 (25U)
278 
279 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0 (26U)
280 
281 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1 (27U)
282 
283 #define UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW (28U)
284 
285 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0 (29U)
286 
287 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1 (30U)
288 
289 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2 (31U)
290 
291 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3 (32U)
292 
293 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0 (33U)
294 
295 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1 (34U)
296 
297 #define UDMA_RM_NUM_BCDMA_RES (11U)
298 
299 #define UDMA_RM_NUM_PKTDMA_RES (35U)
300 
301 #define UDMA_RM_NUM_RES (35U)
302 
306 #define UDMA_RM_NUM_SHARED_RES (2U)
307 
309 #define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE)
310 
312 #define UDMA_PSIL_DEST_THREAD_OFFSET (0x8000U)
313 
323 #define UDMA_PSIL_CH_CPSW2_RX (0x4500U)
324 #define UDMA_PSIL_CH_SAUL0_RX (0x4000U)
325 #define UDMA_PSIL_CH_ICSS_G0_RX (0x4100U)
326 #define UDMA_PSIL_CH_ICSS_G1_RX (0x4200U)
327 
328 #define UDMA_PSIL_CH_CPSW2_TX (UDMA_PSIL_CH_CPSW2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
329 #define UDMA_PSIL_CH_SAUL0_TX (UDMA_PSIL_CH_SAUL0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
330 #define UDMA_PSIL_CH_ICSS_G0_TX (UDMA_PSIL_CH_ICSS_G0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
331 #define UDMA_PSIL_CH_ICSS_G1_TX (UDMA_PSIL_CH_ICSS_G1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
332 
333 #define UDMA_PSIL_CH_CPSW2_TX_CNT (8U)
334 #define UDMA_PSIL_CH_SAUL0_TX_CNT (2U)
335 #define UDMA_PSIL_CH_ICSS_G0_TX_CNT (9U)
336 #define UDMA_PSIL_CH_ICSS_G1_TX_CNT (9U)
337 
338 #define UDMA_PSIL_CH_CPSW2_RX_CNT (1U)
339 #define UDMA_PSIL_CH_SAUL0_RX_CNT (4U)
340 #define UDMA_PSIL_CH_ICSS_G0_RX_CNT (5U)
341 #define UDMA_PSIL_CH_ICSS_G1_RX_CNT (5U)
342 
364 /*
365  * PDMA MAIN0 MCSPI RX Channels
366  */
367 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX (0x4300U + 0U)
368 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX (0x4300U + 1U)
369 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX (0x4300U + 2U)
370 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX (0x4300U + 3U)
371 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX (0x4300U + 4U)
372 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX (0x4300U + 5U)
373 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX (0x4300U + 6U)
374 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX (0x4300U + 7U)
375 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX (0x4300U + 8U)
376 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX (0x4300U + 9U)
377 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX (0x4300U + 10U)
378 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX (0x4300U + 11U)
379 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX (0x4300U + 12U)
380 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX (0x4300U + 13U)
381 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX (0x4300U + 14U)
382 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX (0x4300U + 15U)
383 /*
384  * PDMA MAIN0 UART RX Channels
385  */
386 #define UDMA_PDMA_CH_MAIN0_UART0_RX (0x4300U + 16U)
387 #define UDMA_PDMA_CH_MAIN0_UART1_RX (0x4300U + 17U)
388 /*
389  * PDMA MAIN0 MCASP RX Channels
390  */
391 #define UDMA_PDMA_CH_MAIN0_MCASP0_RX (0x4500U + 0U)
392 #define UDMA_PDMA_CH_MAIN0_MCASP1_RX (0x4500U + 1U)
393 #define UDMA_PDMA_CH_MAIN0_MCASP2_RX (0x4500U + 2U)
394 
406 /*
407  * PDMA MAIN0 MCSPI TX Channels
408  */
409 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
410 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
411 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
412 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
413 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
414 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
415 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
416 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
417 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
418 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
419 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
420 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
421 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
422 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
423 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
424 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
425 /*
426  * PDMA MAIN0 UART TX Channels
427  */
428 #define UDMA_PDMA_CH_MAIN0_UART0_TX (UDMA_PDMA_CH_MAIN0_UART0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
429 #define UDMA_PDMA_CH_MAIN0_UART1_TX (UDMA_PDMA_CH_MAIN0_UART1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
430 /*
431  * PDMA MAIN0 MCASP TX Channels
432  */
433 #define UDMA_PDMA_CH_MAIN0_MCASP0_TX (UDMA_PDMA_CH_MAIN0_MCASP0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
434 #define UDMA_PDMA_CH_MAIN0_MCASP1_TX (UDMA_PDMA_CH_MAIN0_MCASP1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
435 #define UDMA_PDMA_CH_MAIN0_MCASP2_TX (UDMA_PDMA_CH_MAIN0_MCASP2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
436 
448 /*
449  * PDMA MAIN1 MCSPI RX Channels
450  */
451 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX (0x4400U + 0U)
452 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX (0x4400U + 1U)
453 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX (0x4400U + 2U)
454 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX (0x4400U + 3U)
455 /*
456  * PDMA MAIN1 UART RX Channels
457  */
458 #define UDMA_PDMA_CH_MAIN1_UART2_RX (0x4400U + 4U)
459 #define UDMA_PDMA_CH_MAIN1_UART3_RX (0x4400U + 5U)
460 #define UDMA_PDMA_CH_MAIN1_UART4_RX (0x4400U + 6U)
461 #define UDMA_PDMA_CH_MAIN1_UART5_RX (0x4400U + 7U)
462 #define UDMA_PDMA_CH_MAIN1_UART6_RX (0x4400U + 8U)
463 /*
464  * PDMA MAIN1 MCAN RX Channels
465  */
466 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX (0x4400U + 9U)
467 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX (0x4400U + 10U)
468 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX (0x4400U + 11U)
469 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX (0x4400U + 12U)
470 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX (0x4400U + 13U)
471 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX (0x4400U + 14U)
472 /*
473  * PDMA MAIN1 ADC RX Channels
474  */
475 #define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX (0x4400U + 15U)
476 #define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX (0x4400U + 16U)
477 
489 /*
490  * PDMA MAIN1 MCSPI TX Channels
491  */
492 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
493 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
494 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
495 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
496 /*
497  * PDMA MAIN1 UART TX Channels
498  */
499 #define UDMA_PDMA_CH_MAIN1_UART2_TX (UDMA_PDMA_CH_MAIN1_UART2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
500 #define UDMA_PDMA_CH_MAIN1_UART3_TX (UDMA_PDMA_CH_MAIN1_UART3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
501 #define UDMA_PDMA_CH_MAIN1_UART4_TX (UDMA_PDMA_CH_MAIN1_UART4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
502 #define UDMA_PDMA_CH_MAIN1_UART5_TX (UDMA_PDMA_CH_MAIN1_UART5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
503 #define UDMA_PDMA_CH_MAIN1_UART6_TX (UDMA_PDMA_CH_MAIN1_UART6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
504 /*
505  * PDMA MAIN1 MCAN TX Channels
506  */
507 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
508 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
509 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
510 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
511 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
512 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
513 
515 /* Channel information for local DRU channels */
517 #define UDMA_UTC_START_CH_DRU (0U)
518 
519 #define UDMA_UTC_NUM_CH_DRU (32U)
520 
521 /* Start of C7x events associated to CLEC that UDMA Driver will manage */
522 #define UDMA_C7X_CORE_INTR_OFFSET (32U)
523 /* Number of C7x Events available for UDMA */
524 #define UDMA_C7X_CORE_NUM_INTR (16)
525 
526 /* CLEC offset for VINT */
527 #define UDMA_VINT_CLEC_OFFSET (192)
528 
531 /* ========================================================================== */
532 /* Structure Declarations */
533 /* ========================================================================== */
534 
535 /* None */
536 
537 /* ========================================================================== */
538 /* Function Declarations */
539 /* ========================================================================== */
540 
546 uint32_t Udma_isCacheCoherent(void);
547 
553 uint32_t Udma_getCoreId(void);
554 
558 void inline Udma_updateDruRegs(uint32_t instId, void *pDruNrt, void *pDruRt);
559 
560 /* ========================================================================== */
561 /* Static Function Definitions */
562 /* ========================================================================== */
563 
564 /* None */
565 
566 #ifdef __cplusplus
567 }
568 #endif
569 
570 #endif /* #ifndef UDMA_SOC_H_ */
Udma_isCacheCoherent
uint32_t Udma_isCacheCoherent(void)
Returns TRUE if the memory is cache coherent.
Udma_getCoreId
uint32_t Udma_getCoreId(void)
Returns the core ID.
Udma_updateDruRegs
void Udma_updateDruRegs(uint32_t instId, void *pDruNrt, void *pDruRt)
Updates DRU Registers.