70 #pragma CHECK_MISRA ("none") 76 #pragma RESET_MISRA ("required") 78 #define Cache_EMIFA_CFG 0x1e00000 79 #define Cache_EMIFA_BASE 0x2000000 80 #define Cache_EMIFA_LENGTH 0x8000000 82 #define Cache_EMIFB_CFG 0x20000000 83 #define Cache_EMIFB_BASE 0x80000000 84 #define Cache_EMIFB_LENGTH 0x10000000 86 #define Cache_EMIFC_CFG 0x1e00000 87 #define Cache_EMIFC_BASE 0x42000000 88 #define Cache_EMIFC_LENGTH 0x8000000 90 #define L2CFG (volatile unsigned int *)0x01840000 91 #define L1PCFG (volatile unsigned int *)0x01840020 92 #define L1PCC (volatile unsigned int *)0x01840024 93 #define L1DCFG (volatile unsigned int *)0x01840040 94 #define L1DCC (volatile unsigned int *)0x01840044 95 #define L2WBAR (volatile unsigned int *)0x01844000 96 #define L2WWC (volatile unsigned int *)0x01844004 97 #define L2WIBAR (volatile unsigned int *)0x01844010 98 #define L2IBAR (volatile unsigned int *)0x01844018 99 #define L2WBINV (volatile unsigned int *)0x01845004 100 #define L1DWBINV (volatile unsigned int *)0x01845044 101 #define L1DINV (volatile unsigned int *)0x01845048 102 #define L2INV (volatile unsigned int *)0x01845008 103 #define L1DWb (volatile unsigned int *)0x01845040 104 #define L2Wb (volatile unsigned int *)0x01845000 106 #define L1DWWC (volatile unsigned int *)0x0184404C 118 void Cache_inv(uint8_t* blockPtr,
unsigned int byteCnt,
bool wait);
130 void Cache_wb(uint8_t* blockPtr,
unsigned int byteCnt,
bool wait);
142 void Cache_wbInv(uint8_t* blockPtr,
unsigned int byteCnt,
bool wait);
void Cache_wb(uint8_t *blockPtr, unsigned int byteCnt, bool wait)
void Cache_wbInv(uint8_t *blockPtr, unsigned int byteCnt, bool wait)
void Cache_inv(uint8_t *blockPtr, unsigned int byteCnt, bool wait)