TI Autonomous Driving Algorithms (TIADALG) Library User Guide
cache.h
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62 
63 
64 #ifndef CACHE_H_
65 #define CACHE_H_
66 
67 
68 #if (!HOST_EMULATION)
69 
70 #pragma CHECK_MISRA ("none")
71 #include <stdio.h>
72 #include <stdlib.h>
73 #include <stdint.h>
74 #include <string.h>
75 #include <stdbool.h>
76 #pragma RESET_MISRA ("required")
77 
78 #define Cache_EMIFA_CFG 0x1e00000
79 #define Cache_EMIFA_BASE 0x2000000
80 #define Cache_EMIFA_LENGTH 0x8000000
81 
82 #define Cache_EMIFB_CFG 0x20000000
83 #define Cache_EMIFB_BASE 0x80000000
84 #define Cache_EMIFB_LENGTH 0x10000000
85 
86 #define Cache_EMIFC_CFG 0x1e00000
87 #define Cache_EMIFC_BASE 0x42000000
88 #define Cache_EMIFC_LENGTH 0x8000000
89 
90 #define L2CFG (volatile unsigned int *)0x01840000
91 #define L1PCFG (volatile unsigned int *)0x01840020
92 #define L1PCC (volatile unsigned int *)0x01840024
93 #define L1DCFG (volatile unsigned int *)0x01840040
94 #define L1DCC (volatile unsigned int *)0x01840044
95 #define L2WBAR (volatile unsigned int *)0x01844000
96 #define L2WWC (volatile unsigned int *)0x01844004
97 #define L2WIBAR (volatile unsigned int *)0x01844010
98 #define L2IBAR (volatile unsigned int *)0x01844018
99 #define L2WBINV (volatile unsigned int *)0x01845004
100 #define L1DWBINV (volatile unsigned int *)0x01845044
101 #define L1DINV (volatile unsigned int *)0x01845048
102 #define L2INV (volatile unsigned int *)0x01845008
103 #define L1DWb (volatile unsigned int *)0x01845040
104 #define L2Wb (volatile unsigned int *)0x01845000
105 
106 #define L1DWWC (volatile unsigned int *)0x0184404C
107 
108 #define MAXWC 0xFF00 /* Max word count per cache operations */
109 
110 /*
111  * ======== Cache_inv ========
112  * Invalidate the range of memory within the specified starting address and
113  * byte count. The range of addresses operated on gets quantized to whole
114  * cache lines in each cache. All cache lines in range are invalidated in L1P
115  * cache. All cache lines in range are invalidated in L1D cache.
116  * All cache lines in range are invaliated in L2 cache.
117  */
118 void Cache_inv(uint8_t* blockPtr, unsigned int byteCnt, bool wait);
119 
120 /*
121  * ======== Cache_wb ========
122  * Writes back the range of memory within the specified starting address
123  * and byte count. The range of addresses operated on gets quantized to
124  * whole cache lines in each cache. There is no effect on L1P cache.
125  * All cache lines within the range are left valid in L1D cache and the data
126  * within the range in L1D cache will be written back to L2 or external.
127  * All cache lines within the range are left valid in L2 cache and the data
128  * within the range in L2 cache will be written back to external.
129  */
130 void Cache_wb(uint8_t* blockPtr, unsigned int byteCnt, bool wait);
131 
132 /*
133  * ======== Cache_wbInv ========
134  * Writes back and invalidates the range of memory within the specified
135  * starting address and byte count. The range of addresses operated on gets
136  * quantized to whole cache lines in each cache. All cache lines within range
137  * are invalidated in L1P cache. All cache lines within the range are
138  * written back to L2 or external and then invalidated in L1D cache
139  * All cache lines within the range are written back to external and then
140  * invalidated in L2 cache.
141  */
142 void Cache_wbInv(uint8_t* blockPtr, unsigned int byteCnt, bool wait);
143 
144 /* Writeback Invalidate Cache */
145 void Cache_WbInvAll();
146 
147 /* Invalidate Cache */
148 void Cache_InvAll();
149 
150 /* Writeback Cache */
151 void Cache_WbAll();
152 
153 #endif
154 #endif /* CACHE_H_ */
void Cache_InvAll()
void Cache_wb(uint8_t *blockPtr, unsigned int byteCnt, bool wait)
void Cache_wbInv(uint8_t *blockPtr, unsigned int byteCnt, bool wait)
void Cache_WbInvAll()
void Cache_WbAll()
void Cache_inv(uint8_t *blockPtr, unsigned int byteCnt, bool wait)

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