J722S MCU+ SDK
09.02.00
Macros
tisci_clocks.h File Reference
Go to the source code of this file.
Macros
#define
TISCI_DEV_DPHY_RX0_IO_RX_CL_L_M
2
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#define
TISCI_DEV_DPHY_RX0_IO_RX_CL_L_P
3
#define
TISCI_DEV_DPHY_RX0_JTAG_TCK
4
#define
TISCI_DEV_DPHY_RX0_MAIN_CLK_CLK
5
#define
TISCI_DEV_DPHY_RX0_PPI_RX_BYTE_CLK
6
#define
TISCI_DEV_DPHY_RX1_IO_RX_CL_L_M
2
#define
TISCI_DEV_DPHY_RX1_IO_RX_CL_L_P
3
#define
TISCI_DEV_DPHY_RX1_JTAG_TCK
4
#define
TISCI_DEV_DPHY_RX1_MAIN_CLK_CLK
5
#define
TISCI_DEV_DPHY_RX1_PPI_RX_BYTE_CLK
6
#define
TISCI_DEV_DPHY_RX2_IO_RX_CL_L_M
2
#define
TISCI_DEV_DPHY_RX2_IO_RX_CL_L_P
3
#define
TISCI_DEV_DPHY_RX2_JTAG_TCK
4
#define
TISCI_DEV_DPHY_RX2_MAIN_CLK_CLK
5
#define
TISCI_DEV_DPHY_RX2_PPI_RX_BYTE_CLK
6
#define
TISCI_DEV_DPHY_RX3_IO_RX_CL_L_M
2
#define
TISCI_DEV_DPHY_RX3_IO_RX_CL_L_P
3
#define
TISCI_DEV_DPHY_RX3_JTAG_TCK
4
#define
TISCI_DEV_DPHY_RX3_MAIN_CLK_CLK
5
#define
TISCI_DEV_DPHY_RX3_PPI_RX_BYTE_CLK
6
#define
TISCI_DEV_DBGSUSPENDROUTER0_INTR_CLK
0
#define
TISCI_DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK
0
#define
TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_CLK
0
#define
TISCI_DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK
0
#define
TISCI_DEV_ATL0_ATL_CLK
0
#define
TISCI_DEV_ATL0_ATL_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK
1
#define
TISCI_DEV_ATL0_ATL_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK
2
#define
TISCI_DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK
3
#define
TISCI_DEV_ATL0_ATL_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK
5
#define
TISCI_DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
6
#define
TISCI_DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
7
#define
TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT
9
#define
TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1
10
#define
TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2
11
#define
TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3
12
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS
13
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP0_AFSX_OUT
14
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP1_AFSX_OUT
15
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP2_AFSX_OUT
16
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP3_AFSX_OUT
17
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP4_AFSX_OUT
18
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0
19
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0
20
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0
21
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0
22
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0
23
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
24
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
25
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
26
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1
30
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT
31
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT
32
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT
33
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT
34
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT
35
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0
36
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0
37
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0
38
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0
39
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0
40
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
41
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
42
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
43
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2
53
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT
54
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT
55
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT
56
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT
57
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT
58
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0
59
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0
60
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0
61
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0
62
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0
63
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
64
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
65
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
66
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3
70
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT
71
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT
72
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT
73
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT
74
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT
75
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0
76
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0
77
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0
78
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0
79
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0
80
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
81
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
82
#define
TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
83
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS
93
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP0_AFSR_OUT
94
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP1_AFSR_OUT
95
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP2_AFSR_OUT
96
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP3_AFSR_OUT
97
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP4_AFSR_OUT
98
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP0_AFSX_OUT
99
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP1_AFSX_OUT
100
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP2_AFSX_OUT
101
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP3_AFSX_OUT
102
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP4_AFSX_OUT
103
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
104
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
105
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
106
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1
110
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP0_AFSR_OUT
111
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP1_AFSR_OUT
112
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP2_AFSR_OUT
113
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP3_AFSR_OUT
114
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP4_AFSR_OUT
115
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT
116
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT
117
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT
118
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT
119
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT
120
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
121
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
122
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
123
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2
133
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP0_AFSR_OUT
134
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP1_AFSR_OUT
135
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP2_AFSR_OUT
136
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP3_AFSR_OUT
137
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP4_AFSR_OUT
138
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT
139
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT
140
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT
141
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT
142
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT
143
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
144
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
145
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
146
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3
150
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP0_AFSR_OUT
151
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP1_AFSR_OUT
152
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP2_AFSR_OUT
153
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP3_AFSR_OUT
154
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP4_AFSR_OUT
155
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT
156
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT
157
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT
158
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT
159
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT
160
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
161
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
162
#define
TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
163
#define
TISCI_DEV_ATL0_VBUS_CLK
173
#define
TISCI_DEV_CPSW0_CPPI_CLK_CLK
0
#define
TISCI_DEV_CPSW0_CPTS_GENF0
1
#define
TISCI_DEV_CPSW0_CPTS_GENF1
2
#define
TISCI_DEV_CPSW0_CPTS_RFT_CLK
3
#define
TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK
4
#define
TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK
5
#define
TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
6
#define
TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
8
#define
TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
9
#define
TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_1_IP1_LN0_TXMCLK
10
#define
TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK
11
#define
TISCI_DEV_CPSW0_GMII1_MR_CLK
13
#define
TISCI_DEV_CPSW0_GMII1_MT_CLK
14
#define
TISCI_DEV_CPSW0_GMII2_MR_CLK
15
#define
TISCI_DEV_CPSW0_GMII2_MT_CLK
16
#define
TISCI_DEV_CPSW0_GMII_RFT_CLK
17
#define
TISCI_DEV_CPSW0_MDIO_MDCLK_O
18
#define
TISCI_DEV_CPSW0_RGMII_MHZ_250_CLK
19
#define
TISCI_DEV_CPSW0_RGMII_MHZ_50_CLK
20
#define
TISCI_DEV_CPSW0_RGMII_MHZ_5_CLK
21
#define
TISCI_DEV_CPSW0_RMII1_MHZ_50_CLK
22
#define
TISCI_DEV_CPSW0_RMII2_MHZ_50_CLK
23
#define
TISCI_DEV_CPSW0_SERDES1_REFCLK
24
#define
TISCI_DEV_CPSW0_SERDES1_RXCLK
25
#define
TISCI_DEV_CPSW0_SERDES1_RXFCLK
26
#define
TISCI_DEV_CPSW0_SERDES1_TXCLK
27
#define
TISCI_DEV_CPSW0_SERDES1_TXFCLK
28
#define
TISCI_DEV_CPSW0_SERDES1_TXMCLK
29
#define
TISCI_DEV_CPSW0_SERDES2_REFCLK
30
#define
TISCI_DEV_CPSW0_SERDES2_RXCLK
31
#define
TISCI_DEV_CPSW0_SERDES2_RXFCLK
32
#define
TISCI_DEV_CPSW0_SERDES2_TXCLK
33
#define
TISCI_DEV_CPSW0_SERDES2_TXFCLK
34
#define
TISCI_DEV_CPSW0_SERDES2_TXMCLK
35
#define
TISCI_DEV_CPT2_AGGR1_VCLK_CLK
0
#define
TISCI_DEV_CPT2_AGGR0_VCLK_CLK
0
#define
TISCI_DEV_MCU_CPT2_AGGR0_VCLK_CLK
0
#define
TISCI_DEV_CSI_RX_IF0_MAIN_CLK_CLK
0
#define
TISCI_DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK
2
#define
TISCI_DEV_CSI_RX_IF0_VBUS_CLK_CLK
3
#define
TISCI_DEV_CSI_RX_IF0_VP_CLK_CLK
4
#define
TISCI_DEV_CSI_RX_IF1_MAIN_CLK_CLK
0
#define
TISCI_DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK
2
#define
TISCI_DEV_CSI_RX_IF1_VBUS_CLK_CLK
3
#define
TISCI_DEV_CSI_RX_IF1_VP_CLK_CLK
4
#define
TISCI_DEV_CSI_RX_IF2_MAIN_CLK_CLK
0
#define
TISCI_DEV_CSI_RX_IF2_PPI_RX_BYTE_CLK
2
#define
TISCI_DEV_CSI_RX_IF2_VBUS_CLK_CLK
3
#define
TISCI_DEV_CSI_RX_IF2_VP_CLK_CLK
4
#define
TISCI_DEV_CSI_RX_IF3_MAIN_CLK_CLK
0
#define
TISCI_DEV_CSI_RX_IF3_PPI_RX_BYTE_CLK
2
#define
TISCI_DEV_CSI_RX_IF3_VBUS_CLK_CLK
3
#define
TISCI_DEV_CSI_RX_IF3_VP_CLK_CLK
4
#define
TISCI_DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK
2
#define
TISCI_DEV_CSI_TX_IF0_ESC_CLK_CLK
3
#define
TISCI_DEV_CSI_TX_IF0_MAIN_CLK_CLK
4
#define
TISCI_DEV_CSI_TX_IF0_VBUS_CLK_CLK
5
#define
TISCI_DEV_STM0_ATB_CLK
0
#define
TISCI_DEV_STM0_CORE_CLK
1
#define
TISCI_DEV_STM0_VBUSP_CLK
2
#define
TISCI_DEV_DCC0_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_DCC0_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_DCC0_DCC_CLKSRC2_CLK
2
#define
TISCI_DEV_DCC0_DCC_CLKSRC3_CLK
3
#define
TISCI_DEV_DCC0_DCC_CLKSRC4_CLK
4
#define
TISCI_DEV_DCC0_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_DCC0_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_DCC0_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_DCC0_DCC_INPUT00_CLK
8
#define
TISCI_DEV_DCC0_DCC_INPUT01_CLK
9
#define
TISCI_DEV_DCC0_DCC_INPUT02_CLK
10
#define
TISCI_DEV_DCC0_DCC_INPUT10_CLK
11
#define
TISCI_DEV_DCC0_VBUS_CLK
12
#define
TISCI_DEV_DCC1_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_DCC1_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_DCC1_DCC_CLKSRC2_CLK
2
#define
TISCI_DEV_DCC1_DCC_CLKSRC3_CLK
3
#define
TISCI_DEV_DCC1_DCC_CLKSRC4_CLK
4
#define
TISCI_DEV_DCC1_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_DCC1_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_DCC1_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_DCC1_DCC_INPUT00_CLK
8
#define
TISCI_DEV_DCC1_DCC_INPUT01_CLK
9
#define
TISCI_DEV_DCC1_DCC_INPUT02_CLK
10
#define
TISCI_DEV_DCC1_DCC_INPUT10_CLK
11
#define
TISCI_DEV_DCC1_VBUS_CLK
12
#define
TISCI_DEV_DCC2_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_DCC2_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_DCC2_DCC_CLKSRC2_CLK
2
#define
TISCI_DEV_DCC2_DCC_CLKSRC3_CLK
3
#define
TISCI_DEV_DCC2_DCC_CLKSRC4_CLK
4
#define
TISCI_DEV_DCC2_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_DCC2_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_DCC2_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_DCC2_DCC_INPUT00_CLK
8
#define
TISCI_DEV_DCC2_DCC_INPUT01_CLK
9
#define
TISCI_DEV_DCC2_DCC_INPUT02_CLK
10
#define
TISCI_DEV_DCC2_DCC_INPUT10_CLK
11
#define
TISCI_DEV_DCC2_VBUS_CLK
12
#define
TISCI_DEV_DCC3_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_DCC3_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_DCC3_DCC_CLKSRC2_CLK
2
#define
TISCI_DEV_DCC3_DCC_CLKSRC3_CLK
3
#define
TISCI_DEV_DCC3_DCC_CLKSRC4_CLK
4
#define
TISCI_DEV_DCC3_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_DCC3_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_DCC3_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_DCC3_DCC_INPUT00_CLK
8
#define
TISCI_DEV_DCC3_DCC_INPUT01_CLK
9
#define
TISCI_DEV_DCC3_DCC_INPUT02_CLK
10
#define
TISCI_DEV_DCC3_DCC_INPUT10_CLK
11
#define
TISCI_DEV_DCC3_VBUS_CLK
12
#define
TISCI_DEV_DCC4_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_DCC4_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_DCC4_DCC_CLKSRC2_CLK
2
#define
TISCI_DEV_DCC4_DCC_CLKSRC3_CLK
3
#define
TISCI_DEV_DCC4_DCC_CLKSRC4_CLK
4
#define
TISCI_DEV_DCC4_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_DCC4_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_DCC4_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_DCC4_DCC_INPUT00_CLK
8
#define
TISCI_DEV_DCC4_DCC_INPUT01_CLK
9
#define
TISCI_DEV_DCC4_DCC_INPUT02_CLK
10
#define
TISCI_DEV_DCC4_DCC_INPUT10_CLK
11
#define
TISCI_DEV_DCC4_VBUS_CLK
12
#define
TISCI_DEV_DCC5_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_DCC5_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_DCC5_DCC_CLKSRC2_CLK
2
#define
TISCI_DEV_DCC5_DCC_CLKSRC3_CLK
3
#define
TISCI_DEV_DCC5_DCC_CLKSRC4_CLK
4
#define
TISCI_DEV_DCC5_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_DCC5_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_DCC5_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_DCC5_DCC_INPUT00_CLK
8
#define
TISCI_DEV_DCC5_DCC_INPUT01_CLK
9
#define
TISCI_DEV_DCC5_DCC_INPUT02_CLK
10
#define
TISCI_DEV_DCC5_DCC_INPUT10_CLK
11
#define
TISCI_DEV_DCC5_VBUS_CLK
12
#define
TISCI_DEV_DCC6_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_DCC6_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_DCC6_DCC_CLKSRC2_CLK
2
#define
TISCI_DEV_DCC6_DCC_CLKSRC3_CLK
3
#define
TISCI_DEV_DCC6_DCC_CLKSRC4_CLK
4
#define
TISCI_DEV_DCC6_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_DCC6_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_DCC6_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_DCC6_DCC_INPUT00_CLK
8
#define
TISCI_DEV_DCC6_DCC_INPUT01_CLK
9
#define
TISCI_DEV_DCC6_DCC_INPUT02_CLK
10
#define
TISCI_DEV_DCC6_DCC_INPUT10_CLK
11
#define
TISCI_DEV_DCC6_VBUS_CLK
12
#define
TISCI_DEV_DCC7_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_DCC7_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_DCC7_DCC_CLKSRC2_CLK
2
#define
TISCI_DEV_DCC7_DCC_CLKSRC3_CLK
3
#define
TISCI_DEV_DCC7_DCC_CLKSRC4_CLK
4
#define
TISCI_DEV_DCC7_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_DCC7_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_DCC7_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_DCC7_DCC_INPUT00_CLK
8
#define
TISCI_DEV_DCC7_DCC_INPUT01_CLK
9
#define
TISCI_DEV_DCC7_DCC_INPUT02_CLK
10
#define
TISCI_DEV_DCC7_DCC_INPUT10_CLK
11
#define
TISCI_DEV_DCC7_VBUS_CLK
12
#define
TISCI_DEV_DCC8_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_DCC8_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_DCC8_DCC_CLKSRC2_CLK
2
#define
TISCI_DEV_DCC8_DCC_CLKSRC3_CLK
3
#define
TISCI_DEV_DCC8_DCC_CLKSRC4_CLK
4
#define
TISCI_DEV_DCC8_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_DCC8_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_DCC8_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_DCC8_DCC_INPUT00_CLK
8
#define
TISCI_DEV_DCC8_DCC_INPUT01_CLK
9
#define
TISCI_DEV_DCC8_DCC_INPUT02_CLK
10
#define
TISCI_DEV_DCC8_DCC_INPUT10_CLK
11
#define
TISCI_DEV_DCC8_VBUS_CLK
12
#define
TISCI_DEV_MCU_DCC0_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_MCU_DCC0_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_MCU_DCC0_DCC_CLKSRC2_CLK
2
#define
TISCI_DEV_MCU_DCC0_DCC_CLKSRC3_CLK
3
#define
TISCI_DEV_MCU_DCC0_DCC_CLKSRC4_CLK
4
#define
TISCI_DEV_MCU_DCC0_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_MCU_DCC0_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_MCU_DCC0_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_MCU_DCC0_DCC_INPUT00_CLK
8
#define
TISCI_DEV_MCU_DCC0_DCC_INPUT01_CLK
9
#define
TISCI_DEV_MCU_DCC0_DCC_INPUT02_CLK
10
#define
TISCI_DEV_MCU_DCC0_DCC_INPUT10_CLK
11
#define
TISCI_DEV_MCU_DCC0_VBUS_CLK
12
#define
TISCI_DEV_MCU_DCC1_DCC_CLKSRC0_CLK
0
#define
TISCI_DEV_MCU_DCC1_DCC_CLKSRC1_CLK
1
#define
TISCI_DEV_MCU_DCC1_DCC_CLKSRC5_CLK
5
#define
TISCI_DEV_MCU_DCC1_DCC_CLKSRC6_CLK
6
#define
TISCI_DEV_MCU_DCC1_DCC_CLKSRC7_CLK
7
#define
TISCI_DEV_MCU_DCC1_DCC_INPUT00_CLK
8
#define
TISCI_DEV_MCU_DCC1_DCC_INPUT01_CLK
9
#define
TISCI_DEV_MCU_DCC1_DCC_INPUT02_CLK
10
#define
TISCI_DEV_MCU_DCC1_DCC_INPUT10_CLK
11
#define
TISCI_DEV_MCU_DCC1_VBUS_CLK
12
#define
TISCI_DEV_DEBUGSS_WRAP0_ATB_CLK
0
#define
TISCI_DEV_DEBUGSS_WRAP0_CORE_CLK
1
#define
TISCI_DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK
2
#define
TISCI_DEV_DEBUGSS_WRAP0_JTAG_TCK
20
#define
TISCI_DEV_DEBUGSS_WRAP0_P1500_WRCK
21
#define
TISCI_DEV_DEBUGSS_WRAP0_TREXPT_CLK
22
#define
TISCI_DEV_DMASS0_BCDMA_0_CLK
0
#define
TISCI_DEV_DMASS0_CBASS_0_CLK
0
#define
TISCI_DEV_DMASS0_INTAGGR_0_CLK
0
#define
TISCI_DEV_DMASS0_IPCSS_0_CLK
0
#define
TISCI_DEV_DMASS0_PKTDMA_0_CLK
0
#define
TISCI_DEV_DMASS0_RINGACC_0_CLK
0
#define
TISCI_DEV_DMASS1_BCDMA_0_CLK
0
#define
TISCI_DEV_DMASS1_INTAGGR_0_CLK
0
#define
TISCI_DEV_TIMER0_TIMER_HCLK_CLK
0
#define
TISCI_DEV_TIMER0_TIMER_PWM
1
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK
2
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
3
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0
4
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK
5
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
6
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
7
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
8
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
10
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK
11
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK
12
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
13
#define
TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1
14
#define
TISCI_DEV_TIMER1_TIMER_HCLK_CLK
0
#define
TISCI_DEV_TIMER1_TIMER_PWM
1
#define
TISCI_DEV_TIMER1_TIMER_TCLK_CLK
2
#define
TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT1
3
#define
TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM
4
#define
TISCI_DEV_TIMER2_TIMER_HCLK_CLK
0
#define
TISCI_DEV_TIMER2_TIMER_PWM
1
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK
2
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
3
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0
4
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK
5
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
6
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
7
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
8
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
10
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK
11
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK
12
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
13
#define
TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1
14
#define
TISCI_DEV_TIMER3_TIMER_HCLK_CLK
0
#define
TISCI_DEV_TIMER3_TIMER_PWM
1
#define
TISCI_DEV_TIMER3_TIMER_TCLK_CLK
2
#define
TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT3
3
#define
TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM
4
#define
TISCI_DEV_TIMER4_TIMER_HCLK_CLK
0
#define
TISCI_DEV_TIMER4_TIMER_PWM
1
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK
2
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
3
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0
4
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK
5
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
6
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
7
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
8
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
10
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK
11
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK
12
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
13
#define
TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1
14
#define
TISCI_DEV_TIMER5_TIMER_HCLK_CLK
0
#define
TISCI_DEV_TIMER5_TIMER_PWM
1
#define
TISCI_DEV_TIMER5_TIMER_TCLK_CLK
2
#define
TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT5
3
#define
TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM
4
#define
TISCI_DEV_TIMER6_TIMER_HCLK_CLK
0
#define
TISCI_DEV_TIMER6_TIMER_PWM
1
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK
2
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
3
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0
4
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK
5
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
6
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
7
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
8
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
10
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK
11
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK
12
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
13
#define
TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1
14
#define
TISCI_DEV_TIMER7_TIMER_HCLK_CLK
0
#define
TISCI_DEV_TIMER7_TIMER_PWM
1
#define
TISCI_DEV_TIMER7_TIMER_TCLK_CLK
2
#define
TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT7
3
#define
TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM
4
#define
TISCI_DEV_MCU_TIMER0_TIMER_HCLK_CLK
0
#define
TISCI_DEV_MCU_TIMER0_TIMER_PWM
1
#define
TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK
2
#define
TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
3
#define
TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4
4
#define
TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
5
#define
TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK
6
#define
TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
7
#define
TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0
8
#define
TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
9
#define
TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
10
#define
TISCI_DEV_MCU_TIMER1_TIMER_HCLK_CLK
0
#define
TISCI_DEV_MCU_TIMER1_TIMER_PWM
1
#define
TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK
2
#define
TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT1
3
#define
TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM
4
#define
TISCI_DEV_MCU_TIMER2_TIMER_HCLK_CLK
0
#define
TISCI_DEV_MCU_TIMER2_TIMER_PWM
1
#define
TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK
2
#define
TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
3
#define
TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4
4
#define
TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
5
#define
TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK
6
#define
TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
7
#define
TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0
8
#define
TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
9
#define
TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
10
#define
TISCI_DEV_MCU_TIMER3_TIMER_HCLK_CLK
0
#define
TISCI_DEV_MCU_TIMER3_TIMER_PWM
1
#define
TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK
2
#define
TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT3
3
#define
TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM
4
#define
TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK
0
#define
TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK
1
#define
TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
2
#define
TISCI_DEV_WKUP_TIMER0_TIMER_PWM
3
#define
TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK
4
#define
TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
5
#define
TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT04
6
#define
TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
7
#define
TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK
8
#define
TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
9
#define
TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0
10
#define
TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
11
#define
TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
12
#define
TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK
0
#define
TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK
1
#define
TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
2
#define
TISCI_DEV_WKUP_TIMER1_TIMER_TCLK_CLK
4
#define
TISCI_DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT1
5
#define
TISCI_DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_WKUP_0_TIMER_PWM
6
#define
TISCI_DEV_ECAP0_VBUS_CLK
0
#define
TISCI_DEV_ECAP1_VBUS_CLK
0
#define
TISCI_DEV_ECAP2_VBUS_CLK
0
#define
TISCI_DEV_ELM0_VBUSP_CLK
0
#define
TISCI_DEV_MMCSD0_EMMCSS_VBUS_CLK
1
#define
TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK
2
#define
TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK
3
#define
TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK
4
#define
TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I
0
#define
TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT
1
#define
TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLK_OUT
2
#define
TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_O
3
#define
TISCI_DEV_MMCSD1_EMMCSDSS_VBUS_CLK
5
#define
TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK
6
#define
TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK
7
#define
TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK
8
#define
TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I
0
#define
TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLKLB_OUT
1
#define
TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLK_OUT
2
#define
TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_O
3
#define
TISCI_DEV_MMCSD2_EMMCSDSS_VBUS_CLK
5
#define
TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK
6
#define
TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK
7
#define
TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK
8
#define
TISCI_DEV_EQEP0_VBUS_CLK
0
#define
TISCI_DEV_EQEP1_VBUS_CLK
0
#define
TISCI_DEV_EQEP2_VBUS_CLK
0
#define
TISCI_DEV_WKUP_ESM0_CLK
0
#define
TISCI_DEV_ESM0_CLK
0
#define
TISCI_DEV_FSS0_FSAS_0_GCLK
0
#define
TISCI_DEV_FSS0_OSPI_0_OSPI_DQS_CLK
0
#define
TISCI_DEV_FSS0_OSPI_0_OSPI_HCLK_CLK
1
#define
TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK
2
#define
TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT
3
#define
TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT
4
#define
TISCI_DEV_FSS0_OSPI_0_OSPI_OCLK_CLK
5
#define
TISCI_DEV_FSS0_OSPI_0_OSPI_PCLK_CLK
6
#define
TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK
7
#define
TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK
8
#define
TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK
9
#define
TISCI_DEV_GICSS0_VCLK_CLK
0
#define
TISCI_DEV_GPIO0_MMR_CLK
0
#define
TISCI_DEV_GPIO1_MMR_CLK
0
#define
TISCI_DEV_MCU_GPIO0_MMR_CLK
0
#define
TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4
1
#define
TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT
2
#define
TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
3
#define
TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
4
#define
TISCI_DEV_GPMC0_FUNC_CLK
0
#define
TISCI_DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK
1
#define
TISCI_DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK
2
#define
TISCI_DEV_GPMC0_PI_GPMC_RET_CLK
3
#define
TISCI_DEV_GPMC0_PO_GPMC_DEV_CLK
4
#define
TISCI_DEV_GPMC0_VBUSM_CLK
5
#define
TISCI_DEV_WKUP_GTC0_GTC_CLK
0
#define
TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK
1
#define
TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK
2
#define
TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
3
#define
TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
5
#define
TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
6
#define
TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2
7
#define
TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK
8
#define
TISCI_DEV_WKUP_GTC0_VBUSP_CLK
9
#define
TISCI_DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK
10
#define
TISCI_DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
11
#define
TISCI_DEV_DDPA0_DDPA_CLK
0
#define
TISCI_DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK
0
#define
TISCI_DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK
1
#define
TISCI_DEV_DSS_DSI0_DPI_0_CLK
2
#define
TISCI_DEV_DSS_DSI0_PLL_CTRL_CLK
3
#define
TISCI_DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK
4
#define
TISCI_DEV_DSS_DSI0_SYS_CLK
5
#define
TISCI_DEV_DSS0_DPI_0_IN_CLK
0
#define
TISCI_DEV_DSS0_DPI_1_IN_CLK
2
#define
TISCI_DEV_DSS0_DPI_1_IN_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK
3
#define
TISCI_DEV_DSS0_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT
4
#define
TISCI_DEV_DSS0_DPI_1_OUT_CLK
5
#define
TISCI_DEV_DSS0_DSS_FUNC_CLK
6
#define
TISCI_DEV_DSS1_DPI_0_IN_CLK
0
#define
TISCI_DEV_DSS1_DPI_0_IN_CLK_PARENT_MAIN_DSS1_DPI0__PLLSEL_OUT0
1
#define
TISCI_DEV_DSS1_DPI_0_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT
2
#define
TISCI_DEV_DSS1_DPI_0_OUT_CLK
3
#define
TISCI_DEV_DSS1_DPI_1_IN_CLK
4
#define
TISCI_DEV_DSS1_DPI_1_IN_CLK_PARENT_MAIN_DSS1_DPI1__PLLSEL_OUT0
5
#define
TISCI_DEV_DSS1_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT
6
#define
TISCI_DEV_DSS1_DPI_1_OUT_CLK
7
#define
TISCI_DEV_DSS1_DSS_FUNC_CLK
8
#define
TISCI_DEV_EPWM0_VBUSP_CLK
0
#define
TISCI_DEV_EPWM1_VBUSP_CLK
0
#define
TISCI_DEV_EPWM2_VBUSP_CLK
0
#define
TISCI_DEV_JPGENC0_CORE_CLK
0
#define
TISCI_DEV_LED0_VBUS_CLK
1
#define
TISCI_DEV_PBIST0_CLK8_CLK
7
#define
TISCI_DEV_PBIST0_TCLK_CLK
9
#define
TISCI_DEV_PBIST1_CLK8_CLK
7
#define
TISCI_DEV_PBIST1_TCLK_CLK
9
#define
TISCI_DEV_WKUP_PBIST0_CLK8_CLK
7
#define
TISCI_DEV_PBIST2_CLK8_CLK
7
#define
TISCI_DEV_PBIST2_TCLK_CLK
9
#define
TISCI_DEV_MCU_PBIST0_CLK8_CLK
7
#define
TISCI_DEV_CODEC0_VPU_ACLK_CLK
0
#define
TISCI_DEV_CODEC0_VPU_BCLK_CLK
1
#define
TISCI_DEV_CODEC0_VPU_CCLK_CLK
2
#define
TISCI_DEV_CODEC0_VPU_PCLK_CLK
3
#define
TISCI_DEV_WKUP_VTM0_FIX_REF2_CLK
0
#define
TISCI_DEV_WKUP_VTM0_FIX_REF_CLK
1
#define
TISCI_DEV_WKUP_VTM0_VBUSP_CLK
2
#define
TISCI_DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK
3
#define
TISCI_DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
4
#define
TISCI_DEV_MCAN0_MCANSS_CCLK_CLK
1
#define
TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK
2
#define
TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
3
#define
TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
4
#define
TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
5
#define
TISCI_DEV_MCAN0_MCANSS_HCLK_CLK
6
#define
TISCI_DEV_MCAN1_MCANSS_CCLK_CLK
1
#define
TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK
2
#define
TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
3
#define
TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
4
#define
TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
5
#define
TISCI_DEV_MCAN1_MCANSS_HCLK_CLK
6
#define
TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK
1
#define
TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK
2
#define
TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
3
#define
TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
4
#define
TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0
5
#define
TISCI_DEV_MCU_MCAN0_MCANSS_HCLK_CLK
6
#define
TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK
1
#define
TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK
2
#define
TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
3
#define
TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
4
#define
TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0
5
#define
TISCI_DEV_MCU_MCAN1_MCANSS_HCLK_CLK
6
#define
TISCI_DEV_MCASP0_AUX_CLK
0
#define
TISCI_DEV_MCASP0_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK
1
#define
TISCI_DEV_MCASP0_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK
2
#define
TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
5
#define
TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
6
#define
TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
7
#define
TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
8
#define
TISCI_DEV_MCASP0_MCASP_ACLKR_PIN
9
#define
TISCI_DEV_MCASP0_MCASP_ACLKR_POUT
10
#define
TISCI_DEV_MCASP0_MCASP_ACLKX_PIN
11
#define
TISCI_DEV_MCASP0_MCASP_ACLKX_POUT
12
#define
TISCI_DEV_MCASP0_MCASP_AFSR_PIN
13
#define
TISCI_DEV_MCASP0_MCASP_AFSR_POUT
14
#define
TISCI_DEV_MCASP0_MCASP_AFSX_PIN
15
#define
TISCI_DEV_MCASP0_MCASP_AFSX_POUT
16
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN
17
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT
18
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
19
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
20
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
21
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
22
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
23
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
24
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
25
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
26
#define
TISCI_DEV_MCASP0_MCASP_AHCLKR_POUT
34
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN
35
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT
36
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
37
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
38
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
39
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
40
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
41
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
42
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
43
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
44
#define
TISCI_DEV_MCASP0_MCASP_AHCLKX_POUT
52
#define
TISCI_DEV_MCASP0_VBUSP_CLK
53
#define
TISCI_DEV_MCASP1_AUX_CLK
0
#define
TISCI_DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK
1
#define
TISCI_DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK
2
#define
TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
5
#define
TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
6
#define
TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
7
#define
TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
8
#define
TISCI_DEV_MCASP1_MCASP_ACLKR_PIN
9
#define
TISCI_DEV_MCASP1_MCASP_ACLKR_POUT
10
#define
TISCI_DEV_MCASP1_MCASP_ACLKX_PIN
11
#define
TISCI_DEV_MCASP1_MCASP_ACLKX_POUT
12
#define
TISCI_DEV_MCASP1_MCASP_AFSR_PIN
13
#define
TISCI_DEV_MCASP1_MCASP_AFSR_POUT
14
#define
TISCI_DEV_MCASP1_MCASP_AFSX_PIN
15
#define
TISCI_DEV_MCASP1_MCASP_AFSX_POUT
16
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN
17
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT
18
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
19
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
20
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
21
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
22
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
23
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
24
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
25
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
26
#define
TISCI_DEV_MCASP1_MCASP_AHCLKR_POUT
34
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN
35
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT
36
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
37
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
38
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
39
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
40
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
41
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
42
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
43
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
44
#define
TISCI_DEV_MCASP1_MCASP_AHCLKX_POUT
52
#define
TISCI_DEV_MCASP1_VBUSP_CLK
53
#define
TISCI_DEV_MCASP2_AUX_CLK
0
#define
TISCI_DEV_MCASP2_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK
1
#define
TISCI_DEV_MCASP2_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK
2
#define
TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
5
#define
TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
6
#define
TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
7
#define
TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
8
#define
TISCI_DEV_MCASP2_MCASP_ACLKR_PIN
9
#define
TISCI_DEV_MCASP2_MCASP_ACLKR_POUT
10
#define
TISCI_DEV_MCASP2_MCASP_ACLKX_PIN
11
#define
TISCI_DEV_MCASP2_MCASP_ACLKX_POUT
12
#define
TISCI_DEV_MCASP2_MCASP_AFSR_PIN
13
#define
TISCI_DEV_MCASP2_MCASP_AFSR_POUT
14
#define
TISCI_DEV_MCASP2_MCASP_AFSX_PIN
15
#define
TISCI_DEV_MCASP2_MCASP_AFSX_POUT
16
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN
17
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT
18
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
19
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
20
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
21
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
22
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
23
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
24
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
25
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
26
#define
TISCI_DEV_MCASP2_MCASP_AHCLKR_POUT
34
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN
35
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT
36
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
37
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
38
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
39
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
40
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
41
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
42
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
43
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
44
#define
TISCI_DEV_MCASP2_MCASP_AHCLKX_POUT
52
#define
TISCI_DEV_MCASP2_VBUSP_CLK
53
#define
TISCI_DEV_MCASP3_AUX_CLK
0
#define
TISCI_DEV_MCASP3_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK
1
#define
TISCI_DEV_MCASP3_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK
2
#define
TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
5
#define
TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
6
#define
TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
7
#define
TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
8
#define
TISCI_DEV_MCASP3_MCASP_ACLKR_PIN
9
#define
TISCI_DEV_MCASP3_MCASP_ACLKR_POUT
10
#define
TISCI_DEV_MCASP3_MCASP_ACLKX_PIN
11
#define
TISCI_DEV_MCASP3_MCASP_ACLKX_POUT
12
#define
TISCI_DEV_MCASP3_MCASP_AFSR_PIN
13
#define
TISCI_DEV_MCASP3_MCASP_AFSR_POUT
14
#define
TISCI_DEV_MCASP3_MCASP_AFSX_PIN
15
#define
TISCI_DEV_MCASP3_MCASP_AFSX_POUT
16
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN
17
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT
18
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
19
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
20
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
21
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
22
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
23
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
24
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
25
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
26
#define
TISCI_DEV_MCASP3_MCASP_AHCLKR_POUT
34
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN
35
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT
36
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
37
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
38
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
39
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
40
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
41
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
42
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
43
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
44
#define
TISCI_DEV_MCASP3_MCASP_AHCLKX_POUT
52
#define
TISCI_DEV_MCASP3_VBUSP_CLK
53
#define
TISCI_DEV_MCASP4_AUX_CLK
0
#define
TISCI_DEV_MCASP4_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK
1
#define
TISCI_DEV_MCASP4_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK
2
#define
TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
5
#define
TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
6
#define
TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
7
#define
TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
8
#define
TISCI_DEV_MCASP4_MCASP_ACLKR_PIN
9
#define
TISCI_DEV_MCASP4_MCASP_ACLKR_POUT
10
#define
TISCI_DEV_MCASP4_MCASP_ACLKX_PIN
11
#define
TISCI_DEV_MCASP4_MCASP_ACLKX_POUT
12
#define
TISCI_DEV_MCASP4_MCASP_AFSR_PIN
13
#define
TISCI_DEV_MCASP4_MCASP_AFSR_POUT
14
#define
TISCI_DEV_MCASP4_MCASP_AFSX_PIN
15
#define
TISCI_DEV_MCASP4_MCASP_AFSX_POUT
16
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN
17
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT
18
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
19
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
20
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
21
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
22
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
23
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
24
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
25
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
26
#define
TISCI_DEV_MCASP4_MCASP_AHCLKR_POUT
34
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN
35
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT
36
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
37
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT
38
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT
39
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT
40
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
41
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
42
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
43
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
44
#define
TISCI_DEV_MCASP4_MCASP_AHCLKX_POUT
52
#define
TISCI_DEV_MCASP4_VBUSP_CLK
53
#define
TISCI_DEV_MCRC64_0_CLK
0
#define
TISCI_DEV_MCU_MCRC64_0_CLK
0
#define
TISCI_DEV_I2C0_CLK
0
#define
TISCI_DEV_I2C0_PISCL
1
#define
TISCI_DEV_I2C0_PISYS_CLK
2
#define
TISCI_DEV_I2C0_PORSCL
3
#define
TISCI_DEV_I2C1_CLK
0
#define
TISCI_DEV_I2C1_PISCL
1
#define
TISCI_DEV_I2C1_PISYS_CLK
2
#define
TISCI_DEV_I2C1_PORSCL
3
#define
TISCI_DEV_I2C2_CLK
0
#define
TISCI_DEV_I2C2_PISCL
1
#define
TISCI_DEV_I2C2_PISYS_CLK
2
#define
TISCI_DEV_I2C2_PORSCL
3
#define
TISCI_DEV_I2C3_CLK
0
#define
TISCI_DEV_I2C3_PISCL
1
#define
TISCI_DEV_I2C3_PISYS_CLK
2
#define
TISCI_DEV_I2C3_PORSCL
3
#define
TISCI_DEV_I2C4_CLK
0
#define
TISCI_DEV_I2C4_PISCL
1
#define
TISCI_DEV_I2C4_PISYS_CLK
2
#define
TISCI_DEV_I2C4_PORSCL
3
#define
TISCI_DEV_MCU_I2C0_CLK
0
#define
TISCI_DEV_MCU_I2C0_PISCL
1
#define
TISCI_DEV_MCU_I2C0_PISYS_CLK
2
#define
TISCI_DEV_MCU_I2C0_PORSCL
3
#define
TISCI_DEV_WKUP_I2C0_CLK
0
#define
TISCI_DEV_WKUP_I2C0_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK
1
#define
TISCI_DEV_WKUP_I2C0_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
2
#define
TISCI_DEV_WKUP_I2C0_PISCL
3
#define
TISCI_DEV_WKUP_I2C0_PISYS_CLK
4
#define
TISCI_DEV_WKUP_I2C0_PORSCL
5
#define
TISCI_DEV_MSRAM8KX256E0_CCLK_CLK
0
#define
TISCI_DEV_MSRAM8KX256E0_VCLK_CLK
1
#define
TISCI_DEV_OLDI_TX_CORE0_OLDI_0_FWD_P_CLK
0
#define
TISCI_DEV_OLDI_TX_CORE0_OLDI_PLL_CLK
5
#define
TISCI_DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK
0
#define
TISCI_DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK
1
#define
TISCI_DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK_PARENT_MAIN_DSS1_DPI0_PCLK_OUT0
2
#define
TISCI_DEV_OLDI_TX_CORE1_OLDI_PLL_CLK
7
#define
TISCI_DEV_OLDI_TX_CORE1_OLDI_PLL_CLK_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK
8
#define
TISCI_DEV_OLDI_TX_CORE1_OLDI_PLL_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK
9
#define
TISCI_DEV_PCIE0_PCIE_CBA_CLK
0
#define
TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK
1
#define
TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK
2
#define
TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK
3
#define
TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
4
#define
TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
6
#define
TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
7
#define
TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B2M4CT_MAIN_1_IP1_LN0_TXMCLK
8
#define
TISCI_DEV_PCIE0_PCIE_LANE0_REFCLK
10
#define
TISCI_DEV_PCIE0_PCIE_LANE0_RXCLK
11
#define
TISCI_DEV_PCIE0_PCIE_LANE0_RXFCLK
12
#define
TISCI_DEV_PCIE0_PCIE_LANE0_TXCLK
13
#define
TISCI_DEV_PCIE0_PCIE_LANE0_TXFCLK
14
#define
TISCI_DEV_PCIE0_PCIE_LANE0_TXMCLK
15
#define
TISCI_DEV_PCIE0_PCIE_PM_CLK
16
#define
TISCI_DEV_R5FSS0_CORE0_CPU_CLK
0
#define
TISCI_DEV_R5FSS0_CORE0_INTERFACE_CLK
1
#define
TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK
0
#define
TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK
1
#define
TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
2
#define
TISCI_DEV_WKUP_R5FSS0_CORE0_INTERFACE_CLK
3
#define
TISCI_DEV_MCU_R5FSS0_CORE0_CPU0_CLK
0
#define
TISCI_DEV_MCU_R5FSS0_CORE0_INTERFACE0_CLK
1
#define
TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK
0
#define
TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_CLK_32K_RC_SEL_OUT0
1
#define
TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
2
#define
TISCI_DEV_WKUP_RTCSS0_JTAG_WRCK
4
#define
TISCI_DEV_WKUP_RTCSS0_VCLK_CLK
6
#define
TISCI_DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK
7
#define
TISCI_DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
8
#define
TISCI_DEV_RTI4_RTI_CLK
0
#define
TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_RTI4_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
4
#define
TISCI_DEV_RTI4_VBUSP_CLK
5
#define
TISCI_DEV_RTI5_RTI_CLK
0
#define
TISCI_DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_RTI5_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
4
#define
TISCI_DEV_RTI5_VBUSP_CLK
5
#define
TISCI_DEV_RTI15_RTI_CLK
0
#define
TISCI_DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_RTI15_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
4
#define
TISCI_DEV_RTI15_VBUSP_CLK
5
#define
TISCI_DEV_RTI0_RTI_CLK
0
#define
TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
4
#define
TISCI_DEV_RTI0_VBUSP_CLK
5
#define
TISCI_DEV_RTI1_RTI_CLK
0
#define
TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
4
#define
TISCI_DEV_RTI1_VBUSP_CLK
5
#define
TISCI_DEV_RTI2_RTI_CLK
0
#define
TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_RTI2_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
4
#define
TISCI_DEV_RTI2_VBUSP_CLK
5
#define
TISCI_DEV_RTI3_RTI_CLK
0
#define
TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_RTI3_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
4
#define
TISCI_DEV_RTI3_VBUSP_CLK
5
#define
TISCI_DEV_RTI8_RTI_CLK
0
#define
TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_RTI8_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
4
#define
TISCI_DEV_RTI8_VBUSP_CLK
5
#define
TISCI_DEV_MCU_RTI0_RTI_CLK
0
#define
TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
4
#define
TISCI_DEV_MCU_RTI0_VBUSP_CLK
5
#define
TISCI_DEV_WKUP_RTI0_RTI_CLK
0
#define
TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
4
#define
TISCI_DEV_WKUP_RTI0_VBUSP_CLK
5
#define
TISCI_DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK
6
#define
TISCI_DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
7
#define
TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK
0
#define
TISCI_DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK
0
#define
TISCI_DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK
0
#define
TISCI_DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK
0
#define
TISCI_DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK
0
#define
TISCI_DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK
2
#define
TISCI_DEV_A53SS0_COREPAC_ARM_CLK_CLK
3
#define
TISCI_DEV_A53SS0_PLL_CTRL_CLK
5
#define
TISCI_DEV_COMPUTE_CLUSTER0_CLKDIV_0_DIVH_CLK4_CLK_CLK
0
#define
TISCI_DEV_COMPUTE_CLUSTER0_CLKDIV_0_DIVP_CLK1_CLK_CLK
1
#define
TISCI_DEV_COMPUTE_CLUSTER0_CLKDIV_0_FUNC_CLKIN_CLK
2
#define
TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0_DIVH_CLK4_CLK_CLK
2
#define
TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0_DIVP_CLK1_CLK_CLK
3
#define
TISCI_DEV_DEBUGSS0_CFG_CLK
0
#define
TISCI_DEV_DEBUGSS0_DBG_CLK
1
#define
TISCI_DEV_DEBUGSS0_SYS_CLK
2
#define
TISCI_DEV_MCU_MCU_16FF0_PLL_CTRL_MCU_CLK24_CLK
3
#define
TISCI_DEV_WKUP_PSC0_CLK
0
#define
TISCI_DEV_WKUP_PSC0_SLOW_CLK
1
#define
TISCI_DEV_A53_RS_BW_LIMITER0_CLK_CLK
0
#define
TISCI_DEV_A53_WS_BW_LIMITER1_CLK_CLK
0
#define
TISCI_DEV_C7XV_RSWS_BS_LIMITER6_CLK_CLK
0
#define
TISCI_DEV_C7XV_RSWS_BS_LIMITER11_CLK_CLK
0
#define
TISCI_DEV_C7X256V0_C7XV_CORE_0_C7XV_CLK
0
#define
TISCI_DEV_C7X256V0_CORE0_DIVH_CLK2_SOC_GCLK
0
#define
TISCI_DEV_C7X256V0_CORE0_DIVH_CLK4_GCLK
1
#define
TISCI_DEV_C7X256V0_CORE0_DIVH_CLK4_SOC_GCLK
2
#define
TISCI_DEV_C7X256V0_CORE0_DIVP_CLK1_GCLK
3
#define
TISCI_DEV_C7X256V0_CORE0_DIVP_CLK1_SOC_GCLK
4
#define
TISCI_DEV_C7X256V0_CLK_C7XV_CLK
0
#define
TISCI_DEV_C7X256V0_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK
1
#define
TISCI_DEV_C7X256V0_CLK_DIVH_CLK2_SOC_GCLK
2
#define
TISCI_DEV_C7X256V0_CLK_DIVH_CLK4_GCLK
3
#define
TISCI_DEV_C7X256V0_CLK_DIVH_CLK4_SOC_GCLK
4
#define
TISCI_DEV_C7X256V0_CLK_DIVP_CLK1_GCLK
5
#define
TISCI_DEV_C7X256V0_CLK_DIVP_CLK1_SOC_GCLK
6
#define
TISCI_DEV_C7X256V0_CLK_PLL_CTRL_CLK
7
#define
TISCI_DEV_C7X256V1_C7XV_CORE_0_C7XV_CLK
0
#define
TISCI_DEV_C7X256V1_CORE0_DIVH_CLK2_SOC_GCLK
0
#define
TISCI_DEV_C7X256V1_CORE0_DIVH_CLK4_GCLK
1
#define
TISCI_DEV_C7X256V1_CORE0_DIVH_CLK4_SOC_GCLK
2
#define
TISCI_DEV_C7X256V1_CORE0_DIVP_CLK1_GCLK
3
#define
TISCI_DEV_C7X256V1_CORE0_DIVP_CLK1_SOC_GCLK
4
#define
TISCI_DEV_C7X256V1_CLK_C7XV_CLK
0
#define
TISCI_DEV_C7X256V1_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK
1
#define
TISCI_DEV_C7X256V1_CLK_DIVH_CLK2_SOC_GCLK
2
#define
TISCI_DEV_C7X256V1_CLK_DIVH_CLK4_GCLK
3
#define
TISCI_DEV_C7X256V1_CLK_DIVH_CLK4_SOC_GCLK
4
#define
TISCI_DEV_C7X256V1_CLK_DIVP_CLK1_GCLK
5
#define
TISCI_DEV_C7X256V1_CLK_DIVP_CLK1_SOC_GCLK
6
#define
TISCI_DEV_C7X256V1_CLK_PLL_CTRL_CLK
7
#define
TISCI_DEV_CTI0_DBG_CLK
0
#define
TISCI_DEV_CTI1_DBG_CLK
0
#define
TISCI_DEV_DDR32SS0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK
0
#define
TISCI_DEV_DDR32SS0_DDRSS_DDR_PLL_CLK
1
#define
TISCI_DEV_DDR32SS0_DDRSS_TCK
2
#define
TISCI_DEV_DDR32SS0_PLL_CTRL_CLK
3
#define
TISCI_DEV_DMPAC0_DMPAC_PLL_CLK
2
#define
TISCI_DEV_DMPAC0_PLL_CTRL_CLK
4
#define
TISCI_DEV_JPGENC_RS_BW_LIMITER4_CLK_CLK
0
#define
TISCI_DEV_JPGENC_WS_BW_LIMITER5_CLK_CLK
0
#define
TISCI_DEV_GPU0_GPU_DCC_CLK
2
#define
TISCI_DEV_GPU0_GPU_PLL_CLK
3
#define
TISCI_DEV_GPU0_PLL_CTRL_CLK
4
#define
TISCI_DEV_GPU_RS_BW_LIMITER9_CLK_CLK
0
#define
TISCI_DEV_GPU_WS_BW_LIMITER10_CLK_CLK
0
#define
TISCI_DEV_PSC0_FW_0_CLK
0
#define
TISCI_DEV_PSC0_CLK
0
#define
TISCI_DEV_PSC0_SLOW_CLK
1
#define
TISCI_DEV_VPAC_RSWS_BW_LIMITER8_CLK_CLK
0
#define
TISCI_DEV_VPAC_RSWS_BW_LIMITER7_CLK_CLK
0
#define
TISCI_DEV_VPAC0_PLL_CTRL_CLK
2
#define
TISCI_DEV_VPAC0_VPAC_PLL_CFG_CLK
4
#define
TISCI_DEV_VPAC0_VPAC_PLL_CLK
5
#define
TISCI_DEV_PBIST3_CLK8_CLK
2
#define
TISCI_DEV_PBIST3_TCLK_CLK
4
#define
TISCI_DEV_CODEC_RS_BW_LIMITER2_CLK_CLK
0
#define
TISCI_DEV_CODEC_WS_BW_LIMITER3_CLK_CLK
0
#define
TISCI_DEV_HSM0_DAP_CLK
0
#define
TISCI_DEV_MCSPI0_CLKSPIREF_CLK
0
#define
TISCI_DEV_MCSPI0_IO_CLKSPII_CLK
1
#define
TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT
2
#define
TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK
3
#define
TISCI_DEV_MCSPI0_IO_CLKSPIO_CLK
4
#define
TISCI_DEV_MCSPI0_VBUSP_CLK
5
#define
TISCI_DEV_MCSPI1_CLKSPIREF_CLK
0
#define
TISCI_DEV_MCSPI1_IO_CLKSPII_CLK
1
#define
TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT
2
#define
TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK
3
#define
TISCI_DEV_MCSPI1_IO_CLKSPIO_CLK
4
#define
TISCI_DEV_MCSPI1_VBUSP_CLK
5
#define
TISCI_DEV_MCSPI2_CLKSPIREF_CLK
0
#define
TISCI_DEV_MCSPI2_IO_CLKSPII_CLK
1
#define
TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT
2
#define
TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK
3
#define
TISCI_DEV_MCSPI2_IO_CLKSPIO_CLK
4
#define
TISCI_DEV_MCSPI2_VBUSP_CLK
5
#define
TISCI_DEV_MCU_MCSPI0_CLKSPIREF_CLK
0
#define
TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK
1
#define
TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT
2
#define
TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK
3
#define
TISCI_DEV_MCU_MCSPI0_IO_CLKSPIO_CLK
4
#define
TISCI_DEV_MCU_MCSPI0_VBUSP_CLK
5
#define
TISCI_DEV_MCU_MCSPI1_CLKSPIREF_CLK
0
#define
TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK
1
#define
TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT
2
#define
TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK
3
#define
TISCI_DEV_MCU_MCSPI1_IO_CLKSPIO_CLK
4
#define
TISCI_DEV_MCU_MCSPI1_VBUSP_CLK
5
#define
TISCI_DEV_SPINLOCK0_VCLK_CLK
0
#define
TISCI_DEV_UART0_FCLK_CLK
0
#define
TISCI_DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0
1
#define
TISCI_DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK
2
#define
TISCI_DEV_UART0_VBUSP_CLK
5
#define
TISCI_DEV_UART1_FCLK_CLK
0
#define
TISCI_DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1
1
#define
TISCI_DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK
2
#define
TISCI_DEV_UART1_VBUSP_CLK
5
#define
TISCI_DEV_UART2_FCLK_CLK
0
#define
TISCI_DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2
1
#define
TISCI_DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK
2
#define
TISCI_DEV_UART2_VBUSP_CLK
5
#define
TISCI_DEV_UART3_FCLK_CLK
0
#define
TISCI_DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3
1
#define
TISCI_DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK
2
#define
TISCI_DEV_UART3_VBUSP_CLK
5
#define
TISCI_DEV_UART4_FCLK_CLK
0
#define
TISCI_DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4
1
#define
TISCI_DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK
2
#define
TISCI_DEV_UART4_VBUSP_CLK
5
#define
TISCI_DEV_UART5_FCLK_CLK
0
#define
TISCI_DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5
1
#define
TISCI_DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK
2
#define
TISCI_DEV_UART5_VBUSP_CLK
5
#define
TISCI_DEV_UART6_FCLK_CLK
0
#define
TISCI_DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6
1
#define
TISCI_DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK
2
#define
TISCI_DEV_UART6_VBUSP_CLK
5
#define
TISCI_DEV_MCU_UART0_FCLK_CLK
0
#define
TISCI_DEV_MCU_UART0_VBUSP_CLK
3
#define
TISCI_DEV_WKUP_UART0_FCLK_CLK
0
#define
TISCI_DEV_WKUP_UART0_VBUSP_CLK
3
#define
TISCI_DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK
4
#define
TISCI_DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
5
#define
TISCI_DEV_USB0_BUS_CLK
0
#define
TISCI_DEV_USB0_CFG_CLK
1
#define
TISCI_DEV_USB0_USB2_APB_PCLK_CLK
2
#define
TISCI_DEV_USB0_USB2_REFCLOCK_CLK
3
#define
TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
4
#define
TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK
5
#define
TISCI_DEV_USB0_USB2_TAP_TCK
10
#define
TISCI_DEV_USB1_ACLK_CLK
0
#define
TISCI_DEV_USB1_CLK_LPM_CLK
1
#define
TISCI_DEV_USB1_PCLK_CLK
2
#define
TISCI_DEV_USB1_USB2_REFCLOCK_CLK
3
#define
TISCI_DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
4
#define
TISCI_DEV_USB1_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK
5
#define
TISCI_DEV_USB1_PIPE_REFCLK
6
#define
TISCI_DEV_USB1_PIPE_RXCLK
7
#define
TISCI_DEV_USB1_PIPE_RXFCLK
8
#define
TISCI_DEV_USB1_PIPE_TXCLK
9
#define
TISCI_DEV_USB1_PIPE_TXFCLK
10
#define
TISCI_DEV_USB1_PIPE_TXMCLK
11
#define
TISCI_DEV_USB1_USB2_APB_PCLK_CLK
12
#define
TISCI_DEV_USB1_USB2_TAP_TCK
17
#define
TISCI_DEV_SERDES_10G0_CLK
0
#define
TISCI_DEV_SERDES_10G0_CORE_REF_CLK
1
#define
TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
2
#define
TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
3
#define
TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK
4
#define
TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK
5
#define
TISCI_DEV_SERDES_10G0_IP1_LN0_REFCLK
7
#define
TISCI_DEV_SERDES_10G0_IP1_LN0_RXCLK
8
#define
TISCI_DEV_SERDES_10G0_IP1_LN0_RXFCLK
9
#define
TISCI_DEV_SERDES_10G0_IP1_LN0_TXCLK
10
#define
TISCI_DEV_SERDES_10G0_IP1_LN0_TXFCLK
11
#define
TISCI_DEV_SERDES_10G0_IP1_LN0_TXMCLK
12
#define
TISCI_DEV_SERDES_10G0_IP2_LN0_REFCLK
13
#define
TISCI_DEV_SERDES_10G0_IP2_LN0_RXCLK
14
#define
TISCI_DEV_SERDES_10G0_IP2_LN0_RXFCLK
15
#define
TISCI_DEV_SERDES_10G0_IP2_LN0_TXCLK
16
#define
TISCI_DEV_SERDES_10G0_IP2_LN0_TXFCLK
17
#define
TISCI_DEV_SERDES_10G0_IP2_LN0_TXMCLK
18
#define
TISCI_DEV_SERDES_10G0_TAP_TCK
40
#define
TISCI_DEV_SERDES_10G1_CLK
0
#define
TISCI_DEV_SERDES_10G1_CORE_REF_CLK
1
#define
TISCI_DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
2
#define
TISCI_DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
3
#define
TISCI_DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK
4
#define
TISCI_DEV_SERDES_10G1_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK
5
#define
TISCI_DEV_SERDES_10G1_IP1_LN0_REFCLK
7
#define
TISCI_DEV_SERDES_10G1_IP1_LN0_RXCLK
8
#define
TISCI_DEV_SERDES_10G1_IP1_LN0_RXFCLK
9
#define
TISCI_DEV_SERDES_10G1_IP1_LN0_TXCLK
10
#define
TISCI_DEV_SERDES_10G1_IP1_LN0_TXFCLK
11
#define
TISCI_DEV_SERDES_10G1_IP1_LN0_TXMCLK
12
#define
TISCI_DEV_SERDES_10G1_IP2_LN0_REFCLK
13
#define
TISCI_DEV_SERDES_10G1_IP2_LN0_RXCLK
14
#define
TISCI_DEV_SERDES_10G1_IP2_LN0_RXFCLK
15
#define
TISCI_DEV_SERDES_10G1_IP2_LN0_TXCLK
16
#define
TISCI_DEV_SERDES_10G1_IP2_LN0_TXFCLK
17
#define
TISCI_DEV_SERDES_10G1_IP2_LN0_TXMCLK
18
#define
TISCI_DEV_SERDES_10G1_TAP_TCK
40
#define
TISCI_DEV_DPHY_TX0_CLK
0
#define
TISCI_DEV_DPHY_TX0_DPHY_REF_CLK
1
#define
TISCI_DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
2
#define
TISCI_DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK
3
#define
TISCI_DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK
4
#define
TISCI_DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK
5
#define
TISCI_DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK
6
#define
TISCI_DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK
8
#define
TISCI_DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK
9
#define
TISCI_DEV_DPHY_TX0_IP3_PPI_M_TXCLKESC_CLK
11
#define
TISCI_DEV_DPHY_TX0_IP4_PPI_M_TXCLKESC_CLK
14
#define
TISCI_DEV_DPHY_TX0_PSM_CLK
16
#define
TISCI_DEV_DPHY_TX0_TAP_TCK
20
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN
0
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT
1
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT
2
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT
3
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT
4
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT
5
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT
6
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT
7
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT
8
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT
9
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT
10
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
11
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
12
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
13
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
14
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK
15
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK
16
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT
17
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN
18
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT
19
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT
20
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT
21
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT
22
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT
23
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT
24
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT
25
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT
26
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT
27
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT
28
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
29
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
30
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
31
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
32
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK
33
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK
34
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT
35
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN
36
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT
37
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT
38
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT
39
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT
40
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT
41
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT
42
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT
43
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT
44
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT
45
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT
46
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT
47
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1
48
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2
49
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3
50
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK
51
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK
52
#define
TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT
53
#define
TISCI_DEV_BOARD0_CLKOUT0_IN
54
#define
TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5
55
#define
TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10
56
#define
TISCI_DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT
61
#define
TISCI_DEV_BOARD0_DDR0_CK0_IN
62
#define
TISCI_DEV_BOARD0_EXT_REFCLK1_OUT
69
#define
TISCI_DEV_BOARD0_GPMC0_CLKLB_IN
70
#define
TISCI_DEV_BOARD0_GPMC0_CLKLB_OUT
71
#define
TISCI_DEV_BOARD0_GPMC0_CLK_IN
72
#define
TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN
73
#define
TISCI_DEV_BOARD0_I2C0_SCL_IN
74
#define
TISCI_DEV_BOARD0_I2C0_SCL_OUT
75
#define
TISCI_DEV_BOARD0_I2C1_SCL_IN
76
#define
TISCI_DEV_BOARD0_I2C1_SCL_OUT
77
#define
TISCI_DEV_BOARD0_I2C2_SCL_IN
78
#define
TISCI_DEV_BOARD0_I2C2_SCL_OUT
79
#define
TISCI_DEV_BOARD0_I2C3_SCL_IN
80
#define
TISCI_DEV_BOARD0_I2C3_SCL_OUT
81
#define
TISCI_DEV_BOARD0_I2C4_SCL_IN
82
#define
TISCI_DEV_BOARD0_I2C4_SCL_OUT
83
#define
TISCI_DEV_BOARD0_MCASP0_ACLKR_IN
85
#define
TISCI_DEV_BOARD0_MCASP0_ACLKR_OUT
86
#define
TISCI_DEV_BOARD0_MCASP0_ACLKX_IN
87
#define
TISCI_DEV_BOARD0_MCASP0_ACLKX_OUT
88
#define
TISCI_DEV_BOARD0_MCASP0_AFSR_IN
89
#define
TISCI_DEV_BOARD0_MCASP0_AFSR_OUT
90
#define
TISCI_DEV_BOARD0_MCASP0_AFSX_IN
91
#define
TISCI_DEV_BOARD0_MCASP0_AFSX_OUT
92
#define
TISCI_DEV_BOARD0_MCASP1_ACLKR_IN
93
#define
TISCI_DEV_BOARD0_MCASP1_ACLKR_OUT
94
#define
TISCI_DEV_BOARD0_MCASP1_ACLKX_IN
95
#define
TISCI_DEV_BOARD0_MCASP1_ACLKX_OUT
96
#define
TISCI_DEV_BOARD0_MCASP1_AFSR_IN
97
#define
TISCI_DEV_BOARD0_MCASP1_AFSR_OUT
98
#define
TISCI_DEV_BOARD0_MCASP1_AFSX_IN
99
#define
TISCI_DEV_BOARD0_MCASP1_AFSX_OUT
100
#define
TISCI_DEV_BOARD0_MCASP2_ACLKR_IN
101
#define
TISCI_DEV_BOARD0_MCASP2_ACLKR_OUT
102
#define
TISCI_DEV_BOARD0_MCASP2_ACLKX_IN
103
#define
TISCI_DEV_BOARD0_MCASP2_ACLKX_OUT
104
#define
TISCI_DEV_BOARD0_MCASP2_AFSR_IN
105
#define
TISCI_DEV_BOARD0_MCASP2_AFSR_OUT
106
#define
TISCI_DEV_BOARD0_MCASP2_AFSX_IN
107
#define
TISCI_DEV_BOARD0_MCASP2_AFSX_OUT
108
#define
TISCI_DEV_BOARD0_MCASP3_ACLKR_IN
109
#define
TISCI_DEV_BOARD0_MCASP3_ACLKR_OUT
110
#define
TISCI_DEV_BOARD0_MCASP3_ACLKX_IN
111
#define
TISCI_DEV_BOARD0_MCASP3_ACLKX_OUT
112
#define
TISCI_DEV_BOARD0_MCASP3_AFSR_IN
113
#define
TISCI_DEV_BOARD0_MCASP3_AFSR_OUT
114
#define
TISCI_DEV_BOARD0_MCASP3_AFSX_IN
115
#define
TISCI_DEV_BOARD0_MCASP3_AFSX_OUT
116
#define
TISCI_DEV_BOARD0_MCASP4_ACLKR_IN
117
#define
TISCI_DEV_BOARD0_MCASP4_ACLKR_OUT
118
#define
TISCI_DEV_BOARD0_MCASP4_ACLKX_IN
119
#define
TISCI_DEV_BOARD0_MCASP4_ACLKX_OUT
120
#define
TISCI_DEV_BOARD0_MCASP4_AFSR_IN
121
#define
TISCI_DEV_BOARD0_MCASP4_AFSR_OUT
122
#define
TISCI_DEV_BOARD0_MCASP4_AFSX_IN
123
#define
TISCI_DEV_BOARD0_MCASP4_AFSX_OUT
124
#define
TISCI_DEV_BOARD0_MCU_EXT_REFCLK0_OUT
125
#define
TISCI_DEV_BOARD0_MCU_I2C0_SCL_OUT
127
#define
TISCI_DEV_BOARD0_MCU_OBSCLK0_IN
128
#define
TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0
129
#define
TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
130
#define
TISCI_DEV_BOARD0_MCU_SPI0_CLK_IN
131
#define
TISCI_DEV_BOARD0_MCU_SPI0_CLK_OUT
132
#define
TISCI_DEV_BOARD0_MCU_SPI1_CLK_IN
133
#define
TISCI_DEV_BOARD0_MCU_SPI1_CLK_OUT
134
#define
TISCI_DEV_BOARD0_MCU_SYSCLKOUT0_IN
135
#define
TISCI_DEV_BOARD0_MCU_TIMER_IO0_IN
136
#define
TISCI_DEV_BOARD0_MCU_TIMER_IO1_IN
137
#define
TISCI_DEV_BOARD0_MCU_TIMER_IO2_IN
138
#define
TISCI_DEV_BOARD0_MCU_TIMER_IO3_IN
139
#define
TISCI_DEV_BOARD0_MDIO0_MDC_IN
140
#define
TISCI_DEV_BOARD0_MMC1_CLKLB_IN
143
#define
TISCI_DEV_BOARD0_MMC1_CLKLB_OUT
144
#define
TISCI_DEV_BOARD0_MMC1_CLK_IN
145
#define
TISCI_DEV_BOARD0_MMC1_CLK_OUT
146
#define
TISCI_DEV_BOARD0_MMC2_CLKLB_IN
147
#define
TISCI_DEV_BOARD0_MMC2_CLKLB_OUT
148
#define
TISCI_DEV_BOARD0_MMC2_CLK_IN
149
#define
TISCI_DEV_BOARD0_MMC2_CLK_OUT
150
#define
TISCI_DEV_BOARD0_OBSCLK0_IN
151
#define
TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0
152
#define
TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
153
#define
TISCI_DEV_BOARD0_OBSCLK1_IN
154
#define
TISCI_DEV_BOARD0_OBSCLK1_IN_PARENT_MAIN_OBSCLK_DIV_OUT0
155
#define
TISCI_DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
156
#define
TISCI_DEV_BOARD0_OSPI0_CLK_IN
157
#define
TISCI_DEV_BOARD0_OSPI0_DQS_OUT
158
#define
TISCI_DEV_BOARD0_OSPI0_LBCLKO_IN
159
#define
TISCI_DEV_BOARD0_OSPI0_LBCLKO_OUT
160
#define
TISCI_DEV_BOARD0_RGMII1_RXC_OUT
161
#define
TISCI_DEV_BOARD0_RGMII2_RXC_OUT
163
#define
TISCI_DEV_BOARD0_RMII1_REF_CLK_OUT
165
#define
TISCI_DEV_BOARD0_RMII2_REF_CLK_OUT
166
#define
TISCI_DEV_BOARD0_SPI0_CLK_IN
167
#define
TISCI_DEV_BOARD0_SPI0_CLK_OUT
168
#define
TISCI_DEV_BOARD0_SPI1_CLK_IN
169
#define
TISCI_DEV_BOARD0_SPI1_CLK_OUT
170
#define
TISCI_DEV_BOARD0_SPI2_CLK_IN
171
#define
TISCI_DEV_BOARD0_SPI2_CLK_OUT
172
#define
TISCI_DEV_BOARD0_SYSCLKOUT0_IN
173
#define
TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN
174
#define
TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0
175
#define
TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT
176
#define
TISCI_DEV_BOARD0_TCK_OUT
177
#define
TISCI_DEV_BOARD0_TIMER_IO0_IN
178
#define
TISCI_DEV_BOARD0_TIMER_IO1_IN
179
#define
TISCI_DEV_BOARD0_TIMER_IO2_IN
180
#define
TISCI_DEV_BOARD0_TIMER_IO3_IN
181
#define
TISCI_DEV_BOARD0_TIMER_IO4_IN
182
#define
TISCI_DEV_BOARD0_TIMER_IO5_IN
183
#define
TISCI_DEV_BOARD0_TIMER_IO6_IN
184
#define
TISCI_DEV_BOARD0_TIMER_IO7_IN
185
#define
TISCI_DEV_BOARD0_TRC_CLK_IN
186
#define
TISCI_DEV_BOARD0_VOUT0_EXTPCLKIN_OUT
187
#define
TISCI_DEV_BOARD0_VOUT0_PCLK_IN
188
#define
TISCI_DEV_BOARD0_VOUT0_PCLK_IN_PARENT_K3_DSS_UL_MAIN_0_DPI_1_OUT_CLK
190
#define
TISCI_DEV_BOARD0_VOUT0_PCLK_IN_PARENT_K3_DSS_UL_MAIN_1_DPI_0_OUT_CLK
191
#define
TISCI_DEV_BOARD0_VOUT0_PCLK_IN_PARENT_K3_DSS_UL_MAIN_1_DPI_1_OUT_CLK
192
#define
TISCI_DEV_BOARD0_WKUP_I2C0_SCL_OUT
194
#define
TISCI_DEV_BOARD0_CSI0_RXCLKN_OUT
195
#define
TISCI_DEV_BOARD0_CSI0_RXCLKP_OUT
196
#define
TISCI_DEV_BOARD0_CSI1_RXCLKN_OUT
197
#define
TISCI_DEV_BOARD0_CSI1_RXCLKP_OUT
198
#define
TISCI_DEV_BOARD0_CSI2_RXCLKN_OUT
199
#define
TISCI_DEV_BOARD0_CSI2_RXCLKP_OUT
200
#define
TISCI_DEV_BOARD0_CSI3_RXCLKN_OUT
201
#define
TISCI_DEV_BOARD0_CSI3_RXCLKP_OUT
202
#define
TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK
0
#define
TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
1
#define
TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8
2
#define
TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3_DUP0
3
#define
TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT
4
#define
TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK
0
#define
TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT
1
#define
TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK
2
#define
TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK
3
#define
TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK
4
#define
TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0
5
#define
TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
6
#define
TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
7
#define
TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK
0
#define
TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
1
#define
TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
2
#define
TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK
3
#define
TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK_DUP0
4
#define
TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
5
#define
TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
6
#define
TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8
7
#define
TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK
8
#define
TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0
9
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK
0
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK
1
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK
2
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
3
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1
4
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK
5
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK
6
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK8
7
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK
8
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK
9
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0
10
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT0_CLK2
11
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM67_C7XV_WRAP_MAIN_0_CLOCK_CONTROL_0_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK
12
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK
13
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM67_GPU_BXS464_WRAP_MAIN_0_GPU_DCC_CLK4
14
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK2
15
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK
16
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM67_DDR_WRAP_MAIN_0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK
17
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
18
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8
19
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0
20
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
21
#define
TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
22
#define
TISCI_DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK
0
#define
TISCI_DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK
1
#define
TISCI_DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK
2
#define
TISCI_DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK
0
#define
TISCI_DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK
1
#define
TISCI_DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK
2
#define
TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK
0
#define
TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_WKUP_CLKSEL_OUT04
2
#define
TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK
4
#define
TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
5
#define
TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0
6
#define
TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
7
#define
TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
8
#define
TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK
0
#define
TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4
2
#define
TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK
4
#define
TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
5
#define
TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0
6
#define
TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
7
#define
TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
8
#define
TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK
0
#define
TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4
2
#define
TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
3
#define
TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK
4
#define
TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
5
#define
TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0
6
#define
TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
7
#define
TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3
8
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK
0
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
3
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1
4
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK
5
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
6
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
7
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
8
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
9
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK
10
#define
TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK
11
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK
0
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
3
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1
4
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK
5
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
6
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
7
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
8
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
9
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK
10
#define
TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK
11
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK
0
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
3
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1
4
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK
5
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
6
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
7
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
8
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
9
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK
10
#define
TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK
11
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK
0
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT
1
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0
2
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0
3
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1
4
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK
5
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT
6
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT
7
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT
8
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT
9
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK
10
#define
TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK
11
#define
TISCI_DEV_DPI0_OUT_SEL_DEV_VD_CLK
0
#define
TISCI_DEV_DPI0_OUT_SEL_DEV_VD_CLK_PARENT_K3_DSS_UL_MAIN_0_DPI_1_OUT_CLK
1
#define
TISCI_DEV_DPI0_OUT_SEL_DEV_VD_CLK_PARENT_K3_DSS_UL_MAIN_1_DPI_0_OUT_CLK
2
#define
TISCI_DEV_DPI0_OUT_SEL_DEV_VD_CLK_PARENT_K3_DSS_UL_MAIN_1_DPI_1_OUT_CLK
3
source
drivers
sciclient
include
tisci
j722s
tisci_clocks.h
generated by
1.8.20