 |
J722S MCU+ SDK
09.02.00
|
|
Go to the documentation of this file.
51 #ifndef SOC_TISCI_DEVICES_H
52 #define SOC_TISCI_DEVICES_H
60 #define TISCI_DEV_DBGSUSPENDROUTER0 2U
61 #define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3U
62 #define TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5U
63 #define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0 6U
64 #define TISCI_DEV_MCU_R5FSS0 7U
65 #define TISCI_DEV_MCU_R5FSS0_CORE0 9U
66 #define TISCI_DEV_CPSW0 13U
67 #define TISCI_DEV_STM0 15U
68 #define TISCI_DEV_DCC0 16U
69 #define TISCI_DEV_DCC1 17U
70 #define TISCI_DEV_DCC2 18U
71 #define TISCI_DEV_DCC3 19U
72 #define TISCI_DEV_DCC4 20U
73 #define TISCI_DEV_DCC5 21U
74 #define TISCI_DEV_SMS0 22U
75 #define TISCI_DEV_MCU_DCC0 23U
76 #define TISCI_DEV_DEBUGSS_WRAP0 24U
77 #define TISCI_DEV_DMASS0 25U
78 #define TISCI_DEV_DMASS0_BCDMA_0 26U
79 #define TISCI_DEV_DMASS0_CBASS_0 27U
80 #define TISCI_DEV_DMASS0_INTAGGR_0 28U
81 #define TISCI_DEV_DMASS0_IPCSS_0 29U
82 #define TISCI_DEV_DMASS0_PKTDMA_0 30U
83 #define TISCI_DEV_DMASS0_RINGACC_0 33U
84 #define TISCI_DEV_MCU_TIMER0 35U
85 #define TISCI_DEV_TIMER0 36U
86 #define TISCI_DEV_TIMER1 37U
87 #define TISCI_DEV_TIMER2 38U
88 #define TISCI_DEV_TIMER3 39U
89 #define TISCI_DEV_TIMER4 40U
90 #define TISCI_DEV_TIMER5 41U
91 #define TISCI_DEV_TIMER6 42U
92 #define TISCI_DEV_TIMER7 43U
93 #define TISCI_DEV_MCU_TIMER1 48U
94 #define TISCI_DEV_MCU_TIMER2 49U
95 #define TISCI_DEV_MCU_TIMER3 50U
96 #define TISCI_DEV_ECAP0 51U
97 #define TISCI_DEV_ECAP1 52U
98 #define TISCI_DEV_ECAP2 53U
99 #define TISCI_DEV_ELM0 54U
100 #define TISCI_DEV_MAIN_EMIF_DATA_ISO_VD 55U
101 #define TISCI_DEV_MMCSD0 57U
102 #define TISCI_DEV_MMCSD1 58U
103 #define TISCI_DEV_EQEP0 59U
104 #define TISCI_DEV_EQEP1 60U
105 #define TISCI_DEV_WKUP_GTC0 61U
106 #define TISCI_DEV_EQEP2 62U
107 #define TISCI_DEV_ESM0 63U
108 #define TISCI_DEV_WKUP_ESM0 64U
109 #define TISCI_DEV_FSS0 73U
110 #define TISCI_DEV_FSS0_FSAS_0 74U
111 #define TISCI_DEV_FSS0_OSPI_0 75U
112 #define TISCI_DEV_GICSS0 76U
113 #define TISCI_DEV_GPIO0 77U
114 #define TISCI_DEV_GPIO1 78U
115 #define TISCI_DEV_MCU_GPIO0 79U
116 #define TISCI_DEV_GPMC0 80U
117 #define TISCI_DEV_LED0 83U
118 #define TISCI_DEV_DDPA0 85U
119 #define TISCI_DEV_EPWM0 86U
120 #define TISCI_DEV_EPWM1 87U
121 #define TISCI_DEV_EPWM2 88U
122 #define TISCI_DEV_WKUP_VTM0 95U
123 #define TISCI_DEV_MAILBOX0 96U
124 #define TISCI_DEV_MAIN2MCU_VD 97U
125 #define TISCI_DEV_MCAN0 98U
126 #define TISCI_DEV_MCAN1 99U
127 #define TISCI_DEV_MCU_MCRC64_0 100U
128 #define TISCI_DEV_I2C0 102U
129 #define TISCI_DEV_I2C1 103U
130 #define TISCI_DEV_I2C2 104U
131 #define TISCI_DEV_I2C3 105U
132 #define TISCI_DEV_MCU_I2C0 106U
133 #define TISCI_DEV_WKUP_I2C0 107U
134 #define TISCI_DEV_WKUP_TIMER0 110U
135 #define TISCI_DEV_WKUP_TIMER1 111U
136 #define TISCI_DEV_WKUP_UART0 114U
137 #define TISCI_DEV_MCRC64_0 116U
138 #define TISCI_DEV_WKUP_RTCSS0 117U
139 #define TISCI_DEV_WKUP_R5FSS0_SS0 118U
140 #define TISCI_DEV_WKUP_R5FSS0 119U
141 #define TISCI_DEV_WKUP_R5FSS0_CORE0 121U
142 #define TISCI_DEV_RTI0 125U
143 #define TISCI_DEV_RTI1 126U
144 #define TISCI_DEV_RTI2 127U
145 #define TISCI_DEV_RTI3 128U
146 #define TISCI_DEV_RTI15 130U
147 #define TISCI_DEV_MCU_RTI0 131U
148 #define TISCI_DEV_WKUP_RTI0 132U
149 #define TISCI_DEV_COMPUTE_CLUSTER0 134U
150 #define TISCI_DEV_A53SS0_CORE_0 135U
151 #define TISCI_DEV_A53SS0_CORE_1 136U
152 #define TISCI_DEV_A53SS0_CORE_2 137U
153 #define TISCI_DEV_A53SS0_CORE_3 138U
154 #define TISCI_DEV_PSCSS0 139U
155 #define TISCI_DEV_WKUP_PSC0 140U
156 #define TISCI_DEV_MCSPI0 141U
157 #define TISCI_DEV_MCSPI1 142U
158 #define TISCI_DEV_MCSPI2 143U
159 #define TISCI_DEV_UART0 146U
160 #define TISCI_DEV_MCU_MCSPI0 147U
161 #define TISCI_DEV_MCU_MCSPI1 148U
162 #define TISCI_DEV_MCU_UART0 149U
163 #define TISCI_DEV_SPINLOCK0 150U
164 #define TISCI_DEV_UART1 152U
165 #define TISCI_DEV_UART2 153U
166 #define TISCI_DEV_UART3 154U
167 #define TISCI_DEV_UART4 155U
168 #define TISCI_DEV_UART5 156U
169 #define TISCI_DEV_BOARD0 157U
170 #define TISCI_DEV_UART6 158U
171 #define TISCI_DEV_USB0 161U
172 #define TISCI_DEV_PBIST0 163U
173 #define TISCI_DEV_WKUP_PBIST0 165U
174 #define TISCI_DEV_A53SS0 166U
175 #define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0 167U
176 #define TISCI_DEV_PSC0_FW_0 168U
177 #define TISCI_DEV_PSC0 169U
178 #define TISCI_DEV_DDR32SS0 170U
179 #define TISCI_DEV_DEBUGSS0 171U
180 #define TISCI_DEV_A53_RS_BW_LIMITER0 172U
181 #define TISCI_DEV_A53_WS_BW_LIMITER1 173U
182 #define TISCI_DEV_GPU_RS_BW_LIMITER9 174U
183 #define TISCI_DEV_GPU_WS_BW_LIMITER10 175U
184 #define TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0 176U
185 #define TISCI_DEV_MAIN_EMIF_CFG_ISO_VD 177U
186 #define TISCI_DEV_MAIN_USB0_ISO_VD 178U
187 #define TISCI_DEV_MAIN_USB2_ISO_VD 179U
188 #define TISCI_DEV_MCU_MCU_16FF0 180U
189 #define TISCI_DEV_CSI_RX_IF0 182U
190 #define TISCI_DEV_DCC6 183U
191 #define TISCI_DEV_MMCSD2 184U
192 #define TISCI_DEV_DPHY_RX0 185U
193 #define TISCI_DEV_DSS0 186U
194 #define TISCI_DEV_MCU_MCAN0 188U
195 #define TISCI_DEV_MCU_MCAN1 189U
196 #define TISCI_DEV_MCASP0 190U
197 #define TISCI_DEV_MCASP1 191U
198 #define TISCI_DEV_MCASP2 192U
199 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD 193U
200 #define TISCI_DEV_CPT2_AGGR1 194U
201 #define TISCI_DEV_CPT2_AGGR0 195U
202 #define TISCI_DEV_MCU_CPT2_AGGR0 196U
203 #define TISCI_DEV_MCU_DCC1 197U
204 #define TISCI_DEV_DMASS1 198U
205 #define TISCI_DEV_DMASS1_BCDMA_0 199U
206 #define TISCI_DEV_DMASS1_INTAGGR_0 200U
207 #define TISCI_DEV_JPGENC0 201U
208 #define TISCI_DEV_WKUP_PBIST1 202U
209 #define TISCI_DEV_MCU_PBIST0 203U
210 #define TISCI_DEV_CODEC0 204U
211 #define TISCI_DEV_RTI4 205U
212 #define TISCI_DEV_C7XV_RSWS_BS_LIMITER6 206U
213 #define TISCI_DEV_C7X256V0 207U
214 #define TISCI_DEV_C7X256V0_C7XV_CORE_0 208U
215 #define TISCI_DEV_C7X256V0_CORE0 209U
216 #define TISCI_DEV_C7X256V0_CLEC 210U
217 #define TISCI_DEV_C7X256V0_CLK 211U
218 #define TISCI_DEV_C7X256V0_DEBUG 212U
219 #define TISCI_DEV_C7X256V0_GICSS 213U
220 #define TISCI_DEV_C7X256V0_PBIST 214U
221 #define TISCI_DEV_JPGENC_RS_BW_LIMITER4 215U
222 #define TISCI_DEV_JPGENC_WS_BW_LIMITER5 216U
223 #define TISCI_DEV_VPAC_RSWS_BW_LIMITER8 217U
224 #define TISCI_DEV_VPAC_RSWS_BW_LIMITER7 218U
225 #define TISCI_DEV_VPAC0 219U
226 #define TISCI_DEV_PBIST3 220U
227 #define TISCI_DEV_CODEC_RS_BW_LIMITER2 221U
228 #define TISCI_DEV_CODEC_WS_BW_LIMITER3 222U
229 #define TISCI_DEV_HSM0 225U
230 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD 226U
231 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD 227U
232 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD 228U
233 #define TISCI_DEV_DCC7 229U
234 #define TISCI_DEV_DCC8 230U
235 #define TISCI_DEV_DSS_DSI0 231U
236 #define TISCI_DEV_DSS1 232U
237 #define TISCI_DEV_PBIST1 233U
238 #define TISCI_DEV_OLDI_TX_CORE0 234U
239 #define TISCI_DEV_OLDI_TX_CORE1 235U
240 #define TISCI_DEV_GPU0 237U
241 #define TISCI_DEV_DPHY_TX0 238U
242 #define TISCI_DEV_DSS1_DPI1_PLLSEL_DEV_VD 240U
243 #define TISCI_DEV_DSS1_DPI0_PLLSEL_DEV_VD 241U
244 #define TISCI_DEV_GPU0_CORE_VD 242U
245 #define TISCI_DEV_OLDI0_VD 243U
246 #define TISCI_DEV_OLDI1_VD 244U
247 #define TISCI_DEV_DPI0_OUT_SEL_DEV_VD 245U
248 #define TISCI_DEV_ATL0 246U
249 #define TISCI_DEV_CSI_RX_IF1 247U
250 #define TISCI_DEV_CSI_RX_IF2 248U
251 #define TISCI_DEV_CSI_RX_IF3 249U
252 #define TISCI_DEV_CSI_TX_IF0 250U
253 #define TISCI_DEV_DPHY_RX1 251U
254 #define TISCI_DEV_DPHY_RX2 252U
255 #define TISCI_DEV_DPHY_RX3 253U
256 #define TISCI_DEV_PBIST2 254U
257 #define TISCI_DEV_MCASP3 255U
258 #define TISCI_DEV_MCASP4 256U
259 #define TISCI_DEV_I2C4 257U
260 #define TISCI_DEV_MSRAM8KX256E0 258U
261 #define TISCI_DEV_PCIE0 259U
262 #define TISCI_DEV_R5FSS0_SS0 260U
263 #define TISCI_DEV_R5FSS0 261U
264 #define TISCI_DEV_R5FSS0_CORE0 262U
265 #define TISCI_DEV_RTI5 263U
266 #define TISCI_DEV_RTI8 264U
267 #define TISCI_DEV_COMPUTE_CLUSTER0_CLKDIV_0 265U
268 #define TISCI_DEV_C7XV_RSWS_BS_LIMITER11 266U
269 #define TISCI_DEV_C7X256V1 267U
270 #define TISCI_DEV_C7X256V1_C7XV_CORE_0 268U
271 #define TISCI_DEV_C7X256V1_CORE0 269U
272 #define TISCI_DEV_C7X256V1_CLEC 270U
273 #define TISCI_DEV_C7X256V1_CLK 271U
274 #define TISCI_DEV_C7X256V1_DEBUG 272U
275 #define TISCI_DEV_C7X256V1_GICSS 273U
276 #define TISCI_DEV_C7X256V1_PBIST 274U
277 #define TISCI_DEV_CTI0 275U
278 #define TISCI_DEV_CTI1 276U
279 #define TISCI_DEV_DMPAC0 277U
280 #define TISCI_DEV_USB1 278U
281 #define TISCI_DEV_SERDES_10G0 279U
282 #define TISCI_DEV_SERDES_10G1 280U
283 #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD 281U
284 #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD 282U
285 #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD 283U
286 #define TISCI_DEV_TIMER1_CLKSEL_VD 284U
287 #define TISCI_DEV_TIMER3_CLKSEL_VD 285U
288 #define TISCI_DEV_TIMER5_CLKSEL_VD 286U
289 #define TISCI_DEV_TIMER7_CLKSEL_VD 287U