J722S MCU+ SDK  09.02.00
sdl_arm_r5_pmu.h
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1 /*
2  * Copyright (C) 2021-24 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
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8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
46 #ifndef SDL_ARM_R5_PMU_H
47 #define SDL_ARM_R5_PMU_H
48 
49 #include <stdint.h>
50 
51 #ifdef __cplusplus
52 extern "C" {
53 #endif
54 
71 /* ========================================================================== */
72 /* Structures and Enums */
73 /* ========================================================================== */
74 
95 typedef enum
96 {
165 
180 typedef struct SDL_PMU_staticReg_read
181 {
182  uint8_t cycleCntDiv;
184  uint8_t exportEvents;
186  uint8_t userEnable;
188  uint32_t cntEnableSetReg;
191 
192 /* @} */
193 
199 #define SDL_ARM_R5_PMU_CYCLE_COUNTER_NUM (31U)
200 
202 #define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_MASK (0x000000FFU)
203 #define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_SHIFT (0x00000000U)
204 #define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_RESETVAL (0x00000000U)
205 #define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_MAX (0x000000FFU)
206 
239 extern void SDL_R5PMU_cfg( uint32_t cycleCntDiv, uint32_t exportEvents, uint32_t userEnable );
240 
262 extern int32_t SDL_R5PMU_verifyCfg(uint32_t cycleCntDiv, uint32_t exportEvents);
263 
275 extern void SDL_R5PMU_enableAllCntrs( uint32_t enable );
276 
285 extern uint32_t SDL_R5PMU_getNumCntrs( void );
286 
297 extern void SDL_R5PMU_cfgCntr( uint32_t cntrNum, SDL_R5PmuEventType eventType );
298 
310 extern void SDL_R5PMU_enableCntrOverflowIntr(uint32_t cntrNum, uint32_t enable );
311 
324 extern void SDL_R5PMU_enableCntr(uint32_t cntrNum, uint32_t enable );
325 
336 extern uint32_t SDL_R5PMU_readCntr(uint32_t cntrNum );
337 
348 extern void SDL_R5PMU_setResetCntr(uint32_t cntrNum, uint32_t cntrVal);
349 
360 extern uint32_t SDL_R5PMU_readCntrOverflowStatus( void );
361 
375 extern void SDL_R5PMU_clearCntrOverflowStatus( uint32_t cntrMask );
376 
384 extern void SDL_R5PMU_resetCycleCnt(void);
385 
393 extern void SDL_R5PMU_resetCntrs(void);
394 
407 
410 #ifdef __cplusplus
411 }
412 #endif
413 #endif /* end of SDL_ARM_R5_PMU_H_ definition */
SDL_ARM_R5_PMU_EVENT_TYPE_PROC_RET
@ SDL_ARM_R5_PMU_EVENT_TYPE_PROC_RET
Definition: sdl_arm_r5_pmu.h:110
SDL_R5PMU_setResetCntr
void SDL_R5PMU_setResetCntr(uint32_t cntrNum, uint32_t cntrVal)
Set a PMU counter.
SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_PF
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_PF
Definition: sdl_arm_r5_pmu.h:128
SDL_ARM_R5_PMU_EVENT_TYPE_PI_X
@ SDL_ARM_R5_PMU_EVENT_TYPE_PI_X
Definition: sdl_arm_r5_pmu.h:104
SDL_ARM_R5_PMU_EVENT_TYPE_ATCM_MB_ECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_ATCM_MB_ECC
Definition: sdl_arm_r5_pmu.h:147
SDL_ARM_R5_PMU_EVENT_TYPE_FIQ_DISABLED_CYCLES
@ SDL_ARM_R5_PMU_EVENT_TYPE_FIQ_DISABLED_CYCLES
Definition: sdl_arm_r5_pmu.h:120
SDL_ARM_R5_PMU_EVENT_TYPE_D_WR
@ SDL_ARM_R5_PMU_EVENT_TYPE_D_WR
Definition: sdl_arm_r5_pmu.h:102
SDL_ARM_R5_PMU_EVENT_TYPE_B1TCM_SB_ECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_B1TCM_SB_ECC
Definition: sdl_arm_r5_pmu.h:152
SDL_ARM_R5_PMU_EVENT_TYPE_ETMEXTOUTM0
@ SDL_ARM_R5_PMU_EVENT_TYPE_ETMEXTOUTM0
Definition: sdl_arm_r5_pmu.h:122
SDL_R5PmuEventType
SDL_R5PmuEventType
This enumerator defines PMU event types.
Definition: sdl_arm_r5_pmu.h:96
SDL_PMU_staticRegs
PMU Static Registers structure.
Definition: sdl_arm_r5_pmu.h:181
SDL_ARM_R5_PMU_EVENT_TYPE_B0TCM_MB_ECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_B0TCM_MB_ECC
Definition: sdl_arm_r5_pmu.h:148
SDL_PMU_staticRegs::exportEvents
uint8_t exportEvents
Definition: sdl_arm_r5_pmu.h:184
SDL_R5PMU_readCntr
uint32_t SDL_R5PMU_readCntr(uint32_t cntrNum)
Read a PMU counter.
SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_MISS
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_MISS
Definition: sdl_arm_r5_pmu.h:98
SDL_ARM_R5_PMU_EVENT_TYPE_BRANCH_PRED
@ SDL_ARM_R5_PMU_EVENT_TYPE_BRANCH_PRED
Definition: sdl_arm_r5_pmu.h:113
SDL_ARM_R5_PMU_EVENT_TYPE_CORRECTABLE_BUS_FAULTS
@ SDL_ARM_R5_PMU_EVENT_TYPE_CORRECTABLE_BUS_FAULTS
Definition: sdl_arm_r5_pmu.h:159
SDL_ARM_R5_PMU_EVENT_TYPE_SWINC
@ SDL_ARM_R5_PMU_EVENT_TYPE_SWINC
Definition: sdl_arm_r5_pmu.h:97
SDL_ARM_R5_PMU_EVENT_TYPE_ACP_DCACHE_ACCESS
@ SDL_ARM_R5_PMU_EVENT_TYPE_ACP_DCACHE_ACCESS
Definition: sdl_arm_r5_pmu.h:161
SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_TAG_CECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_TAG_CECC
Definition: sdl_arm_r5_pmu.h:126
SDL_ARM_R5_PMU_EVENT_TYPE_INT_DIV
@ SDL_ARM_R5_PMU_EVENT_TYPE_INT_DIV
Definition: sdl_arm_r5_pmu.h:133
SDL_ARM_R5_PMU_EVENT_TYPE_CID_CHANGE
@ SDL_ARM_R5_PMU_EVENT_TYPE_CID_CHANGE
Definition: sdl_arm_r5_pmu.h:107
SDL_R5PMU_getNumCntrs
uint32_t SDL_R5PMU_getNumCntrs(void)
Get the number of PMU counters supported.
SDL_ARM_R5_PMU_EVENT_TYPE_IRQ_DISABLED_CYCLES
@ SDL_ARM_R5_PMU_EVENT_TYPE_IRQ_DISABLED_CYCLES
Definition: sdl_arm_r5_pmu.h:121
SDL_PMU_staticRegs::userEnable
uint8_t userEnable
Definition: sdl_arm_r5_pmu.h:186
SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_PF
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_PF
Definition: sdl_arm_r5_pmu.h:154
SDL_R5PMU_resetCycleCnt
void SDL_R5PMU_resetCycleCnt(void)
Reset the cycle counter to zero.
SDL_ARM_R5_PMU_EVENT_TYPE_PLD_LINEFILL
@ SDL_ARM_R5_PMU_EVENT_TYPE_PLD_LINEFILL
Definition: sdl_arm_r5_pmu.h:135
SDL_ARM_R5_PMU_EVENT_TYPE_PLD_NO_LINEFILL
@ SDL_ARM_R5_PMU_EVENT_TYPE_PLD_NO_LINEFILL
Definition: sdl_arm_r5_pmu.h:136
SDL_ARM_R5_PMU_EVENT_TYPE_ACP_DCACHE_INVALIDATE
@ SDL_ARM_R5_PMU_EVENT_TYPE_ACP_DCACHE_INVALIDATE
Definition: sdl_arm_r5_pmu.h:162
SDL_PMU_staticRegs::cycleCntDiv
uint8_t cycleCntDiv
Definition: sdl_arm_r5_pmu.h:182
SDL_ARM_R5_PMU_EVENT_TYPE_LIVELOCK
@ SDL_ARM_R5_PMU_EVENT_TYPE_LIVELOCK
Definition: sdl_arm_r5_pmu.h:146
SDL_ARM_R5_PMU_EVENT_TYPE_D_RD
@ SDL_ARM_R5_PMU_EVENT_TYPE_D_RD
Definition: sdl_arm_r5_pmu.h:101
SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_STALL
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_STALL
Definition: sdl_arm_r5_pmu.h:114
SDL_R5PMU_enableCntrOverflowIntr
void SDL_R5PMU_enableCntrOverflowIntr(uint32_t cntrNum, uint32_t enable)
Enable/disable overflow interrupt generation for a PMU counter.
SDL_ARM_R5_PMU_EVENT_TYPE_SB_ATTR
@ SDL_ARM_R5_PMU_EVENT_TYPE_SB_ATTR
Definition: sdl_arm_r5_pmu.h:139
SDL_R5PMU_verifyCfg
int32_t SDL_R5PMU_verifyCfg(uint32_t cycleCntDiv, uint32_t exportEvents)
Configure the Performance Management Unit (PMU)
SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_ACCESS
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_ACCESS
Definition: sdl_arm_r5_pmu.h:138
SDL_ARM_R5_PMU_EVENT_TYPE_SW_PC
@ SDL_ARM_R5_PMU_EVENT_TYPE_SW_PC
Definition: sdl_arm_r5_pmu.h:108
SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_LS
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_LS
Definition: sdl_arm_r5_pmu.h:129
SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_A
@ SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_A
Definition: sdl_arm_r5_pmu.h:140
SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_WB
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_WB
Definition: sdl_arm_r5_pmu.h:116
SDL_R5PMU_cfg
void SDL_R5PMU_cfg(uint32_t cycleCntDiv, uint32_t exportEvents, uint32_t userEnable)
Configure the Performance Management Unit (PMU)
SDL_R5PMU_clearCntrOverflowStatus
void SDL_R5PMU_clearCntrOverflowStatus(uint32_t cntrMask)
Clear the overflow flag for the specified counter(s)
SDL_ARM_R5_PMU_EVENT_TYPE_BRANCH_TAKEN
@ SDL_ARM_R5_PMU_EVENT_TYPE_BRANCH_TAKEN
Definition: sdl_arm_r5_pmu.h:112
SDL_ARM_R5_PMU_EVENT_TYPE_INT_DIV_STALL
@ SDL_ARM_R5_PMU_EVENT_TYPE_INT_DIV_STALL
Definition: sdl_arm_r5_pmu.h:134
SDL_ARM_R5_PMU_EVENT_TYPE_CORRECTABLE_EVENTS
@ SDL_ARM_R5_PMU_EVENT_TYPE_CORRECTABLE_EVENTS
Definition: sdl_arm_r5_pmu.h:157
SDL_ARM_R5_PMU_EVENT_TYPE_FATAL_BUS_FAULTS
@ SDL_ARM_R5_PMU_EVENT_TYPE_FATAL_BUS_FAULTS
Definition: sdl_arm_r5_pmu.h:160
SDL_ARM_R5_PMU_EVENT_TYPE_SB_DRAIN
@ SDL_ARM_R5_PMU_EVENT_TYPE_SB_DRAIN
Definition: sdl_arm_r5_pmu.h:119
SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_LS
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_LS
Definition: sdl_arm_r5_pmu.h:153
SDL_ARM_R5_PMU_EVENT_TYPE_EXCEPTION_RET
@ SDL_ARM_R5_PMU_EVENT_TYPE_EXCEPTION_RET
Definition: sdl_arm_r5_pmu.h:106
SDL_ARM_R5_PMU_EVENT_TYPE_UNALIGNED_ACCESS
@ SDL_ARM_R5_PMU_EVENT_TYPE_UNALIGNED_ACCESS
Definition: sdl_arm_r5_pmu.h:111
SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_TAG_CECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_TAG_CECC
Definition: sdl_arm_r5_pmu.h:124
SDL_ARM_R5_PMU_EVENT_TYPE_LSU_QF_STALL
@ SDL_ARM_R5_PMU_EVENT_TYPE_LSU_QF_STALL
Definition: sdl_arm_r5_pmu.h:132
SDL_R5PMU_cfgCntr
void SDL_R5PMU_cfgCntr(uint32_t cntrNum, SDL_R5PmuEventType eventType)
Configure a PMU counter.
SDL_ARM_R5_PMU_EVENT_TYPE_CYCLE_CNT
@ SDL_ARM_R5_PMU_EVENT_TYPE_CYCLE_CNT
Definition: sdl_arm_r5_pmu.h:163
SDL_ARM_R5_PMU_EVENT_TYPE_DOUBLE_FP
@ SDL_ARM_R5_PMU_EVENT_TYPE_DOUBLE_FP
Definition: sdl_arm_r5_pmu.h:143
SDL_PMU_staticRegs::cntEnableSetReg
uint32_t cntEnableSetReg
Definition: sdl_arm_r5_pmu.h:188
SDL_ARM_R5_PMU_EVENT_TYPE_B0TCM_SB_ECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_B0TCM_SB_ECC
Definition: sdl_arm_r5_pmu.h:151
SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_B
@ SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_B
Definition: sdl_arm_r5_pmu.h:141
SDL_ARM_R5_PMU_EVENT_TYPE_LSU_BUSY_STALL
@ SDL_ARM_R5_PMU_EVENT_TYPE_LSU_BUSY_STALL
Definition: sdl_arm_r5_pmu.h:118
SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_ACCESS
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_ACCESS
Definition: sdl_arm_r5_pmu.h:100
SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_DATA_FECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_DATA_FECC
Definition: sdl_arm_r5_pmu.h:144
SDL_ARM_R5_PMU_EVENT_TYPE_ATCM_SB_ECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_ATCM_SB_ECC
Definition: sdl_arm_r5_pmu.h:150
SDL_ARM_R5_PMU_EVENT_TYPE_B_IMMEDIATE
@ SDL_ARM_R5_PMU_EVENT_TYPE_B_IMMEDIATE
Definition: sdl_arm_r5_pmu.h:109
SDL_ARM_R5_PMU_EVENT_TYPE_ETMEXTOUTM1
@ SDL_ARM_R5_PMU_EVENT_TYPE_ETMEXTOUTM1
Definition: sdl_arm_r5_pmu.h:123
SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_TAG_FECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_TAG_FECC
Definition: sdl_arm_r5_pmu.h:145
SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_OTHER
@ SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_OTHER
Definition: sdl_arm_r5_pmu.h:142
SDL_ARM_R5_PMU_EVENT_TYPE_SB_MERGE
@ SDL_ARM_R5_PMU_EVENT_TYPE_SB_MERGE
Definition: sdl_arm_r5_pmu.h:130
SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_DATA_CECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_DATA_CECC
Definition: sdl_arm_r5_pmu.h:125
SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_MISS
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_MISS
Definition: sdl_arm_r5_pmu.h:99
SDL_R5PMU_enableCntr
void SDL_R5PMU_enableCntr(uint32_t cntrNum, uint32_t enable)
Enable/disable a PMU counter.
SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_AXI
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_AXI
Definition: sdl_arm_r5_pmu.h:156
SDL_R5PMU_enableAllCntrs
void SDL_R5PMU_enableAllCntrs(uint32_t enable)
Enable/disable all PMU counters.
SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_DATA_CECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_DATA_CECC
Definition: sdl_arm_r5_pmu.h:127
SDL_ARM_R5_PMU_EVENT_TYPE_B1TCM_MB_ECC
@ SDL_ARM_R5_PMU_EVENT_TYPE_B1TCM_MB_ECC
Definition: sdl_arm_r5_pmu.h:149
SDL_ARM_R5_PMU_EVENT_TYPE_LSU_SB_STALL
@ SDL_ARM_R5_PMU_EVENT_TYPE_LSU_SB_STALL
Definition: sdl_arm_r5_pmu.h:131
SDL_ARM_R5_PMU_EVENT_TYPE_I_X
@ SDL_ARM_R5_PMU_EVENT_TYPE_I_X
Definition: sdl_arm_r5_pmu.h:103
SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_STALL
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_STALL
Definition: sdl_arm_r5_pmu.h:115
SDL_ARM_R5_PMU_EVENT_TYPE_FATAL_EVENTS
@ SDL_ARM_R5_PMU_EVENT_TYPE_FATAL_EVENTS
Definition: sdl_arm_r5_pmu.h:158
SDL_ARM_R5_PMU_EVENT_TYPE_NONCACHEABLE_ACCESS
@ SDL_ARM_R5_PMU_EVENT_TYPE_NONCACHEABLE_ACCESS
Definition: sdl_arm_r5_pmu.h:137
SDL_ARM_R5_PMU_EVENT_TYPE_EXCEPTION
@ SDL_ARM_R5_PMU_EVENT_TYPE_EXCEPTION
Definition: sdl_arm_r5_pmu.h:105
SDL_R5PMU_resetCntrs
void SDL_R5PMU_resetCntrs(void)
Reset all counters to zero.
SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_AXI
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_AXI
Definition: sdl_arm_r5_pmu.h:155
SDL_R5PMU_readStaticRegisters
void SDL_R5PMU_readStaticRegisters(SDL_PMU_staticRegs *pStaticRegs)
PMU API to Read the Static Registers. This function reads the values of the static registers such as ...
SDL_ARM_R5_PMU_EVENT_TYPE_MEM_REQ
@ SDL_ARM_R5_PMU_EVENT_TYPE_MEM_REQ
Definition: sdl_arm_r5_pmu.h:117
SDL_R5PMU_readCntrOverflowStatus
uint32_t SDL_R5PMU_readCntrOverflowStatus(void)
Read the overflow status for all of the counters.