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Data Structures | |
struct | CacheP_Config |
Cache config structure, this used by SysConfig and not to be used by end-users directly. More... | |
Macros | |
#define | CacheP_CACHELINE_ALIGNMENT (128U) |
Cache line size for alignment of buffers. Actual CPU defined cache line can be smaller that this value, this define is a utility macro to keep application portable across different CPU's. More... | |
Cache Type | |
#define | CacheP_TYPE_L1P (0x0001u) |
#define | CacheP_TYPE_L1D (0x0002u) |
#define | CacheP_TYPE_L2P (0x0004u) |
#define | CacheP_TYPE_L2D (0x0008u) |
#define | CacheP_TYPE_L1 ((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D)) |
#define | CacheP_TYPE_L2 ((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D)) |
#define | CacheP_TYPE_ALLP ((CacheP_TYPE_L1P)|(CacheP_TYPE_L2P)) |
#define | CacheP_TYPE_ALLD ((CacheP_TYPE_L1D)|(CacheP_TYPE_L2D)) |
#define | CacheP_TYPE_ALL (((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D))|((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D))) |
Functions | |
void | CacheP_enable (uint32_t type) |
Cache enable. More... | |
void | CacheP_disable (uint32_t type) |
Cache disable. More... | |
uint32_t | CacheP_getEnabled (void) |
Get cache enabled bits. More... | |
void | CacheP_wbAll (uint32_t type) |
Cache writeback for full cache. More... | |
void | CacheP_wbInvAll (uint32_t type) |
Cache writeback and invalidate for full cache. More... | |
void | CacheP_wb (void *addr, uint32_t size, uint32_t type) |
Cache writeback for a specified region. More... | |
void | CacheP_inv (void *addr, uint32_t size, uint32_t type) |
Cache invalidate for a specified region. More... | |
void | CacheP_wbInv (void *addr, uint32_t size, uint32_t type) |
Cache writeback and invalidate for a specified region. More... | |
void | CacheP_init (void) |
Initialize Cache sub-system, called by SysConfig, not to be called by end users. More... | |
void | CacheP_invL1dAll () |
Invalidates all in data cache. More... | |
void | CacheP_invL1pAll () |
Invalidates all in instruction cache. More... | |
uint32_t | CacheP_armR5GetIcacheLineSize (void) |
Get the instruction cache line size This function is used to get the instruction cache line size for MCU. Implementation of this API/code is use-case specific. More... | |
void | CacheP_armR5InvalidateIcacheMva (uint32_t address) |
Invalidate an instruction cache line by MVA This function is used to invalidate an instruction cache Line by MVA. More... | |
void | CacheP_armR5InvalidateDcacheSetWay (uint32_t set, uint32_t way) |
Invalidate a data cache line by set and way. More... | |
void | CacheP_armR5CleanDcacheSetWay (uint32_t set, uint32_t way) |
Clean a data cache line by set and way. More... | |
void | CacheP_armR5CleanInvalidateDcacheSetWay (uint32_t set, uint32_t way) |
Clean and invalidate a data cache line by set and way. More... | |
void | CacheP_armR5DisableEcc (void) |
Disable ECC (parity) checking on cache rams. More... | |
void | CacheP_armR5EnableAxiAccess (void) |
Enable AXI slave access to cache RAM. More... | |
Variables | |
CacheP_Config | gCacheConfig |
Externally defined Cache configuration. More... | |