J722S MCU+ SDK  09.02.00
sciclient_irq_rm.c File Reference

Introduction

irq_tree for J722S

Variables

static struct Sciclient_rmIaUsedMapping rom_usage_DMASS0_INTAGGR_0 [1U]
 
uint8_t vint_usage_count_DMASS0_INTAGGR_0 [184U] = {0}
 
static struct Sciclient_rmIaUsedMapping rom_usage_DMASS1_INTAGGR_0 [1U]
 
uint8_t vint_usage_count_DMASS1_INTAGGR_0 [40] = {0}
 
struct Sciclient_rmIaInst gRmIaInstances [SCICLIENT_RM_IA_NUM_INST]
 
struct Sciclient_rmIrInst gRmIrInstances [SCICLIENT_RM_IR_NUM_INST]
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_WKUP_R5FSS0_CORE0_intr_32_47
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_32_47
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V1_CLEC_gic_spi_32_47
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_7_to_HSM0_nvic_208_215
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_20_21_to_R5FSS0_CORE0_intr_56_57
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_32_33_to_R5FSS0_CORE0_intr_58_59
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_16_19_to_R5FSS0_CORE0_intr_104_107
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_22_23_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_34_35_to_MCU_R5FSS0_CORE0_cpu0_intr_32_33
 
const struct Sciclient_rmIrqIf *const tisci_if_MAIN_GPIOMUX_INTROUTER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MAIN_GPIOMUX_INTROUTER0
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_WKUP_R5FSS0_CORE0_intr_104_107
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_104_107
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V1_CLEC_gic_spi_104_107
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_R5FSS0_CORE0_cpu0_intr_104_107
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_HSM0_nvic_78_81
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_12_13_to_R5FSS0_CORE0_intr_32_33
 
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_14_15_to_R5FSS0_CORE0_intr_60_61
 
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_MCU_GPIOMUX_INTROUTER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_WKUP_MCU_GPIOMUX_INTROUTER0
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PCIE0_pcie_cpts_hw2_push_0_0
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_CPSW0_cpts_hw1_push_0_0
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_CPSW0_cpts_hw2_push_1_1
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_CPSW0_cpts_hw3_push_2_2
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_CPSW0_cpts_hw4_push_3_3
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_CPSW0_cpts_hw5_push_4_4
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_CPSW0_cpts_hw6_push_5_5
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPSW0_cpts_hw7_push_6_6
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPSW0_cpts_hw8_push_7_7
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMESYNC_EVENT_INTROUTER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_EVENT_INTROUTER0
 
const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_0
 
const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
 
const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
 
const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
 
const struct Sciclient_rmIrqIf *const tisci_if_CPSW0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CPSW0
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V0_CLEC_gic_spi_64_103
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_16_31
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V1_CLEC_gic_spi_64_103
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_100_115_to_C7X256V1_CLEC_soc_events_in_16_31
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_WKUP_R5FSS0_CORE0_intr_8_15
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_WKUP_R5FSS0_CORE0_intr_64_95
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_136_151_to_HSM0_nvic_176_191
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE0_intr_64_79
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_R5FSS0_CORE0_cpu0_intr_64_79
 
const struct Sciclient_rmIrqIf *const tisci_if_DMASS0_INTAGGR_0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DMASS0_INTAGGR_0
 
const struct Sciclient_rmIrqIf MCU_TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_170_170
 
const struct Sciclient_rmIrqIf *const tisci_if_MCU_TIMER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCU_TIMER0
 
const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_162_162
 
const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER0
 
const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_163_163
 
const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER1
 
const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_164_164
 
const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER2
 
const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_165_165
 
const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER3
 
const struct Sciclient_rmIrqIf TIMER4_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_166_166
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER4 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER4
 
const struct Sciclient_rmIrqIf TIMER5_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_167_167
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER5 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER5
 
const struct Sciclient_rmIrqIf TIMER6_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_168_168
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER6 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER6
 
const struct Sciclient_rmIrqIf TIMER7_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_169_169
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER7 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER7
 
const struct Sciclient_rmIrqIf MCU_TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_171_171
 
const struct Sciclient_rmIrqIf *const tisci_if_MCU_TIMER1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCU_TIMER1
 
const struct Sciclient_rmIrqIf MCU_TIMER2_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_172_172
 
const struct Sciclient_rmIrqIf *const tisci_if_MCU_TIMER2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCU_TIMER2
 
const struct Sciclient_rmIrqIf MCU_TIMER3_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_173_173
 
const struct Sciclient_rmIrqIf *const tisci_if_MCU_TIMER3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCU_TIMER3
 
const struct Sciclient_rmIrqIf WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_11_11
 
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_GTC0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_WKUP_GTC0
 
const struct Sciclient_rmIrqIf GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
 
const struct Sciclient_rmIrqIf GPIO0_gpio_90_91_to_MAIN_GPIOMUX_INTROUTER0_in_176_177
 
const struct Sciclient_rmIrqIf GPIO0_gpio_bank_92_97_to_MAIN_GPIOMUX_INTROUTER0_in_190_195
 
const struct Sciclient_rmIrqIf *const tisci_if_GPIO0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPIO0
 
const struct Sciclient_rmIrqIf GPIO1_gpio_0_71_to_MAIN_GPIOMUX_INTROUTER0_in_90_161
 
const struct Sciclient_rmIrqIf GPIO1_gpio_bank_72_77_to_MAIN_GPIOMUX_INTROUTER0_in_180_185
 
const struct Sciclient_rmIrqIf *const tisci_if_GPIO1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPIO1
 
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_23_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_0_23
 
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_24_25_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_30_31
 
const struct Sciclient_rmIrqIf *const tisci_if_MCU_GPIO0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCU_GPIO0
 
const struct Sciclient_rmIrqIf GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_26_26
 
const struct Sciclient_rmIrqIf *const tisci_if_GPMC0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPMC0
 
const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_8_8
 
const struct Sciclient_rmIrqIf *const tisci_if_EPWM0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EPWM0
 
const struct Sciclient_rmIrqIf WKUP_TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_174_174
 
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_TIMER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_WKUP_TIMER0
 
const struct Sciclient_rmIrqIf WKUP_TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_175_175
 
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_TIMER1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_WKUP_TIMER1
 
const struct Sciclient_rmIrqIf MCRC64_0_int_mcrc_4_4_to_DMASS0_INTAGGR_0_intaggr_levi_pend_7_7
 
const struct Sciclient_rmIrqIf MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31
 
const struct Sciclient_rmIrqIf *const tisci_if_MCRC64_0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCRC64_0
 
const struct Sciclient_rmIrqIf DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27
 
const struct Sciclient_rmIrqIf *const tisci_if_DEBUGSS0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DEBUGSS0
 
const struct Sciclient_rmIrqIf DSS0_dispc_intr_req_0_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_2_2
 
const struct Sciclient_rmIrqIf DSS0_dispc_intr_req_1_1_1_to_DMASS0_INTAGGR_0_intaggr_levi_pend_3_3
 
const struct Sciclient_rmIrqIf *const tisci_if_DSS0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DSS0
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_GICSS0_spi_237_244
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_C7X256V0_CLEC_gic_spi_237_244
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_C7X256V1_CLEC_gic_spi_237_244
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_8_11_to_WKUP_R5FSS0_CORE0_intr_129_132
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_12_12_to_WKUP_R5FSS0_CORE0_intr_150_150
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_13_15_to_WKUP_R5FSS0_CORE0_intr_158_160
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_32_39_to_R5FSS0_CORE0_intr_8_15
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_24_27_to_R5FSS0_CORE0_intr_129_132
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_28_29_to_R5FSS0_CORE0_intr_138_139
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_30_31_to_R5FSS0_CORE0_intr_143_144
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_23_23_to_R5FSS0_CORE0_intr_150_150
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_14_15_to_R5FSS0_CORE0_intr_158_159
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_22_22_to_R5FSS0_CORE0_intr_160_160
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_16_19_to_MCU_R5FSS0_CORE0_cpu0_intr_129_132
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_20_20_to_MCU_R5FSS0_CORE0_cpu0_intr_150_150
 
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_21_23_to_MCU_R5FSS0_CORE0_cpu0_intr_158_160
 
const struct Sciclient_rmIrqIf *const tisci_if_DMASS1_INTAGGR_0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DMASS1_INTAGGR_0
 
const struct Sciclient_rmIrqIf DSS1_dispc_intr_req_0_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_4_4
 
const struct Sciclient_rmIrqIf DSS1_dispc_intr_req_1_1_1_to_DMASS0_INTAGGR_0_intaggr_levi_pend_5_5
 
const struct Sciclient_rmIrqIf *const tisci_if_DSS1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DSS1
 
const struct Sciclient_rmIrqIf MCASP3_rec_intr_pend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_186_186
 
const struct Sciclient_rmIrqIf MCASP3_xmit_intr_pend_1_1_to_MAIN_GPIOMUX_INTROUTER0_in_187_187
 
const struct Sciclient_rmIrqIf *const tisci_if_MCASP3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCASP3
 
const struct Sciclient_rmIrqIf MCASP4_rec_intr_pend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_188_188
 
const struct Sciclient_rmIrqIf MCASP4_xmit_intr_pend_1_1_to_MAIN_GPIOMUX_INTROUTER0_in_189_189
 
const struct Sciclient_rmIrqIf *const tisci_if_MCASP4 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCASP4
 
const struct Sciclient_rmIrqIf I2C4_pointrpend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_178_178
 
const struct Sciclient_rmIrqIf *const tisci_if_I2C4 []
 
static const struct Sciclient_rmIrqNode tisci_irq_I2C4
 
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_1_1
 
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_4_4
 
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_5_5
 
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_6_6
 
const struct Sciclient_rmIrqIf PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_7_7
 
const struct Sciclient_rmIrqIf *const tisci_if_PCIE0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_PCIE0
 
const struct Sciclient_rmIrqIf DMPAC0_dmpac_level_0_1_to_MAIN_GPIOMUX_INTROUTER0_in_196_197
 
const struct Sciclient_rmIrqIf *const tisci_if_DMPAC0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DMPAC0
 
const struct Sciclient_rmIrqNode *const gRmIrqTree []
 
const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])
 

Variable Documentation

◆ rom_usage_DMASS0_INTAGGR_0

struct Sciclient_rmIaUsedMapping rom_usage_DMASS0_INTAGGR_0[1U]
static
Initial value:
= {
{
.event = 30U,
.cleared = false,
},
}

◆ vint_usage_count_DMASS0_INTAGGR_0

uint8_t vint_usage_count_DMASS0_INTAGGR_0[184U] = {0}

◆ rom_usage_DMASS1_INTAGGR_0

struct Sciclient_rmIaUsedMapping rom_usage_DMASS1_INTAGGR_0[1U]
static
Initial value:
= {
{
.event = 5651U,
.cleared = false,
},
}

◆ vint_usage_count_DMASS1_INTAGGR_0

uint8_t vint_usage_count_DMASS1_INTAGGR_0[40] = {0}

◆ gRmIaInstances

struct Sciclient_rmIaInst gRmIaInstances[SCICLIENT_RM_IA_NUM_INST]
Initial value:
=
{
{
.imap = 0x48100000,
.sevt_offset = 0u,
.n_sevt = 1536u,
.n_vint = 184,
.vint_usage_count = &vint_usage_count_DMASS0_INTAGGR_0[0],
.v0_b0_evt = 0,
.rom_usage = &rom_usage_DMASS0_INTAGGR_0[0U],
.n_rom_usage = 1,
},
{
.imap = 0x4e0b0000,
.sevt_offset = 12288u,
.n_sevt = 216u,
.n_vint = 40,
.vint_usage_count = &vint_usage_count_DMASS1_INTAGGR_0[0],
.v0_b0_evt = 0,
.rom_usage = &rom_usage_DMASS1_INTAGGR_0[0U],
.n_rom_usage = 1,
}
}

◆ gRmIrInstances

struct Sciclient_rmIrInst gRmIrInstances[SCICLIENT_RM_IR_NUM_INST]
Initial value:
=
{
{
.cfg = 0xa00000,
.n_inp = 200u,
.n_outp = 36u,
.inp0_mapping = 0,
.rom_usage = NULL,
.n_rom_usage = 0U,
},
{
.cfg = 0x4210000,
.n_inp = 32u,
.n_outp = 16u,
.inp0_mapping = 0,
.rom_usage = NULL,
.n_rom_usage = 0U,
},
{
.cfg = 0xa40000,
.n_inp = 20u,
.n_outp = 26u,
.inp0_mapping = 0,
.rom_usage = NULL,
.n_rom_usage = 0U,
},
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
Initial value:
= {
.lbase = 0,
.len = 16,
.rbase = 32,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_WKUP_R5FSS0_CORE0_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_WKUP_R5FSS0_CORE0_intr_32_47
Initial value:
= {
.lbase = 0,
.len = 16,
.rbase = 32,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_32_47
Initial value:
= {
.lbase = 0,
.len = 16,
.rbase = 32,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V1_CLEC_gic_spi_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V1_CLEC_gic_spi_32_47
Initial value:
= {
.lbase = 0,
.len = 16,
.rbase = 32,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_0_7_to_HSM0_nvic_208_215

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_7_to_HSM0_nvic_208_215
Initial value:
= {
.lbase = 0,
.len = 8,
.rbase = 208,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_20_21_to_R5FSS0_CORE0_intr_56_57

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_20_21_to_R5FSS0_CORE0_intr_56_57
Initial value:
= {
.lbase = 20,
.len = 2,
.rbase = 56,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_32_33_to_R5FSS0_CORE0_intr_58_59

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_32_33_to_R5FSS0_CORE0_intr_58_59
Initial value:
= {
.lbase = 32,
.len = 2,
.rbase = 58,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_16_19_to_R5FSS0_CORE0_intr_104_107

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_16_19_to_R5FSS0_CORE0_intr_104_107
Initial value:
= {
.lbase = 16,
.len = 4,
.rbase = 104,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
Initial value:
= {
.lbase = 24,
.len = 8,
.rbase = 16,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_22_23_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_22_23_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
Initial value:
= {
.lbase = 22,
.len = 2,
.rbase = 24,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_34_35_to_MCU_R5FSS0_CORE0_cpu0_intr_32_33

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_34_35_to_MCU_R5FSS0_CORE0_cpu0_intr_32_33
Initial value:
= {
.lbase = 34,
.len = 2,
.rbase = 32,
}

◆ tisci_if_MAIN_GPIOMUX_INTROUTER0

◆ tisci_irq_MAIN_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_MAIN_GPIOMUX_INTROUTER0
static
Initial value:

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
Initial value:
= {
.lbase = 0,
.len = 4,
.rbase = 104,
}

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_WKUP_R5FSS0_CORE0_intr_104_107

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_WKUP_R5FSS0_CORE0_intr_104_107
Initial value:
= {
.lbase = 0,
.len = 4,
.rbase = 104,
}

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_104_107

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_104_107
Initial value:
= {
.lbase = 0,
.len = 4,
.rbase = 104,
}

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V1_CLEC_gic_spi_104_107

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V1_CLEC_gic_spi_104_107
Initial value:
= {
.lbase = 0,
.len = 4,
.rbase = 104,
}

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_R5FSS0_CORE0_cpu0_intr_104_107

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_R5FSS0_CORE0_cpu0_intr_104_107
Initial value:
= {
.lbase = 4,
.len = 4,
.rbase = 104,
}

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_HSM0_nvic_78_81

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_HSM0_nvic_78_81
Initial value:
= {
.lbase = 4,
.len = 4,
.rbase = 78,
}

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91
Initial value:
= {
.lbase = 8,
.len = 4,
.rbase = 88,
}

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95
Initial value:
= {
.lbase = 8,
.len = 4,
.rbase = 92,
}

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99
Initial value:
= {
.lbase = 8,
.len = 4,
.rbase = 96,
}

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_12_13_to_R5FSS0_CORE0_intr_32_33

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_12_13_to_R5FSS0_CORE0_intr_32_33
Initial value:
= {
.lbase = 12,
.len = 2,
.rbase = 32,
}

◆ WKUP_MCU_GPIOMUX_INTROUTER0_outp_14_15_to_R5FSS0_CORE0_intr_60_61

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_14_15_to_R5FSS0_CORE0_intr_60_61
Initial value:
= {
.lbase = 14,
.len = 2,
.rbase = 60,
}

◆ tisci_if_WKUP_MCU_GPIOMUX_INTROUTER0

◆ tisci_irq_WKUP_MCU_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_WKUP_MCU_GPIOMUX_INTROUTER0
static
Initial value:

◆ TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
Initial value:
= {
.lbase = 0,
.len = 8,
.rbase = 8,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PCIE0_pcie_cpts_hw2_push_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PCIE0_pcie_cpts_hw2_push_0_0
Initial value:
= {
.lbase = 8,
.len = 1,
.rbase = 0,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_CPSW0_cpts_hw1_push_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_CPSW0_cpts_hw1_push_0_0
Initial value:
= {
.lbase = 10,
.len = 1,
.rbase = 0,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_CPSW0_cpts_hw2_push_1_1

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_CPSW0_cpts_hw2_push_1_1
Initial value:
= {
.lbase = 11,
.len = 1,
.rbase = 1,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_CPSW0_cpts_hw3_push_2_2

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_CPSW0_cpts_hw3_push_2_2
Initial value:
= {
.lbase = 12,
.len = 1,
.rbase = 2,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_CPSW0_cpts_hw4_push_3_3

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_CPSW0_cpts_hw4_push_3_3
Initial value:
= {
.lbase = 13,
.len = 1,
.rbase = 3,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_CPSW0_cpts_hw5_push_4_4

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_CPSW0_cpts_hw5_push_4_4
Initial value:
= {
.lbase = 14,
.len = 1,
.rbase = 4,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_CPSW0_cpts_hw6_push_5_5

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_CPSW0_cpts_hw6_push_5_5
Initial value:
= {
.lbase = 15,
.len = 1,
.rbase = 5,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPSW0_cpts_hw7_push_6_6

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPSW0_cpts_hw7_push_6_6
Initial value:
= {
.lbase = 16,
.len = 1,
.rbase = 6,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPSW0_cpts_hw8_push_7_7

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPSW0_cpts_hw8_push_7_7
Initial value:
= {
.lbase = 17,
.len = 1,
.rbase = 7,
}

◆ tisci_if_TIMESYNC_EVENT_INTROUTER0

◆ tisci_irq_TIMESYNC_EVENT_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_EVENT_INTROUTER0
static
Initial value:

◆ CPSW0_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_0

const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_0
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 0,
}

◆ CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16

const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 16,
}

◆ CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17

const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
Initial value:
= {
.lbase = 2,
.len = 1,
.rbase = 17,
}

◆ CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18

const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
Initial value:
= {
.lbase = 3,
.len = 1,
.rbase = 18,
}

◆ tisci_if_CPSW0

◆ tisci_irq_CPSW0

const struct Sciclient_rmIrqNode tisci_irq_CPSW0
static
Initial value:
= {
.n_if = 4,
.p_if = &tisci_if_CPSW0[0],
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
Initial value:
= {
.lbase = 0,
.len = 40,
.rbase = 64,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V0_CLEC_gic_spi_64_103

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V0_CLEC_gic_spi_64_103
Initial value:
= {
.lbase = 0,
.len = 40,
.rbase = 64,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_16_31

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_16_31
Initial value:
= {
.lbase = 84,
.len = 16,
.rbase = 16,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V1_CLEC_gic_spi_64_103

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V1_CLEC_gic_spi_64_103
Initial value:
= {
.lbase = 0,
.len = 40,
.rbase = 64,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_100_115_to_C7X256V1_CLEC_soc_events_in_16_31

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_100_115_to_C7X256V1_CLEC_soc_events_in_16_31
Initial value:
= {
.lbase = 100,
.len = 16,
.rbase = 16,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_WKUP_R5FSS0_CORE0_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_WKUP_R5FSS0_CORE0_intr_8_15
Initial value:
= {
.lbase = 72,
.len = 8,
.rbase = 8,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_WKUP_R5FSS0_CORE0_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_WKUP_R5FSS0_CORE0_intr_64_95
Initial value:
= {
.lbase = 40,
.len = 32,
.rbase = 64,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_136_151_to_HSM0_nvic_176_191

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_136_151_to_HSM0_nvic_176_191
Initial value:
= {
.lbase = 136,
.len = 16,
.rbase = 176,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE0_intr_64_79

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE0_intr_64_79
Initial value:
= {
.lbase = 152,
.len = 16,
.rbase = 64,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_R5FSS0_CORE0_cpu0_intr_64_79

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_R5FSS0_CORE0_cpu0_intr_64_79
Initial value:
= {
.lbase = 168,
.len = 16,
.rbase = 64,
}

◆ tisci_if_DMASS0_INTAGGR_0

◆ tisci_irq_DMASS0_INTAGGR_0

const struct Sciclient_rmIrqNode tisci_irq_DMASS0_INTAGGR_0
static
Initial value:
= {
.n_if = 10,
}

◆ MCU_TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_170_170

const struct Sciclient_rmIrqIf MCU_TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_170_170
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 170,
}

◆ tisci_if_MCU_TIMER0

const struct Sciclient_rmIrqIf* const tisci_if_MCU_TIMER0[]

◆ tisci_irq_MCU_TIMER0

const struct Sciclient_rmIrqNode tisci_irq_MCU_TIMER0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_MCU_TIMER0[0],
}

◆ TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_162_162

const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_162_162
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 162,
}

◆ TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0

const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 0,
}

◆ tisci_if_TIMER0

const struct Sciclient_rmIrqIf* const tisci_if_TIMER0[]

◆ tisci_irq_TIMER0

const struct Sciclient_rmIrqNode tisci_irq_TIMER0
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_TIMER0[0],
}

◆ TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_163_163

const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_163_163
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 163,
}

◆ TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1

const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 1,
}

◆ tisci_if_TIMER1

const struct Sciclient_rmIrqIf* const tisci_if_TIMER1[]

◆ tisci_irq_TIMER1

const struct Sciclient_rmIrqNode tisci_irq_TIMER1
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_TIMER1[0],
}

◆ TIMER2_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_164_164

const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_164_164
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 164,
}

◆ TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2

const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 2,
}

◆ tisci_if_TIMER2

const struct Sciclient_rmIrqIf* const tisci_if_TIMER2[]

◆ tisci_irq_TIMER2

const struct Sciclient_rmIrqNode tisci_irq_TIMER2
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_TIMER2[0],
}

◆ TIMER3_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_165_165

const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_165_165
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 165,
}

◆ TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3

const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 3,
}

◆ tisci_if_TIMER3

const struct Sciclient_rmIrqIf* const tisci_if_TIMER3[]

◆ tisci_irq_TIMER3

const struct Sciclient_rmIrqNode tisci_irq_TIMER3
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_TIMER3[0],
}

◆ TIMER4_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_166_166

const struct Sciclient_rmIrqIf TIMER4_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_166_166
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 166,
}

◆ tisci_if_TIMER4

const struct Sciclient_rmIrqIf* const tisci_if_TIMER4[]

◆ tisci_irq_TIMER4

const struct Sciclient_rmIrqNode tisci_irq_TIMER4
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_TIMER4[0],
}

◆ TIMER5_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_167_167

const struct Sciclient_rmIrqIf TIMER5_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_167_167
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 167,
}

◆ tisci_if_TIMER5

const struct Sciclient_rmIrqIf* const tisci_if_TIMER5[]

◆ tisci_irq_TIMER5

const struct Sciclient_rmIrqNode tisci_irq_TIMER5
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_TIMER5[0],
}

◆ TIMER6_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_168_168

const struct Sciclient_rmIrqIf TIMER6_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_168_168
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 168,
}

◆ tisci_if_TIMER6

const struct Sciclient_rmIrqIf* const tisci_if_TIMER6[]

◆ tisci_irq_TIMER6

const struct Sciclient_rmIrqNode tisci_irq_TIMER6
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_TIMER6[0],
}

◆ TIMER7_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_169_169

const struct Sciclient_rmIrqIf TIMER7_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_169_169
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 169,
}

◆ tisci_if_TIMER7

const struct Sciclient_rmIrqIf* const tisci_if_TIMER7[]

◆ tisci_irq_TIMER7

const struct Sciclient_rmIrqNode tisci_irq_TIMER7
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_TIMER7[0],
}

◆ MCU_TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_171_171

const struct Sciclient_rmIrqIf MCU_TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_171_171
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 171,
}

◆ tisci_if_MCU_TIMER1

const struct Sciclient_rmIrqIf* const tisci_if_MCU_TIMER1[]

◆ tisci_irq_MCU_TIMER1

const struct Sciclient_rmIrqNode tisci_irq_MCU_TIMER1
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_MCU_TIMER1[0],
}

◆ MCU_TIMER2_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_172_172

const struct Sciclient_rmIrqIf MCU_TIMER2_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_172_172
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 172,
}

◆ tisci_if_MCU_TIMER2

const struct Sciclient_rmIrqIf* const tisci_if_MCU_TIMER2[]

◆ tisci_irq_MCU_TIMER2

const struct Sciclient_rmIrqNode tisci_irq_MCU_TIMER2
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_MCU_TIMER2[0],
}

◆ MCU_TIMER3_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_173_173

const struct Sciclient_rmIrqIf MCU_TIMER3_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_173_173
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 173,
}

◆ tisci_if_MCU_TIMER3

const struct Sciclient_rmIrqIf* const tisci_if_MCU_TIMER3[]

◆ tisci_irq_MCU_TIMER3

const struct Sciclient_rmIrqNode tisci_irq_MCU_TIMER3
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_MCU_TIMER3[0],
}

◆ WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_11_11

const struct Sciclient_rmIrqIf WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_11_11
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 11,
}

◆ tisci_if_WKUP_GTC0

const struct Sciclient_rmIrqIf* const tisci_if_WKUP_GTC0[]

◆ tisci_irq_WKUP_GTC0

const struct Sciclient_rmIrqNode tisci_irq_WKUP_GTC0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_WKUP_GTC0[0],
}

◆ GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89

const struct Sciclient_rmIrqIf GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
Initial value:
= {
.lbase = 0,
.len = 90,
.rbase = 0,
}

◆ GPIO0_gpio_90_91_to_MAIN_GPIOMUX_INTROUTER0_in_176_177

const struct Sciclient_rmIrqIf GPIO0_gpio_90_91_to_MAIN_GPIOMUX_INTROUTER0_in_176_177
Initial value:
= {
.lbase = 90,
.len = 2,
.rbase = 176,
}

◆ GPIO0_gpio_bank_92_97_to_MAIN_GPIOMUX_INTROUTER0_in_190_195

const struct Sciclient_rmIrqIf GPIO0_gpio_bank_92_97_to_MAIN_GPIOMUX_INTROUTER0_in_190_195
Initial value:
= {
.lbase = 92,
.len = 6,
.rbase = 190,
}

◆ tisci_if_GPIO0

◆ tisci_irq_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_GPIO0
static
Initial value:
= {
.n_if = 3,
.p_if = &tisci_if_GPIO0[0],
}

◆ GPIO1_gpio_0_71_to_MAIN_GPIOMUX_INTROUTER0_in_90_161

const struct Sciclient_rmIrqIf GPIO1_gpio_0_71_to_MAIN_GPIOMUX_INTROUTER0_in_90_161
Initial value:
= {
.lbase = 0,
.len = 72,
.rbase = 90,
}

◆ GPIO1_gpio_bank_72_77_to_MAIN_GPIOMUX_INTROUTER0_in_180_185

const struct Sciclient_rmIrqIf GPIO1_gpio_bank_72_77_to_MAIN_GPIOMUX_INTROUTER0_in_180_185
Initial value:
= {
.lbase = 72,
.len = 6,
.rbase = 180,
}

◆ tisci_if_GPIO1

const struct Sciclient_rmIrqIf* const tisci_if_GPIO1[]

◆ tisci_irq_GPIO1

const struct Sciclient_rmIrqNode tisci_irq_GPIO1
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_GPIO1[0],
}

◆ MCU_GPIO0_gpio_0_23_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_0_23

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_23_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_0_23
Initial value:
= {
.lbase = 0,
.len = 24,
.rbase = 0,
}

◆ MCU_GPIO0_gpio_bank_24_25_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_30_31

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_24_25_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_30_31
Initial value:
= {
.lbase = 24,
.len = 2,
.rbase = 30,
}

◆ tisci_if_MCU_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_MCU_GPIO0[]

◆ tisci_irq_MCU_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_MCU_GPIO0
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_MCU_GPIO0[0],
}

◆ GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_26_26

const struct Sciclient_rmIrqIf GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_26_26
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 26,
}

◆ tisci_if_GPMC0

const struct Sciclient_rmIrqIf* const tisci_if_GPMC0[]

◆ tisci_irq_GPMC0

const struct Sciclient_rmIrqNode tisci_irq_GPMC0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_GPMC0[0],
}

◆ EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_8_8

const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_8_8
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 8,
}

◆ tisci_if_EPWM0

const struct Sciclient_rmIrqIf* const tisci_if_EPWM0[]

◆ tisci_irq_EPWM0

const struct Sciclient_rmIrqNode tisci_irq_EPWM0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_EPWM0[0],
}

◆ WKUP_TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_174_174

const struct Sciclient_rmIrqIf WKUP_TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_174_174
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 174,
}

◆ tisci_if_WKUP_TIMER0

const struct Sciclient_rmIrqIf* const tisci_if_WKUP_TIMER0[]

◆ tisci_irq_WKUP_TIMER0

const struct Sciclient_rmIrqNode tisci_irq_WKUP_TIMER0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_WKUP_TIMER0[0],
}

◆ WKUP_TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_175_175

const struct Sciclient_rmIrqIf WKUP_TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_175_175
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 175,
}

◆ tisci_if_WKUP_TIMER1

const struct Sciclient_rmIrqIf* const tisci_if_WKUP_TIMER1[]

◆ tisci_irq_WKUP_TIMER1

const struct Sciclient_rmIrqNode tisci_irq_WKUP_TIMER1
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_WKUP_TIMER1[0],
}

◆ MCRC64_0_int_mcrc_4_4_to_DMASS0_INTAGGR_0_intaggr_levi_pend_7_7

const struct Sciclient_rmIrqIf MCRC64_0_int_mcrc_4_4_to_DMASS0_INTAGGR_0_intaggr_levi_pend_7_7
Initial value:
= {
.lbase = 4,
.len = 1,
.rbase = 7,
}

◆ MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31

const struct Sciclient_rmIrqIf MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31
Initial value:
= {
.lbase = 0,
.len = 4,
.rbase = 28,
}

◆ tisci_if_MCRC64_0

◆ tisci_irq_MCRC64_0

const struct Sciclient_rmIrqNode tisci_irq_MCRC64_0
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_MCRC64_0[0],
}

◆ DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27

const struct Sciclient_rmIrqIf DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 27,
}

◆ tisci_if_DEBUGSS0

const struct Sciclient_rmIrqIf* const tisci_if_DEBUGSS0[]

◆ tisci_irq_DEBUGSS0

const struct Sciclient_rmIrqNode tisci_irq_DEBUGSS0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_DEBUGSS0[0],
}

◆ DSS0_dispc_intr_req_0_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_2_2

const struct Sciclient_rmIrqIf DSS0_dispc_intr_req_0_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_2_2
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 2,
}

◆ DSS0_dispc_intr_req_1_1_1_to_DMASS0_INTAGGR_0_intaggr_levi_pend_3_3

const struct Sciclient_rmIrqIf DSS0_dispc_intr_req_1_1_1_to_DMASS0_INTAGGR_0_intaggr_levi_pend_3_3
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 3,
}

◆ tisci_if_DSS0

◆ tisci_irq_DSS0

const struct Sciclient_rmIrqNode tisci_irq_DSS0
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_DSS0[0],
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_GICSS0_spi_237_244

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_GICSS0_spi_237_244
Initial value:
= {
.lbase = 0,
.len = 8,
.rbase = 237,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_C7X256V0_CLEC_gic_spi_237_244

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_C7X256V0_CLEC_gic_spi_237_244
Initial value:
= {
.lbase = 0,
.len = 8,
.rbase = 237,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_C7X256V1_CLEC_gic_spi_237_244

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_C7X256V1_CLEC_gic_spi_237_244
Initial value:
= {
.lbase = 0,
.len = 8,
.rbase = 237,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_8_11_to_WKUP_R5FSS0_CORE0_intr_129_132

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_8_11_to_WKUP_R5FSS0_CORE0_intr_129_132
Initial value:
= {
.lbase = 8,
.len = 4,
.rbase = 129,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_12_12_to_WKUP_R5FSS0_CORE0_intr_150_150

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_12_12_to_WKUP_R5FSS0_CORE0_intr_150_150
Initial value:
= {
.lbase = 12,
.len = 1,
.rbase = 150,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_13_15_to_WKUP_R5FSS0_CORE0_intr_158_160

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_13_15_to_WKUP_R5FSS0_CORE0_intr_158_160
Initial value:
= {
.lbase = 13,
.len = 3,
.rbase = 158,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_32_39_to_R5FSS0_CORE0_intr_8_15

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_32_39_to_R5FSS0_CORE0_intr_8_15
Initial value:
= {
.lbase = 32,
.len = 8,
.rbase = 8,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_24_27_to_R5FSS0_CORE0_intr_129_132

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_24_27_to_R5FSS0_CORE0_intr_129_132
Initial value:
= {
.lbase = 24,
.len = 4,
.rbase = 129,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_28_29_to_R5FSS0_CORE0_intr_138_139

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_28_29_to_R5FSS0_CORE0_intr_138_139
Initial value:
= {
.lbase = 28,
.len = 2,
.rbase = 138,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_30_31_to_R5FSS0_CORE0_intr_143_144

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_30_31_to_R5FSS0_CORE0_intr_143_144
Initial value:
= {
.lbase = 30,
.len = 2,
.rbase = 143,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_23_23_to_R5FSS0_CORE0_intr_150_150

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_23_23_to_R5FSS0_CORE0_intr_150_150
Initial value:
= {
.lbase = 23,
.len = 1,
.rbase = 150,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_14_15_to_R5FSS0_CORE0_intr_158_159

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_14_15_to_R5FSS0_CORE0_intr_158_159
Initial value:
= {
.lbase = 14,
.len = 2,
.rbase = 158,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_22_22_to_R5FSS0_CORE0_intr_160_160

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_22_22_to_R5FSS0_CORE0_intr_160_160
Initial value:
= {
.lbase = 22,
.len = 1,
.rbase = 160,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_16_19_to_MCU_R5FSS0_CORE0_cpu0_intr_129_132

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_16_19_to_MCU_R5FSS0_CORE0_cpu0_intr_129_132
Initial value:
= {
.lbase = 16,
.len = 4,
.rbase = 129,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_20_20_to_MCU_R5FSS0_CORE0_cpu0_intr_150_150

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_20_20_to_MCU_R5FSS0_CORE0_cpu0_intr_150_150
Initial value:
= {
.lbase = 20,
.len = 1,
.rbase = 150,
}

◆ DMASS1_INTAGGR_0_intaggr_vintr_pend_21_23_to_MCU_R5FSS0_CORE0_cpu0_intr_158_160

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_21_23_to_MCU_R5FSS0_CORE0_cpu0_intr_158_160
Initial value:
= {
.lbase = 21,
.len = 3,
.rbase = 158,
}

◆ tisci_if_DMASS1_INTAGGR_0

◆ tisci_irq_DMASS1_INTAGGR_0

const struct Sciclient_rmIrqNode tisci_irq_DMASS1_INTAGGR_0
static
Initial value:
= {
.n_if = 16,
}

◆ DSS1_dispc_intr_req_0_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_4_4

const struct Sciclient_rmIrqIf DSS1_dispc_intr_req_0_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_4_4
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 4,
}

◆ DSS1_dispc_intr_req_1_1_1_to_DMASS0_INTAGGR_0_intaggr_levi_pend_5_5

const struct Sciclient_rmIrqIf DSS1_dispc_intr_req_1_1_1_to_DMASS0_INTAGGR_0_intaggr_levi_pend_5_5
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 5,
}

◆ tisci_if_DSS1

◆ tisci_irq_DSS1

const struct Sciclient_rmIrqNode tisci_irq_DSS1
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_DSS1[0],
}

◆ MCASP3_rec_intr_pend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_186_186

const struct Sciclient_rmIrqIf MCASP3_rec_intr_pend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_186_186
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 186,
}

◆ MCASP3_xmit_intr_pend_1_1_to_MAIN_GPIOMUX_INTROUTER0_in_187_187

const struct Sciclient_rmIrqIf MCASP3_xmit_intr_pend_1_1_to_MAIN_GPIOMUX_INTROUTER0_in_187_187
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 187,
}

◆ tisci_if_MCASP3

◆ tisci_irq_MCASP3

const struct Sciclient_rmIrqNode tisci_irq_MCASP3
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_MCASP3[0],
}

◆ MCASP4_rec_intr_pend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_188_188

const struct Sciclient_rmIrqIf MCASP4_rec_intr_pend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_188_188
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 188,
}

◆ MCASP4_xmit_intr_pend_1_1_to_MAIN_GPIOMUX_INTROUTER0_in_189_189

const struct Sciclient_rmIrqIf MCASP4_xmit_intr_pend_1_1_to_MAIN_GPIOMUX_INTROUTER0_in_189_189
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 189,
}

◆ tisci_if_MCASP4

◆ tisci_irq_MCASP4

const struct Sciclient_rmIrqNode tisci_irq_MCASP4
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_MCASP4[0],
}

◆ I2C4_pointrpend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_178_178

const struct Sciclient_rmIrqIf I2C4_pointrpend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_178_178
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 178,
}

◆ tisci_if_I2C4

const struct Sciclient_rmIrqIf* const tisci_if_I2C4[]

◆ tisci_irq_I2C4

const struct Sciclient_rmIrqNode tisci_irq_I2C4
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_I2C4[0],
}

◆ PCIE0_pcie_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_1_1

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_1_1
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 1,
}

◆ PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_4_4

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_4_4
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 4,
}

◆ PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_5_5

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_5_5
Initial value:
= {
.lbase = 2,
.len = 1,
.rbase = 5,
}

◆ PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_6_6

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_6_6
Initial value:
= {
.lbase = 3,
.len = 1,
.rbase = 6,
}

◆ PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_7_7

const struct Sciclient_rmIrqIf PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_7_7
Initial value:
= {
.lbase = 4,
.len = 1,
.rbase = 7,
}

◆ tisci_if_PCIE0

◆ tisci_irq_PCIE0

const struct Sciclient_rmIrqNode tisci_irq_PCIE0
static
Initial value:
= {
.n_if = 5,
.p_if = &tisci_if_PCIE0[0],
}

◆ DMPAC0_dmpac_level_0_1_to_MAIN_GPIOMUX_INTROUTER0_in_196_197

const struct Sciclient_rmIrqIf DMPAC0_dmpac_level_0_1_to_MAIN_GPIOMUX_INTROUTER0_in_196_197
Initial value:
= {
.lbase = 0,
.len = 2,
.rbase = 196,
}

◆ tisci_if_DMPAC0

const struct Sciclient_rmIrqIf* const tisci_if_DMPAC0[]

◆ tisci_irq_DMPAC0

const struct Sciclient_rmIrqNode tisci_irq_DMPAC0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_DMPAC0[0],
}

◆ gRmIrqTree

const struct Sciclient_rmIrqNode* const gRmIrqTree[]

◆ gRmIrqTreeCount

const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])
MAIN_GPIOMUX_INTROUTER0_outp_22_23_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_22_23_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
Definition: sciclient_irq_rm.c:177
TISCI_DEV_EPWM0
#define TISCI_DEV_EPWM0
Definition: tisci_devices.h:119
MCU_TIMER3_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_173_173
const struct Sciclient_rmIrqIf MCU_TIMER3_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_173_173
Definition: sciclient_irq_rm.c:694
DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_WKUP_R5FSS0_CORE0_intr_8_15
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_WKUP_R5FSS0_CORE0_intr_8_15
Definition: sciclient_irq_rm.c:441
DMASS1_INTAGGR_0_intaggr_vintr_pend_14_15_to_R5FSS0_CORE0_intr_158_159
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_14_15_to_R5FSS0_CORE0_intr_158_159
Definition: sciclient_irq_rm.c:994
TIMER4_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_166_166
const struct Sciclient_rmIrqIf TIMER4_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_166_166
Definition: sciclient_irq_rm.c:598
rom_usage_DMASS0_INTAGGR_0
static struct Sciclient_rmIaUsedMapping rom_usage_DMASS0_INTAGGR_0[1U]
Definition: sciclient_irq_rm.c:48
tisci_if_EPWM0
const struct Sciclient_rmIrqIf *const tisci_if_EPWM0[]
Definition: sciclient_irq_rm.c:824
tisci_if_TIMER7
const struct Sciclient_rmIrqIf *const tisci_if_TIMER7[]
Definition: sciclient_irq_rm.c:652
tisci_if_WKUP_TIMER1
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_TIMER1[]
Definition: sciclient_irq_rm.c:856
TISCI_DEV_DSS0
#define TISCI_DEV_DSS0
Definition: tisci_devices.h:193
WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95
Definition: sciclient_irq_rm.c:251
TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_CPSW0_cpts_hw1_push_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_CPSW0_cpts_hw1_push_0_0
Definition: sciclient_irq_rm.c:307
tisci_if_DSS0
const struct Sciclient_rmIrqIf *const tisci_if_DSS0[]
Definition: sciclient_irq_rm.c:917
TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPSW0_cpts_hw8_push_7_7
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPSW0_cpts_hw8_push_7_7
Definition: sciclient_irq_rm.c:349
TISCI_DEV_TIMER1
#define TISCI_DEV_TIMER1
Definition: tisci_devices.h:86
DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_C7X256V0_CLEC_gic_spi_237_244
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_C7X256V0_CLEC_gic_spi_237_244
Definition: sciclient_irq_rm.c:934
TIMER7_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_169_169
const struct Sciclient_rmIrqIf TIMER7_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_169_169
Definition: sciclient_irq_rm.c:646
WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91
Definition: sciclient_irq_rm.c:245
tisci_if_GPMC0
const struct Sciclient_rmIrqIf *const tisci_if_GPMC0[]
Definition: sciclient_irq_rm.c:808
TISCI_DEV_MCU_TIMER1
#define TISCI_DEV_MCU_TIMER1
Definition: tisci_devices.h:93
CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
Definition: sciclient_irq_rm.c:386
tisci_if_DMPAC0
const struct Sciclient_rmIrqIf *const tisci_if_DMPAC0[]
Definition: sciclient_irq_rm.c:1184
MCASP4_xmit_intr_pend_1_1_to_MAIN_GPIOMUX_INTROUTER0_in_189_189
const struct Sciclient_rmIrqIf MCASP4_xmit_intr_pend_1_1_to_MAIN_GPIOMUX_INTROUTER0_in_189_189
Definition: sciclient_irq_rm.c:1101
DSS1_dispc_intr_req_0_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_4_4
const struct Sciclient_rmIrqIf DSS1_dispc_intr_req_0_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_4_4
Definition: sciclient_irq_rm.c:1049
TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
Definition: sciclient_irq_rm.c:295
tisci_if_TIMER1
const struct Sciclient_rmIrqIf *const tisci_if_TIMER1[]
Definition: sciclient_irq_rm.c:541
PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_7_7
const struct Sciclient_rmIrqIf PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_7_7
Definition: sciclient_irq_rm.c:1158
GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_26_26
const struct Sciclient_rmIrqIf GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_26_26
Definition: sciclient_irq_rm.c:802
TISCI_DEV_MCASP3
#define TISCI_DEV_MCASP3
Definition: tisci_devices.h:257
TISCI_DEV_PCIE0
#define TISCI_DEV_PCIE0
Definition: tisci_devices.h:261
DSS1_dispc_intr_req_1_1_1_to_DMASS0_INTAGGR_0_intaggr_levi_pend_5_5
const struct Sciclient_rmIrqIf DSS1_dispc_intr_req_1_1_1_to_DMASS0_INTAGGR_0_intaggr_levi_pend_5_5
Definition: sciclient_irq_rm.c:1055
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_32_47
Definition: sciclient_irq_rm.c:135
DMASS0_INTAGGR_0_intaggr_vintr_pend_136_151_to_HSM0_nvic_176_191
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_136_151_to_HSM0_nvic_176_191
Definition: sciclient_irq_rm.c:453
TISCI_DEV_C7X256V1_CLEC
#define TISCI_DEV_C7X256V1_CLEC
Definition: tisci_devices.h:272
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V1_CLEC_gic_spi_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V1_CLEC_gic_spi_32_47
Definition: sciclient_irq_rm.c:141
PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_6_6
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_6_6
Definition: sciclient_irq_rm.c:1152
TISCI_DEV_CPSW0
#define TISCI_DEV_CPSW0
Definition: tisci_devices.h:66
WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_WKUP_R5FSS0_CORE0_intr_104_107
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_WKUP_R5FSS0_CORE0_intr_104_107
Definition: sciclient_irq_rm.c:215
tisci_if_GPIO0
const struct Sciclient_rmIrqIf *const tisci_if_GPIO0[]
Definition: sciclient_irq_rm.c:744
DMASS1_INTAGGR_0_intaggr_vintr_pend_28_29_to_R5FSS0_CORE0_intr_138_139
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_28_29_to_R5FSS0_CORE0_intr_138_139
Definition: sciclient_irq_rm.c:976
MCU_GPIO0_gpio_bank_24_25_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_30_31
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_24_25_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_30_31
Definition: sciclient_irq_rm.c:785
TISCI_DEV_MCU_TIMER0
#define TISCI_DEV_MCU_TIMER0
Definition: tisci_devices.h:84
tisci_if_TIMER4
const struct Sciclient_rmIrqIf *const tisci_if_TIMER4[]
Definition: sciclient_irq_rm.c:604
tisci_if_MCU_GPIO0
const struct Sciclient_rmIrqIf *const tisci_if_MCU_GPIO0[]
Definition: sciclient_irq_rm.c:791
NULL
#define NULL
Define NULL if not defined.
Definition: csl_types.h:100
TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PCIE0_pcie_cpts_hw2_push_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PCIE0_pcie_cpts_hw2_push_0_0
Definition: sciclient_irq_rm.c:301
TISCI_DEV_DMASS0_INTAGGR_0
#define TISCI_DEV_DMASS0_INTAGGR_0
Definition: tisci_devices.h:80
tisci_if_GPIO1
const struct Sciclient_rmIrqIf *const tisci_if_GPIO1[]
Definition: sciclient_irq_rm.c:768
tisci_if_PCIE0
const struct Sciclient_rmIrqIf *const tisci_if_PCIE0[]
Definition: sciclient_irq_rm.c:1164
tisci_if_DMASS1_INTAGGR_0
const struct Sciclient_rmIrqIf *const tisci_if_DMASS1_INTAGGR_0[]
Definition: sciclient_irq_rm.c:1024
WKUP_TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_174_174
const struct Sciclient_rmIrqIf WKUP_TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_174_174
Definition: sciclient_irq_rm.c:834
tisci_if_TIMER2
const struct Sciclient_rmIrqIf *const tisci_if_TIMER2[]
Definition: sciclient_irq_rm.c:564
TISCI_DEV_WKUP_ESM0
#define TISCI_DEV_WKUP_ESM0
Definition: tisci_devices.h:108
tisci_if_MCASP4
const struct Sciclient_rmIrqIf *const tisci_if_MCASP4[]
Definition: sciclient_irq_rm.c:1107
tisci_if_MCRC64_0
const struct Sciclient_rmIrqIf *const tisci_if_MCRC64_0[]
Definition: sciclient_irq_rm.c:878
MCU_TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_171_171
const struct Sciclient_rmIrqIf MCU_TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_171_171
Definition: sciclient_irq_rm.c:662
TIMER5_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_167_167
const struct Sciclient_rmIrqIf TIMER5_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_167_167
Definition: sciclient_irq_rm.c:614
TISCI_DEV_TIMER2
#define TISCI_DEV_TIMER2
Definition: tisci_devices.h:87
TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
Definition: sciclient_irq_rm.c:581
DSS0_dispc_intr_req_0_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_2_2
const struct Sciclient_rmIrqIf DSS0_dispc_intr_req_0_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_2_2
Definition: sciclient_irq_rm.c:905
EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_8_8
const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_8_8
Definition: sciclient_irq_rm.c:818
TISCI_DEV_MCU_R5FSS0_CORE0
#define TISCI_DEV_MCU_R5FSS0_CORE0
Definition: tisci_devices.h:65
DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V0_CLEC_gic_spi_64_103
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V0_CLEC_gic_spi_64_103
Definition: sciclient_irq_rm.c:417
DMASS1_INTAGGR_0_intaggr_vintr_pend_12_12_to_WKUP_R5FSS0_CORE0_intr_150_150
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_12_12_to_WKUP_R5FSS0_CORE0_intr_150_150
Definition: sciclient_irq_rm.c:952
DMASS1_INTAGGR_0_intaggr_vintr_pend_30_31_to_R5FSS0_CORE0_intr_143_144
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_30_31_to_R5FSS0_CORE0_intr_143_144
Definition: sciclient_irq_rm.c:982
DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE0_intr_64_79
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE0_intr_64_79
Definition: sciclient_irq_rm.c:459
TISCI_DEV_TIMER4
#define TISCI_DEV_TIMER4
Definition: tisci_devices.h:89
MAIN_GPIOMUX_INTROUTER0_outp_32_33_to_R5FSS0_CORE0_intr_58_59
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_32_33_to_R5FSS0_CORE0_intr_58_59
Definition: sciclient_irq_rm.c:159
TISCI_DEV_DEBUGSS0
#define TISCI_DEV_DEBUGSS0
Definition: tisci_devices.h:179
DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_WKUP_R5FSS0_CORE0_intr_64_95
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_WKUP_R5FSS0_CORE0_intr_64_95
Definition: sciclient_irq_rm.c:447
WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
Definition: sciclient_irq_rm.c:209
PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_5_5
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_5_5
Definition: sciclient_irq_rm.c:1146
tisci_if_DSS1
const struct Sciclient_rmIrqIf *const tisci_if_DSS1[]
Definition: sciclient_irq_rm.c:1061
TISCI_DEV_MCU_TIMER2
#define TISCI_DEV_MCU_TIMER2
Definition: tisci_devices.h:94
DMASS1_INTAGGR_0_intaggr_vintr_pend_23_23_to_R5FSS0_CORE0_intr_150_150
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_23_23_to_R5FSS0_CORE0_intr_150_150
Definition: sciclient_irq_rm.c:988
tisci_if_MCU_TIMER3
const struct Sciclient_rmIrqIf *const tisci_if_MCU_TIMER3[]
Definition: sciclient_irq_rm.c:700
DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27
const struct Sciclient_rmIrqIf DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27
Definition: sciclient_irq_rm.c:889
TISCI_DEV_R5FSS0_CORE0
#define TISCI_DEV_R5FSS0_CORE0
Definition: tisci_devices.h:264
tisci_if_TIMER0
const struct Sciclient_rmIrqIf *const tisci_if_TIMER0[]
Definition: sciclient_irq_rm.c:518
GPIO0_gpio_90_91_to_MAIN_GPIOMUX_INTROUTER0_in_176_177
const struct Sciclient_rmIrqIf GPIO0_gpio_90_91_to_MAIN_GPIOMUX_INTROUTER0_in_176_177
Definition: sciclient_irq_rm.c:732
DSS0_dispc_intr_req_1_1_1_to_DMASS0_INTAGGR_0_intaggr_levi_pend_3_3
const struct Sciclient_rmIrqIf DSS0_dispc_intr_req_1_1_1_to_DMASS0_INTAGGR_0_intaggr_levi_pend_3_3
Definition: sciclient_irq_rm.c:911
tisci_if_WKUP_MCU_GPIOMUX_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_MCU_GPIOMUX_INTROUTER0[]
Definition: sciclient_irq_rm.c:275
tisci_if_MAIN_GPIOMUX_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_MAIN_GPIOMUX_INTROUTER0[]
Definition: sciclient_irq_rm.c:189
DMASS1_INTAGGR_0_intaggr_vintr_pend_32_39_to_R5FSS0_CORE0_intr_8_15
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_32_39_to_R5FSS0_CORE0_intr_8_15
Definition: sciclient_irq_rm.c:964
TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_162_162
const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_162_162
Definition: sciclient_irq_rm.c:506
GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
const struct Sciclient_rmIrqIf GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
Definition: sciclient_irq_rm.c:726
DMASS1_INTAGGR_0_intaggr_vintr_pend_13_15_to_WKUP_R5FSS0_CORE0_intr_158_160
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_13_15_to_WKUP_R5FSS0_CORE0_intr_158_160
Definition: sciclient_irq_rm.c:958
WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_104_107
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_104_107
Definition: sciclient_irq_rm.c:221
DMASS1_INTAGGR_0_intaggr_vintr_pend_21_23_to_MCU_R5FSS0_CORE0_cpu0_intr_158_160
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_21_23_to_MCU_R5FSS0_CORE0_cpu0_intr_158_160
Definition: sciclient_irq_rm.c:1018
TISCI_DEV_WKUP_GTC0
#define TISCI_DEV_WKUP_GTC0
Definition: tisci_devices.h:105
TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPSW0_cpts_hw7_push_6_6
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPSW0_cpts_hw7_push_6_6
Definition: sciclient_irq_rm.c:343
DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_C7X256V1_CLEC_gic_spi_237_244
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_C7X256V1_CLEC_gic_spi_237_244
Definition: sciclient_irq_rm.c:940
tisci_if_TIMER6
const struct Sciclient_rmIrqIf *const tisci_if_TIMER6[]
Definition: sciclient_irq_rm.c:636
TISCI_DEV_TIMER0
#define TISCI_DEV_TIMER0
Definition: tisci_devices.h:85
tisci_if_MCU_TIMER1
const struct Sciclient_rmIrqIf *const tisci_if_MCU_TIMER1[]
Definition: sciclient_irq_rm.c:668
TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_CPSW0_cpts_hw6_push_5_5
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_CPSW0_cpts_hw6_push_5_5
Definition: sciclient_irq_rm.c:337
WKUP_MCU_GPIOMUX_INTROUTER0_outp_14_15_to_R5FSS0_CORE0_intr_60_61
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_14_15_to_R5FSS0_CORE0_intr_60_61
Definition: sciclient_irq_rm.c:269
DMPAC0_dmpac_level_0_1_to_MAIN_GPIOMUX_INTROUTER0_in_196_197
const struct Sciclient_rmIrqIf DMPAC0_dmpac_level_0_1_to_MAIN_GPIOMUX_INTROUTER0_in_196_197
Definition: sciclient_irq_rm.c:1178
GPIO1_gpio_0_71_to_MAIN_GPIOMUX_INTROUTER0_in_90_161
const struct Sciclient_rmIrqIf GPIO1_gpio_0_71_to_MAIN_GPIOMUX_INTROUTER0_in_90_161
Definition: sciclient_irq_rm.c:756
TISCI_DEV_MAIN_GPIOMUX_INTROUTER0
#define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0
Definition: tisci_devices.h:61
MCU_GPIO0_gpio_0_23_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_0_23
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_23_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_0_23
Definition: sciclient_irq_rm.c:779
TISCI_DEV_DMPAC0
#define TISCI_DEV_DMPAC0
Definition: tisci_devices.h:279
DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_16_31
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_16_31
Definition: sciclient_irq_rm.c:423
TISCI_DEV_MCRC64_0
#define TISCI_DEV_MCRC64_0
Definition: tisci_devices.h:137
DMASS1_INTAGGR_0_intaggr_vintr_pend_24_27_to_R5FSS0_CORE0_intr_129_132
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_24_27_to_R5FSS0_CORE0_intr_129_132
Definition: sciclient_irq_rm.c:970
DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V1_CLEC_gic_spi_64_103
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V1_CLEC_gic_spi_64_103
Definition: sciclient_irq_rm.c:429
GPIO1_gpio_bank_72_77_to_MAIN_GPIOMUX_INTROUTER0_in_180_185
const struct Sciclient_rmIrqIf GPIO1_gpio_bank_72_77_to_MAIN_GPIOMUX_INTROUTER0_in_180_185
Definition: sciclient_irq_rm.c:762
tisci_if_TIMESYNC_EVENT_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_TIMESYNC_EVENT_INTROUTER0[]
Definition: sciclient_irq_rm.c:355
WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99
Definition: sciclient_irq_rm.c:257
MAIN_GPIOMUX_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
Definition: sciclient_irq_rm.c:171
tisci_if_DMASS0_INTAGGR_0
const struct Sciclient_rmIrqIf *const tisci_if_DMASS0_INTAGGR_0[]
Definition: sciclient_irq_rm.c:471
TISCI_DEV_TIMER3
#define TISCI_DEV_TIMER3
Definition: tisci_devices.h:88
MCASP3_rec_intr_pend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_186_186
const struct Sciclient_rmIrqIf MCASP3_rec_intr_pend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_186_186
Definition: sciclient_irq_rm.c:1072
vint_usage_count_DMASS1_INTAGGR_0
uint8_t vint_usage_count_DMASS1_INTAGGR_0[40]
Definition: sciclient_irq_rm.c:62
TISCI_DEV_WKUP_TIMER0
#define TISCI_DEV_WKUP_TIMER0
Definition: tisci_devices.h:134
MCASP3_xmit_intr_pend_1_1_to_MAIN_GPIOMUX_INTROUTER0_in_187_187
const struct Sciclient_rmIrqIf MCASP3_xmit_intr_pend_1_1_to_MAIN_GPIOMUX_INTROUTER0_in_187_187
Definition: sciclient_irq_rm.c:1078
MCASP4_rec_intr_pend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_188_188
const struct Sciclient_rmIrqIf MCASP4_rec_intr_pend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_188_188
Definition: sciclient_irq_rm.c:1095
DMASS1_INTAGGR_0_intaggr_vintr_pend_8_11_to_WKUP_R5FSS0_CORE0_intr_129_132
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_8_11_to_WKUP_R5FSS0_CORE0_intr_129_132
Definition: sciclient_irq_rm.c:946
MCU_TIMER2_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_172_172
const struct Sciclient_rmIrqIf MCU_TIMER2_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_172_172
Definition: sciclient_irq_rm.c:678
tisci_if_MCASP3
const struct Sciclient_rmIrqIf *const tisci_if_MCASP3[]
Definition: sciclient_irq_rm.c:1084
DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_R5FSS0_CORE0_cpu0_intr_64_79
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_R5FSS0_CORE0_cpu0_intr_64_79
Definition: sciclient_irq_rm.c:465
DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_GICSS0_spi_237_244
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_GICSS0_spi_237_244
Definition: sciclient_irq_rm.c:928
DMASS1_INTAGGR_0_intaggr_vintr_pend_20_20_to_MCU_R5FSS0_CORE0_cpu0_intr_150_150
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_20_20_to_MCU_R5FSS0_CORE0_cpu0_intr_150_150
Definition: sciclient_irq_rm.c:1012
DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
Definition: sciclient_irq_rm.c:411
TIMER3_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_165_165
const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_165_165
Definition: sciclient_irq_rm.c:575
TISCI_DEV_DSS1
#define TISCI_DEV_DSS1
Definition: tisci_devices.h:236
PCIE0_pcie_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_1_1
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_1_1
Definition: sciclient_irq_rm.c:1134
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_WKUP_R5FSS0_CORE0_intr_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_WKUP_R5FSS0_CORE0_intr_32_47
Definition: sciclient_irq_rm.c:129
TIMER2_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_164_164
const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_164_164
Definition: sciclient_irq_rm.c:552
TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
Definition: sciclient_irq_rm.c:535
MAIN_GPIOMUX_INTROUTER0_outp_20_21_to_R5FSS0_CORE0_intr_56_57
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_20_21_to_R5FSS0_CORE0_intr_56_57
Definition: sciclient_irq_rm.c:153
PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_4_4
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_4_4
Definition: sciclient_irq_rm.c:1140
tisci_if_CPSW0
const struct Sciclient_rmIrqIf *const tisci_if_CPSW0[]
Definition: sciclient_irq_rm.c:398
MAIN_GPIOMUX_INTROUTER0_outp_0_7_to_HSM0_nvic_208_215
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_7_to_HSM0_nvic_208_215
Definition: sciclient_irq_rm.c:147
TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_163_163
const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_163_163
Definition: sciclient_irq_rm.c:529
TIMER6_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_168_168
const struct Sciclient_rmIrqIf TIMER6_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_168_168
Definition: sciclient_irq_rm.c:630
MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31
const struct Sciclient_rmIrqIf MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31
Definition: sciclient_irq_rm.c:872
TISCI_DEV_TIMESYNC_EVENT_INTROUTER0
#define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0
Definition: tisci_devices.h:63
TISCI_DEV_TIMER6
#define TISCI_DEV_TIMER6
Definition: tisci_devices.h:91
TISCI_DEV_TIMER7
#define TISCI_DEV_TIMER7
Definition: tisci_devices.h:92
rom_usage_DMASS1_INTAGGR_0
static struct Sciclient_rmIaUsedMapping rom_usage_DMASS1_INTAGGR_0[1U]
Definition: sciclient_irq_rm.c:56
TISCI_DEV_MCU_GPIO0
#define TISCI_DEV_MCU_GPIO0
Definition: tisci_devices.h:115
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
Definition: sciclient_irq_rm.c:123
TISCI_DEV_WKUP_R5FSS0_CORE0
#define TISCI_DEV_WKUP_R5FSS0_CORE0
Definition: tisci_devices.h:141
WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_R5FSS0_CORE0_cpu0_intr_104_107
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_R5FSS0_CORE0_cpu0_intr_104_107
Definition: sciclient_irq_rm.c:233
tisci_if_MCU_TIMER2
const struct Sciclient_rmIrqIf *const tisci_if_MCU_TIMER2[]
Definition: sciclient_irq_rm.c:684
MAIN_GPIOMUX_INTROUTER0_outp_34_35_to_MCU_R5FSS0_CORE0_cpu0_intr_32_33
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_34_35_to_MCU_R5FSS0_CORE0_cpu0_intr_32_33
Definition: sciclient_irq_rm.c:183
TISCI_DEV_GICSS0
#define TISCI_DEV_GICSS0
Definition: tisci_devices.h:112
CPSW0_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_0
const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_0
Definition: sciclient_irq_rm.c:374
TISCI_DEV_GPIO0
#define TISCI_DEV_GPIO0
Definition: tisci_devices.h:113
WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V1_CLEC_gic_spi_104_107
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V1_CLEC_gic_spi_104_107
Definition: sciclient_irq_rm.c:227
TISCI_DEV_C7X256V0_CLEC
#define TISCI_DEV_C7X256V0_CLEC
Definition: tisci_devices.h:216
WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_11_11
const struct Sciclient_rmIrqIf WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_11_11
Definition: sciclient_irq_rm.c:710
tisci_if_WKUP_TIMER0
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_TIMER0[]
Definition: sciclient_irq_rm.c:840
DMASS1_INTAGGR_0_intaggr_vintr_pend_22_22_to_R5FSS0_CORE0_intr_160_160
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_22_22_to_R5FSS0_CORE0_intr_160_160
Definition: sciclient_irq_rm.c:1000
TISCI_DEV_MCASP4
#define TISCI_DEV_MCASP4
Definition: tisci_devices.h:258
TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
Definition: sciclient_irq_rm.c:512
MAIN_GPIOMUX_INTROUTER0_outp_16_19_to_R5FSS0_CORE0_intr_104_107
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_16_19_to_R5FSS0_CORE0_intr_104_107
Definition: sciclient_irq_rm.c:165
TISCI_DEV_MCU_TIMER3
#define TISCI_DEV_MCU_TIMER3
Definition: tisci_devices.h:95
TISCI_DEV_I2C4
#define TISCI_DEV_I2C4
Definition: tisci_devices.h:259
TISCI_DEV_HSM0
#define TISCI_DEV_HSM0
Definition: tisci_devices.h:229
DMASS1_INTAGGR_0_intaggr_vintr_pend_16_19_to_MCU_R5FSS0_CORE0_cpu0_intr_129_132
const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_16_19_to_MCU_R5FSS0_CORE0_cpu0_intr_129_132
Definition: sciclient_irq_rm.c:1006
TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
Definition: sciclient_irq_rm.c:558
TISCI_DEV_DMASS1_INTAGGR_0
#define TISCI_DEV_DMASS1_INTAGGR_0
Definition: tisci_devices.h:206
tisci_if_I2C4
const struct Sciclient_rmIrqIf *const tisci_if_I2C4[]
Definition: sciclient_irq_rm.c:1124
TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_CPSW0_cpts_hw4_push_3_3
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_CPSW0_cpts_hw4_push_3_3
Definition: sciclient_irq_rm.c:325
TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0
#define TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0
Definition: tisci_devices.h:62
TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_CPSW0_cpts_hw3_push_2_2
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_CPSW0_cpts_hw3_push_2_2
Definition: sciclient_irq_rm.c:319
TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_CPSW0_cpts_hw2_push_1_1
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_CPSW0_cpts_hw2_push_1_1
Definition: sciclient_irq_rm.c:313
tisci_if_WKUP_GTC0
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_GTC0[]
Definition: sciclient_irq_rm.c:716
DMASS0_INTAGGR_0_intaggr_vintr_pend_100_115_to_C7X256V1_CLEC_soc_events_in_16_31
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_100_115_to_C7X256V1_CLEC_soc_events_in_16_31
Definition: sciclient_irq_rm.c:435
WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_HSM0_nvic_78_81
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_HSM0_nvic_78_81
Definition: sciclient_irq_rm.c:239
TISCI_DEV_WKUP_TIMER1
#define TISCI_DEV_WKUP_TIMER1
Definition: tisci_devices.h:135
TISCI_DEV_GPMC0
#define TISCI_DEV_GPMC0
Definition: tisci_devices.h:116
tisci_if_DEBUGSS0
const struct Sciclient_rmIrqIf *const tisci_if_DEBUGSS0[]
Definition: sciclient_irq_rm.c:895
WKUP_MCU_GPIOMUX_INTROUTER0_outp_12_13_to_R5FSS0_CORE0_intr_32_33
const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_12_13_to_R5FSS0_CORE0_intr_32_33
Definition: sciclient_irq_rm.c:263
tisci_if_TIMER3
const struct Sciclient_rmIrqIf *const tisci_if_TIMER3[]
Definition: sciclient_irq_rm.c:587
TISCI_DEV_TIMER5
#define TISCI_DEV_TIMER5
Definition: tisci_devices.h:90
TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_CPSW0_cpts_hw5_push_4_4
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_CPSW0_cpts_hw5_push_4_4
Definition: sciclient_irq_rm.c:331
MCU_TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_170_170
const struct Sciclient_rmIrqIf MCU_TIMER0_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_170_170
Definition: sciclient_irq_rm.c:490
vint_usage_count_DMASS0_INTAGGR_0
uint8_t vint_usage_count_DMASS0_INTAGGR_0[184U]
Definition: sciclient_irq_rm.c:54
CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
Definition: sciclient_irq_rm.c:380
CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
Definition: sciclient_irq_rm.c:392
GPIO0_gpio_bank_92_97_to_MAIN_GPIOMUX_INTROUTER0_in_190_195
const struct Sciclient_rmIrqIf GPIO0_gpio_bank_92_97_to_MAIN_GPIOMUX_INTROUTER0_in_190_195
Definition: sciclient_irq_rm.c:738
MCRC64_0_int_mcrc_4_4_to_DMASS0_INTAGGR_0_intaggr_levi_pend_7_7
const struct Sciclient_rmIrqIf MCRC64_0_int_mcrc_4_4_to_DMASS0_INTAGGR_0_intaggr_levi_pend_7_7
Definition: sciclient_irq_rm.c:866
I2C4_pointrpend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_178_178
const struct Sciclient_rmIrqIf I2C4_pointrpend_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_178_178
Definition: sciclient_irq_rm.c:1118
tisci_if_MCU_TIMER0
const struct Sciclient_rmIrqIf *const tisci_if_MCU_TIMER0[]
Definition: sciclient_irq_rm.c:496
TISCI_DEV_GPIO1
#define TISCI_DEV_GPIO1
Definition: tisci_devices.h:114
tisci_if_TIMER5
const struct Sciclient_rmIrqIf *const tisci_if_TIMER5[]
Definition: sciclient_irq_rm.c:620
WKUP_TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_175_175
const struct Sciclient_rmIrqIf WKUP_TIMER1_timer_pwm_0_0_to_MAIN_GPIOMUX_INTROUTER0_in_175_175
Definition: sciclient_irq_rm.c:850