For more details and example usage, see Cache
Data Structures | |
struct | CacheP_Config |
Cache config structure, this used by SysConfig and not to be used by end-users directly. More... | |
Functions | |
void | CacheP_enable (uint32_t type) |
Cache enable. More... | |
void | CacheP_disable (uint32_t type) |
Cache disable. More... | |
uint32_t | CacheP_getEnabled (void) |
Get cache enabled bits. More... | |
void | CacheP_wbAll (uint32_t type) |
Cache writeback for full cache. More... | |
void | CacheP_wbInvAll (uint32_t type) |
Cache writeback and invalidate for full cache. More... | |
void | CacheP_wb (void *addr, uint32_t size, uint32_t type) |
Cache writeback for a specified region. More... | |
void | CacheP_inv (void *addr, uint32_t size, uint32_t type) |
Cache invalidate for a specified region. More... | |
void | CacheP_wbInv (void *addr, uint32_t size, uint32_t type) |
Cache writeback and invalidate for a specified region. More... | |
void | CacheP_init (void) |
Initialize Cache sub-system, called by SysConfig, not to be called by end users. More... | |
void | CacheP_invL1dAll () |
Invalidates all in data cache. More... | |
void | CacheP_invL1pAll () |
Invalidates all in instruction cache. More... | |
uint32_t | CacheP_armR5GetIcacheLineSize (void) |
Get the instruction cache line size This function is used to get the instruction cache line size for MCU. Implementation of this API/code is use-case specific. More... | |
void | CacheP_armR5InvalidateIcacheMva (uint32_t address) |
Invalidate an instruction cache line by MVA This function is used to invalidate an instruction cache Line by MVA. More... | |
void | CacheP_armR5InvalidateDcacheSetWay (uint32_t set, uint32_t way) |
Invalidate a data cache line by set and way. More... | |
void | CacheP_armR5CleanDcacheSetWay (uint32_t set, uint32_t way) |
Clean a data cache line by set and way. More... | |
void | CacheP_armR5CleanInvalidateDcacheSetWay (uint32_t set, uint32_t way) |
Clean and invalidate a data cache line by set and way. More... | |
void | CacheP_armR5DisableEcc (void) |
Disable ECC (parity) checking on cache rams. More... | |
void | CacheP_armR5EnableAxiAccess (void) |
Enable AXI slave access to cache RAM. More... | |
Macros | |
#define | CacheP_CACHELINE_ALIGNMENT (128U) |
Cache line size for alignment of buffers. Actual CPU defined cache line can be smaller that this value, this define is a utility macro to keep application portable across different CPU's. More... | |
Cache Type | |
Values defined for CacheP types | |
#define | CacheP_TYPE_L1P (0x0001u) |
#define | CacheP_TYPE_L1D (0x0002u) |
#define | CacheP_TYPE_L2P (0x0004u) |
#define | CacheP_TYPE_L2D (0x0008u) |
#define | CacheP_TYPE_L1 ((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D)) |
#define | CacheP_TYPE_L2 ((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D)) |
#define | CacheP_TYPE_ALLP ((CacheP_TYPE_L1P)|(CacheP_TYPE_L2P)) |
#define | CacheP_TYPE_ALLD ((CacheP_TYPE_L1D)|(CacheP_TYPE_L2D)) |
#define | CacheP_TYPE_ALL (((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D))|((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D))) |
#define CacheP_CACHELINE_ALIGNMENT (128U) |
Cache line size for alignment of buffers. Actual CPU defined cache line can be smaller that this value, this define is a utility macro to keep application portable across different CPU's.
#define CacheP_TYPE_L1P (0x0001u) |
L1 program cache
#define CacheP_TYPE_L1D (0x0002u) |
L1 data cache
#define CacheP_TYPE_L2P (0x0004u) |
L2 program cache
#define CacheP_TYPE_L2D (0x0008u) |
L2 data cache
#define CacheP_TYPE_L1 ((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D)) |
All L1 cache's
#define CacheP_TYPE_L2 ((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D)) |
All L2 cache's
#define CacheP_TYPE_ALLP ((CacheP_TYPE_L1P)|(CacheP_TYPE_L2P)) |
All program cache's
#define CacheP_TYPE_ALLD ((CacheP_TYPE_L1D)|(CacheP_TYPE_L2D)) |
All data cache's
#define CacheP_TYPE_ALL (((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D))|((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D))) |
All cache's
void CacheP_enable | ( | uint32_t | type | ) |
Cache enable.
type | [in] cache type's to enable R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_disable | ( | uint32_t | type | ) |
Cache disable.
type | [in] cache type's to disable R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
uint32_t CacheP_getEnabled | ( | void | ) |
Get cache enabled bits.
void CacheP_wbAll | ( | uint32_t | type | ) |
Cache writeback for full cache.
type | [in] cache type's to writeback R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_wbInvAll | ( | uint32_t | type | ) |
Cache writeback and invalidate for full cache.
type | [in] cache type's to writeback and invalidate R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_wb | ( | void * | addr, |
uint32_t | size, | ||
uint32_t | type | ||
) |
Cache writeback for a specified region.
addr | [in] region address. Recommend to specify address that is cache line aligned |
size | [in] region size in bytes. Recommend to specify size that is multiple of cache line size |
type | [in] cache type's to writeback R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_inv | ( | void * | addr, |
uint32_t | size, | ||
uint32_t | type | ||
) |
Cache invalidate for a specified region.
addr | [in] region address. Recommend to specify address that is cache line aligned |
size | [in] region size in bytes. Recommend to specify size that is multiple of cache line size |
type | [in] cache type's to invalidate R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_wbInv | ( | void * | addr, |
uint32_t | size, | ||
uint32_t | type | ||
) |
Cache writeback and invalidate for a specified region.
addr | [in] region address. Recommend to specify address that is cache line aligned |
size | [in] region size in bytes. Recommend to specify size that is multiple of cache line size |
type | [in] cache type's to writeback and invalidate R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_init | ( | void | ) |
Initialize Cache sub-system, called by SysConfig, not to be called by end users.
void CacheP_invL1dAll | ( | ) |
Invalidates all in data cache.
void CacheP_invL1pAll | ( | ) |
Invalidates all in instruction cache.
uint32_t CacheP_armR5GetIcacheLineSize | ( | void | ) |
Get the instruction cache line size This function is used to get the instruction cache line size for MCU. Implementation of this API/code is use-case specific.
void CacheP_armR5InvalidateIcacheMva | ( | uint32_t | address | ) |
Invalidate an instruction cache line by MVA This function is used to invalidate an instruction cache Line by MVA.
address | [IN] Modified virtual address |
void CacheP_armR5InvalidateDcacheSetWay | ( | uint32_t | set, |
uint32_t | way | ||
) |
Invalidate a data cache line by set and way.
This function is used to invalidate a data cache line by set and way.
set | [IN] Indicates the cache set to invalidate |
way | [IN] Indicates the cache way to invalidate |
void CacheP_armR5CleanDcacheSetWay | ( | uint32_t | set, |
uint32_t | way | ||
) |
Clean a data cache line by set and way.
This function is used to clean a data cache line by set and way.
set | [IN] Indicates the cache set to clean |
way | [IN] Indicates the cache way to clean |
void CacheP_armR5CleanInvalidateDcacheSetWay | ( | uint32_t | set, |
uint32_t | way | ||
) |
Clean and invalidate a data cache line by set and way.
This function is used to clean and invalidate a data cache line by set and way.
set | [IN] Indicates the cache set to clean and invalidate |
way | [IN] Indicates the cache way to clean and invalidate |
void CacheP_armR5DisableEcc | ( | void | ) |
Disable ECC (parity) checking on cache rams.
This function is used to disable ECC (parity) checking on cache rams.
void CacheP_armR5EnableAxiAccess | ( | void | ) |
Enable AXI slave access to cache RAM.
This function is used to enable AXI slave access to cache RAM.
|
extern |
Externally defined Cache configuration.