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J722S MCU+ SDK
09.02.00
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Go to the documentation of this file.
41 #ifndef SCICLIENT_FMWMSGPARAMS_H_
42 #define SCICLIENT_FMWMSGPARAMS_H_
59 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU)
69 #define SCICLIENT_FIRMWARE_ABI_MAJOR (3U)
74 #define SCICLIENT_FIRMWARE_ABI_MINOR (1U)
84 #define SCICLIENT_CONTEXT_WKUP_R5_SEC_0 (0U)
86 #define SCICLIENT_CONTEXT_WKUP_R5_NONSEC_0 (1U)
88 #define SCICLIENT_CONTEXT_MAIN_R5_SEC_0 (2U)
90 #define SCICLIENT_CONTEXT_MAIN_R5_NONSEC_0 (3U)
92 #define SCICLIENT_CONTEXT_A53_SEC_0 (4U)
94 #define SCICLIENT_CONTEXT_A53_SEC_1 (5U)
96 #define SCICLIENT_CONTEXT_A53_NONSEC_0 (6U)
98 #define SCICLIENT_CONTEXT_A53_NONSEC_1 (7U)
100 #define SCICLIENT_CONTEXT_A53_NONSEC_2 (8U)
102 #define SCICLIENT_CONTEXT_MCU_R5_0_NONSEC_0 (9U)
104 #define SCICLIENT_CONTEXT_C7X_NONSEC_0 (10U)
106 #define SCICLIENT_CONTEXT_C7X_NONSEC_1 (11U)
108 #define SCICLIENT_CONTEXT_GPU_NONSEC_0 (12U)
110 #define SCICLIENT_CONTEXT_GPU_NONSEC_1 (13U)
113 #define SCICLIENT_CONTEXT_MAX_NUM (14U)
125 #define SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)
130 #define SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)
135 #define SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)
140 #define SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)
145 #define SCICLIENT_PROC_ID_C7X256V0_C7XV_CORE_0 (0x30U)
150 #define SCICLIENT_PROC_ID_C7X256V1_C7XV_CORE_0 (0x31U)
155 #define SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)
160 #define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0 (0x03U)
165 #define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x04U)
170 #define SCICLIENT_PROC_ID_WKUP_R5FSS0_CORE0 (0x01U)
175 #define SCICLIENT_SOC_NUM_PROCESSORS (0x0AU)
180 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)
181 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)
182 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)
183 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)
189 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)
190 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)
191 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)
192 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)
193 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)
217 #define TISCI_ISC_CC_ID (160U)
226 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U)
227 #define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START (4096U)
228 #define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)
229 #define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START (5120U)
230 #define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)
231 #define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U)
232 #define TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START (6656U)
233 #define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (8192U)
234 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)
235 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)
236 #define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (9728U)
237 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)
238 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)
239 #define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (11264U)
240 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)
241 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)
242 #define TISCI_BCDMA1_TX_EOES_IRQ_SRC_IDX_START (1536U)
243 #define TISCI_BCDMA1_TX_DC_OES_IRQ_SRC_IDX_START (2048U)
244 #define TISCI_BCDMA1_TX_RC_OES_IRQ_SRC_IDX_START (2560U)
245 #define TISCI_BCDMA1_RX_EOES_IRQ_SRC_IDX_START (3072U)
246 #define TISCI_BCDMA1_RX_DC_OES_IRQ_SRC_IDX_START (3584U)
247 #define TISCI_BCDMA1_RX_RC_OES_IRQ_SRC_IDX_START (4096U)
251 #define SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U)
252 #define SCICLIENT_C7X_SECURE_INTERRUPT_NUM (10U)
253 #define SCICLIENT_C7X_0_CLEC_EVENT_IN (CSLR_C7X256V0_CLEC_SOC_EVENTS_IN_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_84)
254 #define SCICLIENT_C7X_1_CLEC_EVENT_IN (CSLR_C7X256V1_CLEC_SOC_EVENTS_IN_DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_100)
262 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0)
263 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0)
272 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID \
273 (SCICLIENT_PROC_ID_WKUP_R5FSS0_CORE0)
274 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID \
275 (SCICLIENT_PROC_ID_WKUP_R5FSS0_CORE0)
279 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1
281 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFF