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J722S MCU+ SDK
09.02.00
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46 #ifndef SDL_ARM_R5_PMU_H
47 #define SDL_ARM_R5_PMU_H
180 typedef struct SDL_PMU_staticReg_read
199 #define SDL_ARM_R5_PMU_CYCLE_COUNTER_NUM (31U)
202 #define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_MASK (0x000000FFU)
203 #define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_SHIFT (0x00000000U)
204 #define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_RESETVAL (0x00000000U)
205 #define SDL_ARM_R5_PMU_CFG_CNTR_EVENT_TYPE_MAX (0x000000FFU)
239 extern void SDL_R5PMU_cfg( uint32_t cycleCntDiv, uint32_t exportEvents, uint32_t userEnable );
@ SDL_ARM_R5_PMU_EVENT_TYPE_PROC_RET
Definition: sdl_arm_r5_pmu.h:110
void SDL_R5PMU_setResetCntr(uint32_t cntrNum, uint32_t cntrVal)
Set a PMU counter.
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_PF
Definition: sdl_arm_r5_pmu.h:128
@ SDL_ARM_R5_PMU_EVENT_TYPE_PI_X
Definition: sdl_arm_r5_pmu.h:104
@ SDL_ARM_R5_PMU_EVENT_TYPE_ATCM_MB_ECC
Definition: sdl_arm_r5_pmu.h:147
@ SDL_ARM_R5_PMU_EVENT_TYPE_FIQ_DISABLED_CYCLES
Definition: sdl_arm_r5_pmu.h:120
@ SDL_ARM_R5_PMU_EVENT_TYPE_D_WR
Definition: sdl_arm_r5_pmu.h:102
@ SDL_ARM_R5_PMU_EVENT_TYPE_B1TCM_SB_ECC
Definition: sdl_arm_r5_pmu.h:152
@ SDL_ARM_R5_PMU_EVENT_TYPE_ETMEXTOUTM0
Definition: sdl_arm_r5_pmu.h:122
SDL_R5PmuEventType
This enumerator defines PMU event types.
Definition: sdl_arm_r5_pmu.h:96
PMU Static Registers structure.
Definition: sdl_arm_r5_pmu.h:181
@ SDL_ARM_R5_PMU_EVENT_TYPE_B0TCM_MB_ECC
Definition: sdl_arm_r5_pmu.h:148
uint8_t exportEvents
Definition: sdl_arm_r5_pmu.h:184
uint32_t SDL_R5PMU_readCntr(uint32_t cntrNum)
Read a PMU counter.
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_MISS
Definition: sdl_arm_r5_pmu.h:98
@ SDL_ARM_R5_PMU_EVENT_TYPE_BRANCH_PRED
Definition: sdl_arm_r5_pmu.h:113
@ SDL_ARM_R5_PMU_EVENT_TYPE_CORRECTABLE_BUS_FAULTS
Definition: sdl_arm_r5_pmu.h:159
@ SDL_ARM_R5_PMU_EVENT_TYPE_SWINC
Definition: sdl_arm_r5_pmu.h:97
@ SDL_ARM_R5_PMU_EVENT_TYPE_ACP_DCACHE_ACCESS
Definition: sdl_arm_r5_pmu.h:161
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_TAG_CECC
Definition: sdl_arm_r5_pmu.h:126
@ SDL_ARM_R5_PMU_EVENT_TYPE_INT_DIV
Definition: sdl_arm_r5_pmu.h:133
@ SDL_ARM_R5_PMU_EVENT_TYPE_CID_CHANGE
Definition: sdl_arm_r5_pmu.h:107
uint32_t SDL_R5PMU_getNumCntrs(void)
Get the number of PMU counters supported.
@ SDL_ARM_R5_PMU_EVENT_TYPE_IRQ_DISABLED_CYCLES
Definition: sdl_arm_r5_pmu.h:121
uint8_t userEnable
Definition: sdl_arm_r5_pmu.h:186
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_PF
Definition: sdl_arm_r5_pmu.h:154
void SDL_R5PMU_resetCycleCnt(void)
Reset the cycle counter to zero.
@ SDL_ARM_R5_PMU_EVENT_TYPE_PLD_LINEFILL
Definition: sdl_arm_r5_pmu.h:135
@ SDL_ARM_R5_PMU_EVENT_TYPE_PLD_NO_LINEFILL
Definition: sdl_arm_r5_pmu.h:136
@ SDL_ARM_R5_PMU_EVENT_TYPE_ACP_DCACHE_INVALIDATE
Definition: sdl_arm_r5_pmu.h:162
uint8_t cycleCntDiv
Definition: sdl_arm_r5_pmu.h:182
@ SDL_ARM_R5_PMU_EVENT_TYPE_LIVELOCK
Definition: sdl_arm_r5_pmu.h:146
@ SDL_ARM_R5_PMU_EVENT_TYPE_D_RD
Definition: sdl_arm_r5_pmu.h:101
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_STALL
Definition: sdl_arm_r5_pmu.h:114
void SDL_R5PMU_enableCntrOverflowIntr(uint32_t cntrNum, uint32_t enable)
Enable/disable overflow interrupt generation for a PMU counter.
@ SDL_ARM_R5_PMU_EVENT_TYPE_SB_ATTR
Definition: sdl_arm_r5_pmu.h:139
int32_t SDL_R5PMU_verifyCfg(uint32_t cycleCntDiv, uint32_t exportEvents)
Configure the Performance Management Unit (PMU)
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_ACCESS
Definition: sdl_arm_r5_pmu.h:138
@ SDL_ARM_R5_PMU_EVENT_TYPE_SW_PC
Definition: sdl_arm_r5_pmu.h:108
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_LS
Definition: sdl_arm_r5_pmu.h:129
@ SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_A
Definition: sdl_arm_r5_pmu.h:140
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_WB
Definition: sdl_arm_r5_pmu.h:116
void SDL_R5PMU_cfg(uint32_t cycleCntDiv, uint32_t exportEvents, uint32_t userEnable)
Configure the Performance Management Unit (PMU)
void SDL_R5PMU_clearCntrOverflowStatus(uint32_t cntrMask)
Clear the overflow flag for the specified counter(s)
@ SDL_ARM_R5_PMU_EVENT_TYPE_BRANCH_TAKEN
Definition: sdl_arm_r5_pmu.h:112
@ SDL_ARM_R5_PMU_EVENT_TYPE_INT_DIV_STALL
Definition: sdl_arm_r5_pmu.h:134
@ SDL_ARM_R5_PMU_EVENT_TYPE_CORRECTABLE_EVENTS
Definition: sdl_arm_r5_pmu.h:157
@ SDL_ARM_R5_PMU_EVENT_TYPE_FATAL_BUS_FAULTS
Definition: sdl_arm_r5_pmu.h:160
@ SDL_ARM_R5_PMU_EVENT_TYPE_SB_DRAIN
Definition: sdl_arm_r5_pmu.h:119
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_LS
Definition: sdl_arm_r5_pmu.h:153
@ SDL_ARM_R5_PMU_EVENT_TYPE_EXCEPTION_RET
Definition: sdl_arm_r5_pmu.h:106
@ SDL_ARM_R5_PMU_EVENT_TYPE_UNALIGNED_ACCESS
Definition: sdl_arm_r5_pmu.h:111
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_TAG_CECC
Definition: sdl_arm_r5_pmu.h:124
@ SDL_ARM_R5_PMU_EVENT_TYPE_LSU_QF_STALL
Definition: sdl_arm_r5_pmu.h:132
void SDL_R5PMU_cfgCntr(uint32_t cntrNum, SDL_R5PmuEventType eventType)
Configure a PMU counter.
@ SDL_ARM_R5_PMU_EVENT_TYPE_CYCLE_CNT
Definition: sdl_arm_r5_pmu.h:163
@ SDL_ARM_R5_PMU_EVENT_TYPE_DOUBLE_FP
Definition: sdl_arm_r5_pmu.h:143
uint32_t cntEnableSetReg
Definition: sdl_arm_r5_pmu.h:188
@ SDL_ARM_R5_PMU_EVENT_TYPE_B0TCM_SB_ECC
Definition: sdl_arm_r5_pmu.h:151
@ SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_B
Definition: sdl_arm_r5_pmu.h:141
@ SDL_ARM_R5_PMU_EVENT_TYPE_LSU_BUSY_STALL
Definition: sdl_arm_r5_pmu.h:118
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_ACCESS
Definition: sdl_arm_r5_pmu.h:100
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_DATA_FECC
Definition: sdl_arm_r5_pmu.h:144
@ SDL_ARM_R5_PMU_EVENT_TYPE_ATCM_SB_ECC
Definition: sdl_arm_r5_pmu.h:150
@ SDL_ARM_R5_PMU_EVENT_TYPE_B_IMMEDIATE
Definition: sdl_arm_r5_pmu.h:109
@ SDL_ARM_R5_PMU_EVENT_TYPE_ETMEXTOUTM1
Definition: sdl_arm_r5_pmu.h:123
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_TAG_FECC
Definition: sdl_arm_r5_pmu.h:145
@ SDL_ARM_R5_PMU_EVENT_TYPE_DUAL_ISSUE_CASE_OTHER
Definition: sdl_arm_r5_pmu.h:142
@ SDL_ARM_R5_PMU_EVENT_TYPE_SB_MERGE
Definition: sdl_arm_r5_pmu.h:130
@ SDL_ARM_R5_PMU_EVENT_TYPE_ICACHE_DATA_CECC
Definition: sdl_arm_r5_pmu.h:125
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_MISS
Definition: sdl_arm_r5_pmu.h:99
void SDL_R5PMU_enableCntr(uint32_t cntrNum, uint32_t enable)
Enable/disable a PMU counter.
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_CECC_AXI
Definition: sdl_arm_r5_pmu.h:156
void SDL_R5PMU_enableAllCntrs(uint32_t enable)
Enable/disable all PMU counters.
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_DATA_CECC
Definition: sdl_arm_r5_pmu.h:127
@ SDL_ARM_R5_PMU_EVENT_TYPE_B1TCM_MB_ECC
Definition: sdl_arm_r5_pmu.h:149
@ SDL_ARM_R5_PMU_EVENT_TYPE_LSU_SB_STALL
Definition: sdl_arm_r5_pmu.h:131
@ SDL_ARM_R5_PMU_EVENT_TYPE_I_X
Definition: sdl_arm_r5_pmu.h:103
@ SDL_ARM_R5_PMU_EVENT_TYPE_DCACHE_STALL
Definition: sdl_arm_r5_pmu.h:115
@ SDL_ARM_R5_PMU_EVENT_TYPE_FATAL_EVENTS
Definition: sdl_arm_r5_pmu.h:158
@ SDL_ARM_R5_PMU_EVENT_TYPE_NONCACHEABLE_ACCESS
Definition: sdl_arm_r5_pmu.h:137
@ SDL_ARM_R5_PMU_EVENT_TYPE_EXCEPTION
Definition: sdl_arm_r5_pmu.h:105
void SDL_R5PMU_resetCntrs(void)
Reset all counters to zero.
@ SDL_ARM_R5_PMU_EVENT_TYPE_TCM_FECC_AXI
Definition: sdl_arm_r5_pmu.h:155
void SDL_R5PMU_readStaticRegisters(SDL_PMU_staticRegs *pStaticRegs)
PMU API to Read the Static Registers. This function reads the values of the static registers such as ...
@ SDL_ARM_R5_PMU_EVENT_TYPE_MEM_REQ
Definition: sdl_arm_r5_pmu.h:117
uint32_t SDL_R5PMU_readCntrOverflowStatus(void)
Read the overflow status for all of the counters.