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J722S MCU+ SDK
09.02.00
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51 #ifndef SOC_J722S_CLOCKS_H
52 #define SOC_J722S_CLOCKS_H
60 #define TISCI_DEV_DPHY_RX0_IO_RX_CL_L_M 2
61 #define TISCI_DEV_DPHY_RX0_IO_RX_CL_L_P 3
62 #define TISCI_DEV_DPHY_RX0_JTAG_TCK 4
63 #define TISCI_DEV_DPHY_RX0_MAIN_CLK_CLK 5
64 #define TISCI_DEV_DPHY_RX0_PPI_RX_BYTE_CLK 6
66 #define TISCI_DEV_DPHY_RX1_IO_RX_CL_L_M 2
67 #define TISCI_DEV_DPHY_RX1_IO_RX_CL_L_P 3
68 #define TISCI_DEV_DPHY_RX1_JTAG_TCK 4
69 #define TISCI_DEV_DPHY_RX1_MAIN_CLK_CLK 5
70 #define TISCI_DEV_DPHY_RX1_PPI_RX_BYTE_CLK 6
72 #define TISCI_DEV_DPHY_RX2_IO_RX_CL_L_M 2
73 #define TISCI_DEV_DPHY_RX2_IO_RX_CL_L_P 3
74 #define TISCI_DEV_DPHY_RX2_JTAG_TCK 4
75 #define TISCI_DEV_DPHY_RX2_MAIN_CLK_CLK 5
76 #define TISCI_DEV_DPHY_RX2_PPI_RX_BYTE_CLK 6
78 #define TISCI_DEV_DPHY_RX3_IO_RX_CL_L_M 2
79 #define TISCI_DEV_DPHY_RX3_IO_RX_CL_L_P 3
80 #define TISCI_DEV_DPHY_RX3_JTAG_TCK 4
81 #define TISCI_DEV_DPHY_RX3_MAIN_CLK_CLK 5
82 #define TISCI_DEV_DPHY_RX3_PPI_RX_BYTE_CLK 6
84 #define TISCI_DEV_DBGSUSPENDROUTER0_INTR_CLK 0
86 #define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK 0
88 #define TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_CLK 0
90 #define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK 0
92 #define TISCI_DEV_ATL0_ATL_CLK 0
93 #define TISCI_DEV_ATL0_ATL_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
94 #define TISCI_DEV_ATL0_ATL_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
95 #define TISCI_DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK 3
96 #define TISCI_DEV_ATL0_ATL_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
97 #define TISCI_DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 6
98 #define TISCI_DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 7
99 #define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT 9
100 #define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 10
101 #define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 11
102 #define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 12
103 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS 13
104 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP0_AFSX_OUT 14
105 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP1_AFSX_OUT 15
106 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP2_AFSX_OUT 16
107 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP3_AFSX_OUT 17
108 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP4_AFSX_OUT 18
109 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 19
110 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 20
111 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 21
112 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 22
113 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 23
114 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 24
115 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 25
116 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 26
117 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1 30
118 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT 31
119 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT 32
120 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT 33
121 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT 34
122 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT 35
123 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 36
124 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 37
125 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 38
126 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 39
127 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 40
128 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 41
129 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 42
130 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 43
131 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2 53
132 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT 54
133 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT 55
134 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT 56
135 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT 57
136 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT 58
137 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 59
138 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 60
139 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 61
140 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 62
141 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 63
142 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 64
143 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 65
144 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 66
145 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3 70
146 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT 71
147 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT 72
148 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT 73
149 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT 74
150 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT 75
151 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 76
152 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 77
153 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 78
154 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 79
155 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 80
156 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 81
157 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 82
158 #define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 83
159 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS 93
160 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP0_AFSR_OUT 94
161 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP1_AFSR_OUT 95
162 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP2_AFSR_OUT 96
163 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP3_AFSR_OUT 97
164 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP4_AFSR_OUT 98
165 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP0_AFSX_OUT 99
166 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP1_AFSX_OUT 100
167 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP2_AFSX_OUT 101
168 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP3_AFSX_OUT 102
169 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP4_AFSX_OUT 103
170 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 104
171 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 105
172 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 106
173 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1 110
174 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP0_AFSR_OUT 111
175 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP1_AFSR_OUT 112
176 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP2_AFSR_OUT 113
177 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP3_AFSR_OUT 114
178 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP4_AFSR_OUT 115
179 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT 116
180 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT 117
181 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT 118
182 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT 119
183 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT 120
184 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 121
185 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 122
186 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 123
187 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2 133
188 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP0_AFSR_OUT 134
189 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP1_AFSR_OUT 135
190 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP2_AFSR_OUT 136
191 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP3_AFSR_OUT 137
192 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP4_AFSR_OUT 138
193 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT 139
194 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT 140
195 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT 141
196 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT 142
197 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT 143
198 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 144
199 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 145
200 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 146
201 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3 150
202 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP0_AFSR_OUT 151
203 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP1_AFSR_OUT 152
204 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP2_AFSR_OUT 153
205 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP3_AFSR_OUT 154
206 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP4_AFSR_OUT 155
207 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT 156
208 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT 157
209 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT 158
210 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT 159
211 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT 160
212 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 161
213 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 162
214 #define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 163
215 #define TISCI_DEV_ATL0_VBUS_CLK 173
217 #define TISCI_DEV_CPSW0_CPPI_CLK_CLK 0
218 #define TISCI_DEV_CPSW0_CPTS_GENF0 1
219 #define TISCI_DEV_CPSW0_CPTS_GENF1 2
220 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK 3
221 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK 4
222 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 5
223 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 6
224 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 8
225 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 9
226 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_1_IP1_LN0_TXMCLK 10
227 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK 11
228 #define TISCI_DEV_CPSW0_GMII1_MR_CLK 13
229 #define TISCI_DEV_CPSW0_GMII1_MT_CLK 14
230 #define TISCI_DEV_CPSW0_GMII2_MR_CLK 15
231 #define TISCI_DEV_CPSW0_GMII2_MT_CLK 16
232 #define TISCI_DEV_CPSW0_GMII_RFT_CLK 17
233 #define TISCI_DEV_CPSW0_MDIO_MDCLK_O 18
234 #define TISCI_DEV_CPSW0_RGMII_MHZ_250_CLK 19
235 #define TISCI_DEV_CPSW0_RGMII_MHZ_50_CLK 20
236 #define TISCI_DEV_CPSW0_RGMII_MHZ_5_CLK 21
237 #define TISCI_DEV_CPSW0_RMII1_MHZ_50_CLK 22
238 #define TISCI_DEV_CPSW0_RMII2_MHZ_50_CLK 23
239 #define TISCI_DEV_CPSW0_SERDES1_REFCLK 24
240 #define TISCI_DEV_CPSW0_SERDES1_RXCLK 25
241 #define TISCI_DEV_CPSW0_SERDES1_RXFCLK 26
242 #define TISCI_DEV_CPSW0_SERDES1_TXCLK 27
243 #define TISCI_DEV_CPSW0_SERDES1_TXFCLK 28
244 #define TISCI_DEV_CPSW0_SERDES1_TXMCLK 29
245 #define TISCI_DEV_CPSW0_SERDES2_REFCLK 30
246 #define TISCI_DEV_CPSW0_SERDES2_RXCLK 31
247 #define TISCI_DEV_CPSW0_SERDES2_RXFCLK 32
248 #define TISCI_DEV_CPSW0_SERDES2_TXCLK 33
249 #define TISCI_DEV_CPSW0_SERDES2_TXFCLK 34
250 #define TISCI_DEV_CPSW0_SERDES2_TXMCLK 35
252 #define TISCI_DEV_CPT2_AGGR1_VCLK_CLK 0
254 #define TISCI_DEV_CPT2_AGGR0_VCLK_CLK 0
256 #define TISCI_DEV_MCU_CPT2_AGGR0_VCLK_CLK 0
258 #define TISCI_DEV_CSI_RX_IF0_MAIN_CLK_CLK 0
259 #define TISCI_DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK 2
260 #define TISCI_DEV_CSI_RX_IF0_VBUS_CLK_CLK 3
261 #define TISCI_DEV_CSI_RX_IF0_VP_CLK_CLK 4
263 #define TISCI_DEV_CSI_RX_IF1_MAIN_CLK_CLK 0
264 #define TISCI_DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK 2
265 #define TISCI_DEV_CSI_RX_IF1_VBUS_CLK_CLK 3
266 #define TISCI_DEV_CSI_RX_IF1_VP_CLK_CLK 4
268 #define TISCI_DEV_CSI_RX_IF2_MAIN_CLK_CLK 0
269 #define TISCI_DEV_CSI_RX_IF2_PPI_RX_BYTE_CLK 2
270 #define TISCI_DEV_CSI_RX_IF2_VBUS_CLK_CLK 3
271 #define TISCI_DEV_CSI_RX_IF2_VP_CLK_CLK 4
273 #define TISCI_DEV_CSI_RX_IF3_MAIN_CLK_CLK 0
274 #define TISCI_DEV_CSI_RX_IF3_PPI_RX_BYTE_CLK 2
275 #define TISCI_DEV_CSI_RX_IF3_VBUS_CLK_CLK 3
276 #define TISCI_DEV_CSI_RX_IF3_VP_CLK_CLK 4
278 #define TISCI_DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK 2
279 #define TISCI_DEV_CSI_TX_IF0_ESC_CLK_CLK 3
280 #define TISCI_DEV_CSI_TX_IF0_MAIN_CLK_CLK 4
281 #define TISCI_DEV_CSI_TX_IF0_VBUS_CLK_CLK 5
283 #define TISCI_DEV_STM0_ATB_CLK 0
284 #define TISCI_DEV_STM0_CORE_CLK 1
285 #define TISCI_DEV_STM0_VBUSP_CLK 2
287 #define TISCI_DEV_DCC0_DCC_CLKSRC0_CLK 0
288 #define TISCI_DEV_DCC0_DCC_CLKSRC1_CLK 1
289 #define TISCI_DEV_DCC0_DCC_CLKSRC2_CLK 2
290 #define TISCI_DEV_DCC0_DCC_CLKSRC3_CLK 3
291 #define TISCI_DEV_DCC0_DCC_CLKSRC4_CLK 4
292 #define TISCI_DEV_DCC0_DCC_CLKSRC5_CLK 5
293 #define TISCI_DEV_DCC0_DCC_CLKSRC6_CLK 6
294 #define TISCI_DEV_DCC0_DCC_CLKSRC7_CLK 7
295 #define TISCI_DEV_DCC0_DCC_INPUT00_CLK 8
296 #define TISCI_DEV_DCC0_DCC_INPUT01_CLK 9
297 #define TISCI_DEV_DCC0_DCC_INPUT02_CLK 10
298 #define TISCI_DEV_DCC0_DCC_INPUT10_CLK 11
299 #define TISCI_DEV_DCC0_VBUS_CLK 12
301 #define TISCI_DEV_DCC1_DCC_CLKSRC0_CLK 0
302 #define TISCI_DEV_DCC1_DCC_CLKSRC1_CLK 1
303 #define TISCI_DEV_DCC1_DCC_CLKSRC2_CLK 2
304 #define TISCI_DEV_DCC1_DCC_CLKSRC3_CLK 3
305 #define TISCI_DEV_DCC1_DCC_CLKSRC4_CLK 4
306 #define TISCI_DEV_DCC1_DCC_CLKSRC5_CLK 5
307 #define TISCI_DEV_DCC1_DCC_CLKSRC6_CLK 6
308 #define TISCI_DEV_DCC1_DCC_CLKSRC7_CLK 7
309 #define TISCI_DEV_DCC1_DCC_INPUT00_CLK 8
310 #define TISCI_DEV_DCC1_DCC_INPUT01_CLK 9
311 #define TISCI_DEV_DCC1_DCC_INPUT02_CLK 10
312 #define TISCI_DEV_DCC1_DCC_INPUT10_CLK 11
313 #define TISCI_DEV_DCC1_VBUS_CLK 12
315 #define TISCI_DEV_DCC2_DCC_CLKSRC0_CLK 0
316 #define TISCI_DEV_DCC2_DCC_CLKSRC1_CLK 1
317 #define TISCI_DEV_DCC2_DCC_CLKSRC2_CLK 2
318 #define TISCI_DEV_DCC2_DCC_CLKSRC3_CLK 3
319 #define TISCI_DEV_DCC2_DCC_CLKSRC4_CLK 4
320 #define TISCI_DEV_DCC2_DCC_CLKSRC5_CLK 5
321 #define TISCI_DEV_DCC2_DCC_CLKSRC6_CLK 6
322 #define TISCI_DEV_DCC2_DCC_CLKSRC7_CLK 7
323 #define TISCI_DEV_DCC2_DCC_INPUT00_CLK 8
324 #define TISCI_DEV_DCC2_DCC_INPUT01_CLK 9
325 #define TISCI_DEV_DCC2_DCC_INPUT02_CLK 10
326 #define TISCI_DEV_DCC2_DCC_INPUT10_CLK 11
327 #define TISCI_DEV_DCC2_VBUS_CLK 12
329 #define TISCI_DEV_DCC3_DCC_CLKSRC0_CLK 0
330 #define TISCI_DEV_DCC3_DCC_CLKSRC1_CLK 1
331 #define TISCI_DEV_DCC3_DCC_CLKSRC2_CLK 2
332 #define TISCI_DEV_DCC3_DCC_CLKSRC3_CLK 3
333 #define TISCI_DEV_DCC3_DCC_CLKSRC4_CLK 4
334 #define TISCI_DEV_DCC3_DCC_CLKSRC5_CLK 5
335 #define TISCI_DEV_DCC3_DCC_CLKSRC6_CLK 6
336 #define TISCI_DEV_DCC3_DCC_CLKSRC7_CLK 7
337 #define TISCI_DEV_DCC3_DCC_INPUT00_CLK 8
338 #define TISCI_DEV_DCC3_DCC_INPUT01_CLK 9
339 #define TISCI_DEV_DCC3_DCC_INPUT02_CLK 10
340 #define TISCI_DEV_DCC3_DCC_INPUT10_CLK 11
341 #define TISCI_DEV_DCC3_VBUS_CLK 12
343 #define TISCI_DEV_DCC4_DCC_CLKSRC0_CLK 0
344 #define TISCI_DEV_DCC4_DCC_CLKSRC1_CLK 1
345 #define TISCI_DEV_DCC4_DCC_CLKSRC2_CLK 2
346 #define TISCI_DEV_DCC4_DCC_CLKSRC3_CLK 3
347 #define TISCI_DEV_DCC4_DCC_CLKSRC4_CLK 4
348 #define TISCI_DEV_DCC4_DCC_CLKSRC5_CLK 5
349 #define TISCI_DEV_DCC4_DCC_CLKSRC6_CLK 6
350 #define TISCI_DEV_DCC4_DCC_CLKSRC7_CLK 7
351 #define TISCI_DEV_DCC4_DCC_INPUT00_CLK 8
352 #define TISCI_DEV_DCC4_DCC_INPUT01_CLK 9
353 #define TISCI_DEV_DCC4_DCC_INPUT02_CLK 10
354 #define TISCI_DEV_DCC4_DCC_INPUT10_CLK 11
355 #define TISCI_DEV_DCC4_VBUS_CLK 12
357 #define TISCI_DEV_DCC5_DCC_CLKSRC0_CLK 0
358 #define TISCI_DEV_DCC5_DCC_CLKSRC1_CLK 1
359 #define TISCI_DEV_DCC5_DCC_CLKSRC2_CLK 2
360 #define TISCI_DEV_DCC5_DCC_CLKSRC3_CLK 3
361 #define TISCI_DEV_DCC5_DCC_CLKSRC4_CLK 4
362 #define TISCI_DEV_DCC5_DCC_CLKSRC5_CLK 5
363 #define TISCI_DEV_DCC5_DCC_CLKSRC6_CLK 6
364 #define TISCI_DEV_DCC5_DCC_CLKSRC7_CLK 7
365 #define TISCI_DEV_DCC5_DCC_INPUT00_CLK 8
366 #define TISCI_DEV_DCC5_DCC_INPUT01_CLK 9
367 #define TISCI_DEV_DCC5_DCC_INPUT02_CLK 10
368 #define TISCI_DEV_DCC5_DCC_INPUT10_CLK 11
369 #define TISCI_DEV_DCC5_VBUS_CLK 12
371 #define TISCI_DEV_DCC6_DCC_CLKSRC0_CLK 0
372 #define TISCI_DEV_DCC6_DCC_CLKSRC1_CLK 1
373 #define TISCI_DEV_DCC6_DCC_CLKSRC2_CLK 2
374 #define TISCI_DEV_DCC6_DCC_CLKSRC3_CLK 3
375 #define TISCI_DEV_DCC6_DCC_CLKSRC4_CLK 4
376 #define TISCI_DEV_DCC6_DCC_CLKSRC5_CLK 5
377 #define TISCI_DEV_DCC6_DCC_CLKSRC6_CLK 6
378 #define TISCI_DEV_DCC6_DCC_CLKSRC7_CLK 7
379 #define TISCI_DEV_DCC6_DCC_INPUT00_CLK 8
380 #define TISCI_DEV_DCC6_DCC_INPUT01_CLK 9
381 #define TISCI_DEV_DCC6_DCC_INPUT02_CLK 10
382 #define TISCI_DEV_DCC6_DCC_INPUT10_CLK 11
383 #define TISCI_DEV_DCC6_VBUS_CLK 12
385 #define TISCI_DEV_DCC7_DCC_CLKSRC0_CLK 0
386 #define TISCI_DEV_DCC7_DCC_CLKSRC1_CLK 1
387 #define TISCI_DEV_DCC7_DCC_CLKSRC2_CLK 2
388 #define TISCI_DEV_DCC7_DCC_CLKSRC3_CLK 3
389 #define TISCI_DEV_DCC7_DCC_CLKSRC4_CLK 4
390 #define TISCI_DEV_DCC7_DCC_CLKSRC5_CLK 5
391 #define TISCI_DEV_DCC7_DCC_CLKSRC6_CLK 6
392 #define TISCI_DEV_DCC7_DCC_CLKSRC7_CLK 7
393 #define TISCI_DEV_DCC7_DCC_INPUT00_CLK 8
394 #define TISCI_DEV_DCC7_DCC_INPUT01_CLK 9
395 #define TISCI_DEV_DCC7_DCC_INPUT02_CLK 10
396 #define TISCI_DEV_DCC7_DCC_INPUT10_CLK 11
397 #define TISCI_DEV_DCC7_VBUS_CLK 12
399 #define TISCI_DEV_DCC8_DCC_CLKSRC0_CLK 0
400 #define TISCI_DEV_DCC8_DCC_CLKSRC1_CLK 1
401 #define TISCI_DEV_DCC8_DCC_CLKSRC2_CLK 2
402 #define TISCI_DEV_DCC8_DCC_CLKSRC3_CLK 3
403 #define TISCI_DEV_DCC8_DCC_CLKSRC4_CLK 4
404 #define TISCI_DEV_DCC8_DCC_CLKSRC5_CLK 5
405 #define TISCI_DEV_DCC8_DCC_CLKSRC6_CLK 6
406 #define TISCI_DEV_DCC8_DCC_CLKSRC7_CLK 7
407 #define TISCI_DEV_DCC8_DCC_INPUT00_CLK 8
408 #define TISCI_DEV_DCC8_DCC_INPUT01_CLK 9
409 #define TISCI_DEV_DCC8_DCC_INPUT02_CLK 10
410 #define TISCI_DEV_DCC8_DCC_INPUT10_CLK 11
411 #define TISCI_DEV_DCC8_VBUS_CLK 12
413 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC0_CLK 0
414 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC1_CLK 1
415 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC2_CLK 2
416 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC3_CLK 3
417 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC4_CLK 4
418 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC5_CLK 5
419 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC6_CLK 6
420 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC7_CLK 7
421 #define TISCI_DEV_MCU_DCC0_DCC_INPUT00_CLK 8
422 #define TISCI_DEV_MCU_DCC0_DCC_INPUT01_CLK 9
423 #define TISCI_DEV_MCU_DCC0_DCC_INPUT02_CLK 10
424 #define TISCI_DEV_MCU_DCC0_DCC_INPUT10_CLK 11
425 #define TISCI_DEV_MCU_DCC0_VBUS_CLK 12
427 #define TISCI_DEV_MCU_DCC1_DCC_CLKSRC0_CLK 0
428 #define TISCI_DEV_MCU_DCC1_DCC_CLKSRC1_CLK 1
429 #define TISCI_DEV_MCU_DCC1_DCC_CLKSRC5_CLK 5
430 #define TISCI_DEV_MCU_DCC1_DCC_CLKSRC6_CLK 6
431 #define TISCI_DEV_MCU_DCC1_DCC_CLKSRC7_CLK 7
432 #define TISCI_DEV_MCU_DCC1_DCC_INPUT00_CLK 8
433 #define TISCI_DEV_MCU_DCC1_DCC_INPUT01_CLK 9
434 #define TISCI_DEV_MCU_DCC1_DCC_INPUT02_CLK 10
435 #define TISCI_DEV_MCU_DCC1_DCC_INPUT10_CLK 11
436 #define TISCI_DEV_MCU_DCC1_VBUS_CLK 12
438 #define TISCI_DEV_DEBUGSS_WRAP0_ATB_CLK 0
439 #define TISCI_DEV_DEBUGSS_WRAP0_CORE_CLK 1
440 #define TISCI_DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK 2
441 #define TISCI_DEV_DEBUGSS_WRAP0_JTAG_TCK 20
442 #define TISCI_DEV_DEBUGSS_WRAP0_P1500_WRCK 21
443 #define TISCI_DEV_DEBUGSS_WRAP0_TREXPT_CLK 22
445 #define TISCI_DEV_DMASS0_BCDMA_0_CLK 0
447 #define TISCI_DEV_DMASS0_CBASS_0_CLK 0
449 #define TISCI_DEV_DMASS0_INTAGGR_0_CLK 0
451 #define TISCI_DEV_DMASS0_IPCSS_0_CLK 0
453 #define TISCI_DEV_DMASS0_PKTDMA_0_CLK 0
455 #define TISCI_DEV_DMASS0_RINGACC_0_CLK 0
457 #define TISCI_DEV_DMASS1_BCDMA_0_CLK 0
459 #define TISCI_DEV_DMASS1_INTAGGR_0_CLK 0
461 #define TISCI_DEV_TIMER0_TIMER_HCLK_CLK 0
462 #define TISCI_DEV_TIMER0_TIMER_PWM 1
463 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK 2
464 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
465 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
466 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
467 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
468 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
469 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
470 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
471 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
472 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
473 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 13
474 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1 14
476 #define TISCI_DEV_TIMER1_TIMER_HCLK_CLK 0
477 #define TISCI_DEV_TIMER1_TIMER_PWM 1
478 #define TISCI_DEV_TIMER1_TIMER_TCLK_CLK 2
479 #define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT1 3
480 #define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM 4
482 #define TISCI_DEV_TIMER2_TIMER_HCLK_CLK 0
483 #define TISCI_DEV_TIMER2_TIMER_PWM 1
484 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK 2
485 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
486 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
487 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
488 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
489 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
490 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
491 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
492 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
493 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
494 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 13
495 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1 14
497 #define TISCI_DEV_TIMER3_TIMER_HCLK_CLK 0
498 #define TISCI_DEV_TIMER3_TIMER_PWM 1
499 #define TISCI_DEV_TIMER3_TIMER_TCLK_CLK 2
500 #define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT3 3
501 #define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM 4
503 #define TISCI_DEV_TIMER4_TIMER_HCLK_CLK 0
504 #define TISCI_DEV_TIMER4_TIMER_PWM 1
505 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK 2
506 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
507 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
508 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
509 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
510 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
511 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
512 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
513 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
514 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
515 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 13
516 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1 14
518 #define TISCI_DEV_TIMER5_TIMER_HCLK_CLK 0
519 #define TISCI_DEV_TIMER5_TIMER_PWM 1
520 #define TISCI_DEV_TIMER5_TIMER_TCLK_CLK 2
521 #define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT5 3
522 #define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM 4
524 #define TISCI_DEV_TIMER6_TIMER_HCLK_CLK 0
525 #define TISCI_DEV_TIMER6_TIMER_PWM 1
526 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK 2
527 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
528 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
529 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
530 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
531 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
532 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
533 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
534 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
535 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
536 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 13
537 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1 14
539 #define TISCI_DEV_TIMER7_TIMER_HCLK_CLK 0
540 #define TISCI_DEV_TIMER7_TIMER_PWM 1
541 #define TISCI_DEV_TIMER7_TIMER_TCLK_CLK 2
542 #define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT7 3
543 #define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM 4
545 #define TISCI_DEV_MCU_TIMER0_TIMER_HCLK_CLK 0
546 #define TISCI_DEV_MCU_TIMER0_TIMER_PWM 1
547 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK 2
548 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
549 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 4
550 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 5
551 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK 6
552 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
553 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 8
554 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 9
555 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 10
557 #define TISCI_DEV_MCU_TIMER1_TIMER_HCLK_CLK 0
558 #define TISCI_DEV_MCU_TIMER1_TIMER_PWM 1
559 #define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK 2
560 #define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT1 3
561 #define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM 4
563 #define TISCI_DEV_MCU_TIMER2_TIMER_HCLK_CLK 0
564 #define TISCI_DEV_MCU_TIMER2_TIMER_PWM 1
565 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK 2
566 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
567 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 4
568 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 5
569 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK 6
570 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
571 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 8
572 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 9
573 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 10
575 #define TISCI_DEV_MCU_TIMER3_TIMER_HCLK_CLK 0
576 #define TISCI_DEV_MCU_TIMER3_TIMER_PWM 1
577 #define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK 2
578 #define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT3 3
579 #define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM 4
581 #define TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK 0
582 #define TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 1
583 #define TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
584 #define TISCI_DEV_WKUP_TIMER0_TIMER_PWM 3
585 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK 4
586 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 5
587 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT04 6
588 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 7
589 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK 8
590 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 9
591 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 10
592 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 11
593 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 12
595 #define TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK 0
596 #define TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 1
597 #define TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
598 #define TISCI_DEV_WKUP_TIMER1_TIMER_TCLK_CLK 4
599 #define TISCI_DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT1 5
600 #define TISCI_DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_WKUP_0_TIMER_PWM 6
602 #define TISCI_DEV_ECAP0_VBUS_CLK 0
604 #define TISCI_DEV_ECAP1_VBUS_CLK 0
606 #define TISCI_DEV_ECAP2_VBUS_CLK 0
608 #define TISCI_DEV_ELM0_VBUSP_CLK 0
610 #define TISCI_DEV_MMCSD0_EMMCSS_VBUS_CLK 1
611 #define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK 2
612 #define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK 3
613 #define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 4
615 #define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I 0
616 #define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT 1
617 #define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLK_OUT 2
618 #define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_O 3
619 #define TISCI_DEV_MMCSD1_EMMCSDSS_VBUS_CLK 5
620 #define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK 6
621 #define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK 7
622 #define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 8
624 #define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I 0
625 #define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLKLB_OUT 1
626 #define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLK_OUT 2
627 #define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_O 3
628 #define TISCI_DEV_MMCSD2_EMMCSDSS_VBUS_CLK 5
629 #define TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK 6
630 #define TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK 7
631 #define TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 8
633 #define TISCI_DEV_EQEP0_VBUS_CLK 0
635 #define TISCI_DEV_EQEP1_VBUS_CLK 0
637 #define TISCI_DEV_EQEP2_VBUS_CLK 0
639 #define TISCI_DEV_WKUP_ESM0_CLK 0
641 #define TISCI_DEV_ESM0_CLK 0
643 #define TISCI_DEV_FSS0_FSAS_0_GCLK 0
645 #define TISCI_DEV_FSS0_OSPI_0_OSPI_DQS_CLK 0
646 #define TISCI_DEV_FSS0_OSPI_0_OSPI_HCLK_CLK 1
647 #define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK 2
648 #define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT 3
649 #define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT 4
650 #define TISCI_DEV_FSS0_OSPI_0_OSPI_OCLK_CLK 5
651 #define TISCI_DEV_FSS0_OSPI_0_OSPI_PCLK_CLK 6
652 #define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK 7
653 #define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK 8
654 #define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK 9
656 #define TISCI_DEV_GICSS0_VCLK_CLK 0
658 #define TISCI_DEV_GPIO0_MMR_CLK 0
660 #define TISCI_DEV_GPIO1_MMR_CLK 0
662 #define TISCI_DEV_MCU_GPIO0_MMR_CLK 0
663 #define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 1
664 #define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT 2
665 #define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 3
666 #define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 4
668 #define TISCI_DEV_GPMC0_FUNC_CLK 0
669 #define TISCI_DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK 1
670 #define TISCI_DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK 2
671 #define TISCI_DEV_GPMC0_PI_GPMC_RET_CLK 3
672 #define TISCI_DEV_GPMC0_PO_GPMC_DEV_CLK 4
673 #define TISCI_DEV_GPMC0_VBUSM_CLK 5
675 #define TISCI_DEV_WKUP_GTC0_GTC_CLK 0
676 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK 1
677 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 2
678 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 3
679 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
680 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 6
681 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2 7
682 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK 8
683 #define TISCI_DEV_WKUP_GTC0_VBUSP_CLK 9
684 #define TISCI_DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 10
685 #define TISCI_DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 11
687 #define TISCI_DEV_DDPA0_DDPA_CLK 0
689 #define TISCI_DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK 0
690 #define TISCI_DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK 1
691 #define TISCI_DEV_DSS_DSI0_DPI_0_CLK 2
692 #define TISCI_DEV_DSS_DSI0_PLL_CTRL_CLK 3
693 #define TISCI_DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK 4
694 #define TISCI_DEV_DSS_DSI0_SYS_CLK 5
696 #define TISCI_DEV_DSS0_DPI_0_IN_CLK 0
697 #define TISCI_DEV_DSS0_DPI_1_IN_CLK 2
698 #define TISCI_DEV_DSS0_DPI_1_IN_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK 3
699 #define TISCI_DEV_DSS0_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT 4
700 #define TISCI_DEV_DSS0_DPI_1_OUT_CLK 5
701 #define TISCI_DEV_DSS0_DSS_FUNC_CLK 6
703 #define TISCI_DEV_DSS1_DPI_0_IN_CLK 0
704 #define TISCI_DEV_DSS1_DPI_0_IN_CLK_PARENT_MAIN_DSS1_DPI0__PLLSEL_OUT0 1
705 #define TISCI_DEV_DSS1_DPI_0_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT 2
706 #define TISCI_DEV_DSS1_DPI_0_OUT_CLK 3
707 #define TISCI_DEV_DSS1_DPI_1_IN_CLK 4
708 #define TISCI_DEV_DSS1_DPI_1_IN_CLK_PARENT_MAIN_DSS1_DPI1__PLLSEL_OUT0 5
709 #define TISCI_DEV_DSS1_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT 6
710 #define TISCI_DEV_DSS1_DPI_1_OUT_CLK 7
711 #define TISCI_DEV_DSS1_DSS_FUNC_CLK 8
713 #define TISCI_DEV_EPWM0_VBUSP_CLK 0
715 #define TISCI_DEV_EPWM1_VBUSP_CLK 0
717 #define TISCI_DEV_EPWM2_VBUSP_CLK 0
719 #define TISCI_DEV_JPGENC0_CORE_CLK 0
721 #define TISCI_DEV_LED0_VBUS_CLK 1
723 #define TISCI_DEV_PBIST0_CLK8_CLK 7
724 #define TISCI_DEV_PBIST0_TCLK_CLK 9
726 #define TISCI_DEV_PBIST1_CLK8_CLK 7
727 #define TISCI_DEV_PBIST1_TCLK_CLK 9
729 #define TISCI_DEV_WKUP_PBIST0_CLK8_CLK 7
731 #define TISCI_DEV_PBIST2_CLK8_CLK 7
732 #define TISCI_DEV_PBIST2_TCLK_CLK 9
734 #define TISCI_DEV_MCU_PBIST0_CLK8_CLK 7
736 #define TISCI_DEV_CODEC0_VPU_ACLK_CLK 0
737 #define TISCI_DEV_CODEC0_VPU_BCLK_CLK 1
738 #define TISCI_DEV_CODEC0_VPU_CCLK_CLK 2
739 #define TISCI_DEV_CODEC0_VPU_PCLK_CLK 3
741 #define TISCI_DEV_WKUP_VTM0_FIX_REF2_CLK 0
742 #define TISCI_DEV_WKUP_VTM0_FIX_REF_CLK 1
743 #define TISCI_DEV_WKUP_VTM0_VBUSP_CLK 2
744 #define TISCI_DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 3
745 #define TISCI_DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 4
747 #define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK 1
748 #define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 2
749 #define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
750 #define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 4
751 #define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 5
752 #define TISCI_DEV_MCAN0_MCANSS_HCLK_CLK 6
754 #define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK 1
755 #define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 2
756 #define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
757 #define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 4
758 #define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 5
759 #define TISCI_DEV_MCAN1_MCANSS_HCLK_CLK 6
761 #define TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK 1
762 #define TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK 2
763 #define TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
764 #define TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 4
765 #define TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0 5
766 #define TISCI_DEV_MCU_MCAN0_MCANSS_HCLK_CLK 6
768 #define TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK 1
769 #define TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK 2
770 #define TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
771 #define TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 4
772 #define TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0 5
773 #define TISCI_DEV_MCU_MCAN1_MCANSS_HCLK_CLK 6
775 #define TISCI_DEV_MCASP0_AUX_CLK 0
776 #define TISCI_DEV_MCASP0_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
777 #define TISCI_DEV_MCASP0_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
778 #define TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 5
779 #define TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 6
780 #define TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 7
781 #define TISCI_DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 8
782 #define TISCI_DEV_MCASP0_MCASP_ACLKR_PIN 9
783 #define TISCI_DEV_MCASP0_MCASP_ACLKR_POUT 10
784 #define TISCI_DEV_MCASP0_MCASP_ACLKX_PIN 11
785 #define TISCI_DEV_MCASP0_MCASP_ACLKX_POUT 12
786 #define TISCI_DEV_MCASP0_MCASP_AFSR_PIN 13
787 #define TISCI_DEV_MCASP0_MCASP_AFSR_POUT 14
788 #define TISCI_DEV_MCASP0_MCASP_AFSX_PIN 15
789 #define TISCI_DEV_MCASP0_MCASP_AFSX_POUT 16
790 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN 17
791 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 18
792 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 19
793 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 20
794 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 21
795 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 22
796 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 23
797 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 24
798 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 25
799 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 26
800 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_POUT 34
801 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN 35
802 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 36
803 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 37
804 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 38
805 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 39
806 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 40
807 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 41
808 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 42
809 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 43
810 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 44
811 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_POUT 52
812 #define TISCI_DEV_MCASP0_VBUSP_CLK 53
814 #define TISCI_DEV_MCASP1_AUX_CLK 0
815 #define TISCI_DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
816 #define TISCI_DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
817 #define TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 5
818 #define TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 6
819 #define TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 7
820 #define TISCI_DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 8
821 #define TISCI_DEV_MCASP1_MCASP_ACLKR_PIN 9
822 #define TISCI_DEV_MCASP1_MCASP_ACLKR_POUT 10
823 #define TISCI_DEV_MCASP1_MCASP_ACLKX_PIN 11
824 #define TISCI_DEV_MCASP1_MCASP_ACLKX_POUT 12
825 #define TISCI_DEV_MCASP1_MCASP_AFSR_PIN 13
826 #define TISCI_DEV_MCASP1_MCASP_AFSR_POUT 14
827 #define TISCI_DEV_MCASP1_MCASP_AFSX_PIN 15
828 #define TISCI_DEV_MCASP1_MCASP_AFSX_POUT 16
829 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN 17
830 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 18
831 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 19
832 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 20
833 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 21
834 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 22
835 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 23
836 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 24
837 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 25
838 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 26
839 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_POUT 34
840 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN 35
841 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 36
842 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 37
843 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 38
844 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 39
845 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 40
846 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 41
847 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 42
848 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 43
849 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 44
850 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_POUT 52
851 #define TISCI_DEV_MCASP1_VBUSP_CLK 53
853 #define TISCI_DEV_MCASP2_AUX_CLK 0
854 #define TISCI_DEV_MCASP2_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
855 #define TISCI_DEV_MCASP2_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
856 #define TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 5
857 #define TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 6
858 #define TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 7
859 #define TISCI_DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 8
860 #define TISCI_DEV_MCASP2_MCASP_ACLKR_PIN 9
861 #define TISCI_DEV_MCASP2_MCASP_ACLKR_POUT 10
862 #define TISCI_DEV_MCASP2_MCASP_ACLKX_PIN 11
863 #define TISCI_DEV_MCASP2_MCASP_ACLKX_POUT 12
864 #define TISCI_DEV_MCASP2_MCASP_AFSR_PIN 13
865 #define TISCI_DEV_MCASP2_MCASP_AFSR_POUT 14
866 #define TISCI_DEV_MCASP2_MCASP_AFSX_PIN 15
867 #define TISCI_DEV_MCASP2_MCASP_AFSX_POUT 16
868 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN 17
869 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 18
870 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 19
871 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 20
872 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 21
873 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 22
874 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 23
875 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 24
876 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 25
877 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 26
878 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_POUT 34
879 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN 35
880 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 36
881 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 37
882 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 38
883 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 39
884 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 40
885 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 41
886 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 42
887 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 43
888 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 44
889 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_POUT 52
890 #define TISCI_DEV_MCASP2_VBUSP_CLK 53
892 #define TISCI_DEV_MCASP3_AUX_CLK 0
893 #define TISCI_DEV_MCASP3_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
894 #define TISCI_DEV_MCASP3_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
895 #define TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 5
896 #define TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 6
897 #define TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 7
898 #define TISCI_DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 8
899 #define TISCI_DEV_MCASP3_MCASP_ACLKR_PIN 9
900 #define TISCI_DEV_MCASP3_MCASP_ACLKR_POUT 10
901 #define TISCI_DEV_MCASP3_MCASP_ACLKX_PIN 11
902 #define TISCI_DEV_MCASP3_MCASP_ACLKX_POUT 12
903 #define TISCI_DEV_MCASP3_MCASP_AFSR_PIN 13
904 #define TISCI_DEV_MCASP3_MCASP_AFSR_POUT 14
905 #define TISCI_DEV_MCASP3_MCASP_AFSX_PIN 15
906 #define TISCI_DEV_MCASP3_MCASP_AFSX_POUT 16
907 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN 17
908 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 18
909 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 19
910 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 20
911 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 21
912 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 22
913 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 23
914 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 24
915 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 25
916 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 26
917 #define TISCI_DEV_MCASP3_MCASP_AHCLKR_POUT 34
918 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN 35
919 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 36
920 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 37
921 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 38
922 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 39
923 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 40
924 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 41
925 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 42
926 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 43
927 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 44
928 #define TISCI_DEV_MCASP3_MCASP_AHCLKX_POUT 52
929 #define TISCI_DEV_MCASP3_VBUSP_CLK 53
931 #define TISCI_DEV_MCASP4_AUX_CLK 0
932 #define TISCI_DEV_MCASP4_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
933 #define TISCI_DEV_MCASP4_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
934 #define TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 5
935 #define TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 6
936 #define TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 7
937 #define TISCI_DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 8
938 #define TISCI_DEV_MCASP4_MCASP_ACLKR_PIN 9
939 #define TISCI_DEV_MCASP4_MCASP_ACLKR_POUT 10
940 #define TISCI_DEV_MCASP4_MCASP_ACLKX_PIN 11
941 #define TISCI_DEV_MCASP4_MCASP_ACLKX_POUT 12
942 #define TISCI_DEV_MCASP4_MCASP_AFSR_PIN 13
943 #define TISCI_DEV_MCASP4_MCASP_AFSR_POUT 14
944 #define TISCI_DEV_MCASP4_MCASP_AFSX_PIN 15
945 #define TISCI_DEV_MCASP4_MCASP_AFSX_POUT 16
946 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN 17
947 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 18
948 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 19
949 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 20
950 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 21
951 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 22
952 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 23
953 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 24
954 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 25
955 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 26
956 #define TISCI_DEV_MCASP4_MCASP_AHCLKR_POUT 34
957 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN 35
958 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 36
959 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 37
960 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 38
961 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 39
962 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 40
963 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 41
964 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 42
965 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 43
966 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 44
967 #define TISCI_DEV_MCASP4_MCASP_AHCLKX_POUT 52
968 #define TISCI_DEV_MCASP4_VBUSP_CLK 53
970 #define TISCI_DEV_MCRC64_0_CLK 0
972 #define TISCI_DEV_MCU_MCRC64_0_CLK 0
974 #define TISCI_DEV_I2C0_CLK 0
975 #define TISCI_DEV_I2C0_PISCL 1
976 #define TISCI_DEV_I2C0_PISYS_CLK 2
977 #define TISCI_DEV_I2C0_PORSCL 3
979 #define TISCI_DEV_I2C1_CLK 0
980 #define TISCI_DEV_I2C1_PISCL 1
981 #define TISCI_DEV_I2C1_PISYS_CLK 2
982 #define TISCI_DEV_I2C1_PORSCL 3
984 #define TISCI_DEV_I2C2_CLK 0
985 #define TISCI_DEV_I2C2_PISCL 1
986 #define TISCI_DEV_I2C2_PISYS_CLK 2
987 #define TISCI_DEV_I2C2_PORSCL 3
989 #define TISCI_DEV_I2C3_CLK 0
990 #define TISCI_DEV_I2C3_PISCL 1
991 #define TISCI_DEV_I2C3_PISYS_CLK 2
992 #define TISCI_DEV_I2C3_PORSCL 3
994 #define TISCI_DEV_I2C4_CLK 0
995 #define TISCI_DEV_I2C4_PISCL 1
996 #define TISCI_DEV_I2C4_PISYS_CLK 2
997 #define TISCI_DEV_I2C4_PORSCL 3
999 #define TISCI_DEV_MCU_I2C0_CLK 0
1000 #define TISCI_DEV_MCU_I2C0_PISCL 1
1001 #define TISCI_DEV_MCU_I2C0_PISYS_CLK 2
1002 #define TISCI_DEV_MCU_I2C0_PORSCL 3
1004 #define TISCI_DEV_WKUP_I2C0_CLK 0
1005 #define TISCI_DEV_WKUP_I2C0_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 1
1006 #define TISCI_DEV_WKUP_I2C0_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
1007 #define TISCI_DEV_WKUP_I2C0_PISCL 3
1008 #define TISCI_DEV_WKUP_I2C0_PISYS_CLK 4
1009 #define TISCI_DEV_WKUP_I2C0_PORSCL 5
1011 #define TISCI_DEV_MSRAM8KX256E0_CCLK_CLK 0
1012 #define TISCI_DEV_MSRAM8KX256E0_VCLK_CLK 1
1014 #define TISCI_DEV_OLDI_TX_CORE0_OLDI_0_FWD_P_CLK 0
1015 #define TISCI_DEV_OLDI_TX_CORE0_OLDI_PLL_CLK 5
1017 #define TISCI_DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK 0
1018 #define TISCI_DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK 1
1019 #define TISCI_DEV_OLDI_TX_CORE1_OLDI_0_FWD_P_CLK_PARENT_MAIN_DSS1_DPI0_PCLK_OUT0 2
1020 #define TISCI_DEV_OLDI_TX_CORE1_OLDI_PLL_CLK 7
1021 #define TISCI_DEV_OLDI_TX_CORE1_OLDI_PLL_CLK_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK 8
1022 #define TISCI_DEV_OLDI_TX_CORE1_OLDI_PLL_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK 9
1024 #define TISCI_DEV_PCIE0_PCIE_CBA_CLK 0
1025 #define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK 1
1026 #define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 2
1027 #define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 3
1028 #define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 4
1029 #define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 6
1030 #define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 7
1031 #define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B2M4CT_MAIN_1_IP1_LN0_TXMCLK 8
1032 #define TISCI_DEV_PCIE0_PCIE_LANE0_REFCLK 10
1033 #define TISCI_DEV_PCIE0_PCIE_LANE0_RXCLK 11
1034 #define TISCI_DEV_PCIE0_PCIE_LANE0_RXFCLK 12
1035 #define TISCI_DEV_PCIE0_PCIE_LANE0_TXCLK 13
1036 #define TISCI_DEV_PCIE0_PCIE_LANE0_TXFCLK 14
1037 #define TISCI_DEV_PCIE0_PCIE_LANE0_TXMCLK 15
1038 #define TISCI_DEV_PCIE0_PCIE_PM_CLK 16
1040 #define TISCI_DEV_R5FSS0_CORE0_CPU_CLK 0
1041 #define TISCI_DEV_R5FSS0_CORE0_INTERFACE_CLK 1
1043 #define TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK 0
1044 #define TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 1
1045 #define TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
1046 #define TISCI_DEV_WKUP_R5FSS0_CORE0_INTERFACE_CLK 3
1048 #define TISCI_DEV_MCU_R5FSS0_CORE0_CPU0_CLK 0
1049 #define TISCI_DEV_MCU_R5FSS0_CORE0_INTERFACE0_CLK 1
1051 #define TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK 0
1052 #define TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_CLK_32K_RC_SEL_OUT0 1
1053 #define TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 2
1054 #define TISCI_DEV_WKUP_RTCSS0_JTAG_WRCK 4
1055 #define TISCI_DEV_WKUP_RTCSS0_VCLK_CLK 6
1056 #define TISCI_DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 7
1057 #define TISCI_DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 8
1059 #define TISCI_DEV_RTI4_RTI_CLK 0
1060 #define TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1061 #define TISCI_DEV_RTI4_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1062 #define TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1063 #define TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
1064 #define TISCI_DEV_RTI4_VBUSP_CLK 5
1066 #define TISCI_DEV_RTI5_RTI_CLK 0
1067 #define TISCI_DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1068 #define TISCI_DEV_RTI5_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1069 #define TISCI_DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1070 #define TISCI_DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
1071 #define TISCI_DEV_RTI5_VBUSP_CLK 5
1073 #define TISCI_DEV_RTI15_RTI_CLK 0
1074 #define TISCI_DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1075 #define TISCI_DEV_RTI15_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1076 #define TISCI_DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1077 #define TISCI_DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
1078 #define TISCI_DEV_RTI15_VBUSP_CLK 5
1080 #define TISCI_DEV_RTI0_RTI_CLK 0
1081 #define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1082 #define TISCI_DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1083 #define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1084 #define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
1085 #define TISCI_DEV_RTI0_VBUSP_CLK 5
1087 #define TISCI_DEV_RTI1_RTI_CLK 0
1088 #define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1089 #define TISCI_DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1090 #define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1091 #define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
1092 #define TISCI_DEV_RTI1_VBUSP_CLK 5
1094 #define TISCI_DEV_RTI2_RTI_CLK 0
1095 #define TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1096 #define TISCI_DEV_RTI2_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1097 #define TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1098 #define TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
1099 #define TISCI_DEV_RTI2_VBUSP_CLK 5
1101 #define TISCI_DEV_RTI3_RTI_CLK 0
1102 #define TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1103 #define TISCI_DEV_RTI3_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1104 #define TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1105 #define TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
1106 #define TISCI_DEV_RTI3_VBUSP_CLK 5
1108 #define TISCI_DEV_RTI8_RTI_CLK 0
1109 #define TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1110 #define TISCI_DEV_RTI8_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1111 #define TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1112 #define TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
1113 #define TISCI_DEV_RTI8_VBUSP_CLK 5
1115 #define TISCI_DEV_MCU_RTI0_RTI_CLK 0
1116 #define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1117 #define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1118 #define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1119 #define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
1120 #define TISCI_DEV_MCU_RTI0_VBUSP_CLK 5
1122 #define TISCI_DEV_WKUP_RTI0_RTI_CLK 0
1123 #define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1124 #define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1125 #define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1126 #define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
1127 #define TISCI_DEV_WKUP_RTI0_VBUSP_CLK 5
1128 #define TISCI_DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 6
1129 #define TISCI_DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 7
1131 #define TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK 0
1133 #define TISCI_DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK 0
1135 #define TISCI_DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK 0
1137 #define TISCI_DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK 0
1139 #define TISCI_DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK 0
1141 #define TISCI_DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK 2
1142 #define TISCI_DEV_A53SS0_COREPAC_ARM_CLK_CLK 3
1143 #define TISCI_DEV_A53SS0_PLL_CTRL_CLK 5
1145 #define TISCI_DEV_COMPUTE_CLUSTER0_CLKDIV_0_DIVH_CLK4_CLK_CLK 0
1146 #define TISCI_DEV_COMPUTE_CLUSTER0_CLKDIV_0_DIVP_CLK1_CLK_CLK 1
1147 #define TISCI_DEV_COMPUTE_CLUSTER0_CLKDIV_0_FUNC_CLKIN_CLK 2
1149 #define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0_DIVH_CLK4_CLK_CLK 2
1150 #define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0_DIVP_CLK1_CLK_CLK 3
1152 #define TISCI_DEV_DEBUGSS0_CFG_CLK 0
1153 #define TISCI_DEV_DEBUGSS0_DBG_CLK 1
1154 #define TISCI_DEV_DEBUGSS0_SYS_CLK 2
1156 #define TISCI_DEV_MCU_MCU_16FF0_PLL_CTRL_MCU_CLK24_CLK 3
1158 #define TISCI_DEV_WKUP_PSC0_CLK 0
1159 #define TISCI_DEV_WKUP_PSC0_SLOW_CLK 1
1161 #define TISCI_DEV_A53_RS_BW_LIMITER0_CLK_CLK 0
1163 #define TISCI_DEV_A53_WS_BW_LIMITER1_CLK_CLK 0
1165 #define TISCI_DEV_C7XV_RSWS_BS_LIMITER6_CLK_CLK 0
1167 #define TISCI_DEV_C7XV_RSWS_BS_LIMITER11_CLK_CLK 0
1169 #define TISCI_DEV_C7X256V0_C7XV_CORE_0_C7XV_CLK 0
1171 #define TISCI_DEV_C7X256V0_CORE0_DIVH_CLK2_SOC_GCLK 0
1172 #define TISCI_DEV_C7X256V0_CORE0_DIVH_CLK4_GCLK 1
1173 #define TISCI_DEV_C7X256V0_CORE0_DIVH_CLK4_SOC_GCLK 2
1174 #define TISCI_DEV_C7X256V0_CORE0_DIVP_CLK1_GCLK 3
1175 #define TISCI_DEV_C7X256V0_CORE0_DIVP_CLK1_SOC_GCLK 4
1177 #define TISCI_DEV_C7X256V0_CLK_C7XV_CLK 0
1178 #define TISCI_DEV_C7X256V0_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK 1
1179 #define TISCI_DEV_C7X256V0_CLK_DIVH_CLK2_SOC_GCLK 2
1180 #define TISCI_DEV_C7X256V0_CLK_DIVH_CLK4_GCLK 3
1181 #define TISCI_DEV_C7X256V0_CLK_DIVH_CLK4_SOC_GCLK 4
1182 #define TISCI_DEV_C7X256V0_CLK_DIVP_CLK1_GCLK 5
1183 #define TISCI_DEV_C7X256V0_CLK_DIVP_CLK1_SOC_GCLK 6
1184 #define TISCI_DEV_C7X256V0_CLK_PLL_CTRL_CLK 7
1186 #define TISCI_DEV_C7X256V1_C7XV_CORE_0_C7XV_CLK 0
1188 #define TISCI_DEV_C7X256V1_CORE0_DIVH_CLK2_SOC_GCLK 0
1189 #define TISCI_DEV_C7X256V1_CORE0_DIVH_CLK4_GCLK 1
1190 #define TISCI_DEV_C7X256V1_CORE0_DIVH_CLK4_SOC_GCLK 2
1191 #define TISCI_DEV_C7X256V1_CORE0_DIVP_CLK1_GCLK 3
1192 #define TISCI_DEV_C7X256V1_CORE0_DIVP_CLK1_SOC_GCLK 4
1194 #define TISCI_DEV_C7X256V1_CLK_C7XV_CLK 0
1195 #define TISCI_DEV_C7X256V1_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK 1
1196 #define TISCI_DEV_C7X256V1_CLK_DIVH_CLK2_SOC_GCLK 2
1197 #define TISCI_DEV_C7X256V1_CLK_DIVH_CLK4_GCLK 3
1198 #define TISCI_DEV_C7X256V1_CLK_DIVH_CLK4_SOC_GCLK 4
1199 #define TISCI_DEV_C7X256V1_CLK_DIVP_CLK1_GCLK 5
1200 #define TISCI_DEV_C7X256V1_CLK_DIVP_CLK1_SOC_GCLK 6
1201 #define TISCI_DEV_C7X256V1_CLK_PLL_CTRL_CLK 7
1203 #define TISCI_DEV_CTI0_DBG_CLK 0
1205 #define TISCI_DEV_CTI1_DBG_CLK 0
1207 #define TISCI_DEV_DDR32SS0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK 0
1208 #define TISCI_DEV_DDR32SS0_DDRSS_DDR_PLL_CLK 1
1209 #define TISCI_DEV_DDR32SS0_DDRSS_TCK 2
1210 #define TISCI_DEV_DDR32SS0_PLL_CTRL_CLK 3
1212 #define TISCI_DEV_DMPAC0_DMPAC_PLL_CLK 2
1213 #define TISCI_DEV_DMPAC0_PLL_CTRL_CLK 4
1215 #define TISCI_DEV_JPGENC_RS_BW_LIMITER4_CLK_CLK 0
1217 #define TISCI_DEV_JPGENC_WS_BW_LIMITER5_CLK_CLK 0
1219 #define TISCI_DEV_GPU0_GPU_DCC_CLK 2
1220 #define TISCI_DEV_GPU0_GPU_PLL_CLK 3
1221 #define TISCI_DEV_GPU0_PLL_CTRL_CLK 4
1223 #define TISCI_DEV_GPU_RS_BW_LIMITER9_CLK_CLK 0
1225 #define TISCI_DEV_GPU_WS_BW_LIMITER10_CLK_CLK 0
1227 #define TISCI_DEV_PSC0_FW_0_CLK 0
1229 #define TISCI_DEV_PSC0_CLK 0
1230 #define TISCI_DEV_PSC0_SLOW_CLK 1
1232 #define TISCI_DEV_VPAC_RSWS_BW_LIMITER8_CLK_CLK 0
1234 #define TISCI_DEV_VPAC_RSWS_BW_LIMITER7_CLK_CLK 0
1236 #define TISCI_DEV_VPAC0_PLL_CTRL_CLK 2
1237 #define TISCI_DEV_VPAC0_VPAC_PLL_CFG_CLK 4
1238 #define TISCI_DEV_VPAC0_VPAC_PLL_CLK 5
1240 #define TISCI_DEV_PBIST3_CLK8_CLK 2
1241 #define TISCI_DEV_PBIST3_TCLK_CLK 4
1243 #define TISCI_DEV_CODEC_RS_BW_LIMITER2_CLK_CLK 0
1245 #define TISCI_DEV_CODEC_WS_BW_LIMITER3_CLK_CLK 0
1247 #define TISCI_DEV_HSM0_DAP_CLK 0
1249 #define TISCI_DEV_MCSPI0_CLKSPIREF_CLK 0
1250 #define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK 1
1251 #define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT 2
1252 #define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK 3
1253 #define TISCI_DEV_MCSPI0_IO_CLKSPIO_CLK 4
1254 #define TISCI_DEV_MCSPI0_VBUSP_CLK 5
1256 #define TISCI_DEV_MCSPI1_CLKSPIREF_CLK 0
1257 #define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK 1
1258 #define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT 2
1259 #define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK 3
1260 #define TISCI_DEV_MCSPI1_IO_CLKSPIO_CLK 4
1261 #define TISCI_DEV_MCSPI1_VBUSP_CLK 5
1263 #define TISCI_DEV_MCSPI2_CLKSPIREF_CLK 0
1264 #define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK 1
1265 #define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT 2
1266 #define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK 3
1267 #define TISCI_DEV_MCSPI2_IO_CLKSPIO_CLK 4
1268 #define TISCI_DEV_MCSPI2_VBUSP_CLK 5
1270 #define TISCI_DEV_MCU_MCSPI0_CLKSPIREF_CLK 0
1271 #define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK 1
1272 #define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT 2
1273 #define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK 3
1274 #define TISCI_DEV_MCU_MCSPI0_IO_CLKSPIO_CLK 4
1275 #define TISCI_DEV_MCU_MCSPI0_VBUSP_CLK 5
1277 #define TISCI_DEV_MCU_MCSPI1_CLKSPIREF_CLK 0
1278 #define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK 1
1279 #define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT 2
1280 #define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK 3
1281 #define TISCI_DEV_MCU_MCSPI1_IO_CLKSPIO_CLK 4
1282 #define TISCI_DEV_MCU_MCSPI1_VBUSP_CLK 5
1284 #define TISCI_DEV_SPINLOCK0_VCLK_CLK 0
1286 #define TISCI_DEV_UART0_FCLK_CLK 0
1287 #define TISCI_DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0 1
1288 #define TISCI_DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
1289 #define TISCI_DEV_UART0_VBUSP_CLK 5
1291 #define TISCI_DEV_UART1_FCLK_CLK 0
1292 #define TISCI_DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1 1
1293 #define TISCI_DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
1294 #define TISCI_DEV_UART1_VBUSP_CLK 5
1296 #define TISCI_DEV_UART2_FCLK_CLK 0
1297 #define TISCI_DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2 1
1298 #define TISCI_DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
1299 #define TISCI_DEV_UART2_VBUSP_CLK 5
1301 #define TISCI_DEV_UART3_FCLK_CLK 0
1302 #define TISCI_DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3 1
1303 #define TISCI_DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
1304 #define TISCI_DEV_UART3_VBUSP_CLK 5
1306 #define TISCI_DEV_UART4_FCLK_CLK 0
1307 #define TISCI_DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4 1
1308 #define TISCI_DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
1309 #define TISCI_DEV_UART4_VBUSP_CLK 5
1311 #define TISCI_DEV_UART5_FCLK_CLK 0
1312 #define TISCI_DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5 1
1313 #define TISCI_DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
1314 #define TISCI_DEV_UART5_VBUSP_CLK 5
1316 #define TISCI_DEV_UART6_FCLK_CLK 0
1317 #define TISCI_DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6 1
1318 #define TISCI_DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
1319 #define TISCI_DEV_UART6_VBUSP_CLK 5
1321 #define TISCI_DEV_MCU_UART0_FCLK_CLK 0
1322 #define TISCI_DEV_MCU_UART0_VBUSP_CLK 3
1324 #define TISCI_DEV_WKUP_UART0_FCLK_CLK 0
1325 #define TISCI_DEV_WKUP_UART0_VBUSP_CLK 3
1326 #define TISCI_DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
1327 #define TISCI_DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 5
1329 #define TISCI_DEV_USB0_BUS_CLK 0
1330 #define TISCI_DEV_USB0_CFG_CLK 1
1331 #define TISCI_DEV_USB0_USB2_APB_PCLK_CLK 2
1332 #define TISCI_DEV_USB0_USB2_REFCLOCK_CLK 3
1333 #define TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 4
1334 #define TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK 5
1335 #define TISCI_DEV_USB0_USB2_TAP_TCK 10
1337 #define TISCI_DEV_USB1_ACLK_CLK 0
1338 #define TISCI_DEV_USB1_CLK_LPM_CLK 1
1339 #define TISCI_DEV_USB1_PCLK_CLK 2
1340 #define TISCI_DEV_USB1_USB2_REFCLOCK_CLK 3
1341 #define TISCI_DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 4
1342 #define TISCI_DEV_USB1_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK 5
1343 #define TISCI_DEV_USB1_PIPE_REFCLK 6
1344 #define TISCI_DEV_USB1_PIPE_RXCLK 7
1345 #define TISCI_DEV_USB1_PIPE_RXFCLK 8
1346 #define TISCI_DEV_USB1_PIPE_TXCLK 9
1347 #define TISCI_DEV_USB1_PIPE_TXFCLK 10
1348 #define TISCI_DEV_USB1_PIPE_TXMCLK 11
1349 #define TISCI_DEV_USB1_USB2_APB_PCLK_CLK 12
1350 #define TISCI_DEV_USB1_USB2_TAP_TCK 17
1352 #define TISCI_DEV_SERDES_10G0_CLK 0
1353 #define TISCI_DEV_SERDES_10G0_CORE_REF_CLK 1
1354 #define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
1355 #define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 3
1356 #define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK 4
1357 #define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK 5
1358 #define TISCI_DEV_SERDES_10G0_IP1_LN0_REFCLK 7
1359 #define TISCI_DEV_SERDES_10G0_IP1_LN0_RXCLK 8
1360 #define TISCI_DEV_SERDES_10G0_IP1_LN0_RXFCLK 9
1361 #define TISCI_DEV_SERDES_10G0_IP1_LN0_TXCLK 10
1362 #define TISCI_DEV_SERDES_10G0_IP1_LN0_TXFCLK 11
1363 #define TISCI_DEV_SERDES_10G0_IP1_LN0_TXMCLK 12
1364 #define TISCI_DEV_SERDES_10G0_IP2_LN0_REFCLK 13
1365 #define TISCI_DEV_SERDES_10G0_IP2_LN0_RXCLK 14
1366 #define TISCI_DEV_SERDES_10G0_IP2_LN0_RXFCLK 15
1367 #define TISCI_DEV_SERDES_10G0_IP2_LN0_TXCLK 16
1368 #define TISCI_DEV_SERDES_10G0_IP2_LN0_TXFCLK 17
1369 #define TISCI_DEV_SERDES_10G0_IP2_LN0_TXMCLK 18
1370 #define TISCI_DEV_SERDES_10G0_TAP_TCK 40
1372 #define TISCI_DEV_SERDES_10G1_CLK 0
1373 #define TISCI_DEV_SERDES_10G1_CORE_REF_CLK 1
1374 #define TISCI_DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
1375 #define TISCI_DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 3
1376 #define TISCI_DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK 4
1377 #define TISCI_DEV_SERDES_10G1_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK 5
1378 #define TISCI_DEV_SERDES_10G1_IP1_LN0_REFCLK 7
1379 #define TISCI_DEV_SERDES_10G1_IP1_LN0_RXCLK 8
1380 #define TISCI_DEV_SERDES_10G1_IP1_LN0_RXFCLK 9
1381 #define TISCI_DEV_SERDES_10G1_IP1_LN0_TXCLK 10
1382 #define TISCI_DEV_SERDES_10G1_IP1_LN0_TXFCLK 11
1383 #define TISCI_DEV_SERDES_10G1_IP1_LN0_TXMCLK 12
1384 #define TISCI_DEV_SERDES_10G1_IP2_LN0_REFCLK 13
1385 #define TISCI_DEV_SERDES_10G1_IP2_LN0_RXCLK 14
1386 #define TISCI_DEV_SERDES_10G1_IP2_LN0_RXFCLK 15
1387 #define TISCI_DEV_SERDES_10G1_IP2_LN0_TXCLK 16
1388 #define TISCI_DEV_SERDES_10G1_IP2_LN0_TXFCLK 17
1389 #define TISCI_DEV_SERDES_10G1_IP2_LN0_TXMCLK 18
1390 #define TISCI_DEV_SERDES_10G1_TAP_TCK 40
1392 #define TISCI_DEV_DPHY_TX0_CLK 0
1393 #define TISCI_DEV_DPHY_TX0_DPHY_REF_CLK 1
1394 #define TISCI_DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 2
1395 #define TISCI_DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK 3
1396 #define TISCI_DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK 4
1397 #define TISCI_DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK 5
1398 #define TISCI_DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK 6
1399 #define TISCI_DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK 8
1400 #define TISCI_DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK 9
1401 #define TISCI_DEV_DPHY_TX0_IP3_PPI_M_TXCLKESC_CLK 11
1402 #define TISCI_DEV_DPHY_TX0_IP4_PPI_M_TXCLKESC_CLK 14
1403 #define TISCI_DEV_DPHY_TX0_PSM_CLK 16
1404 #define TISCI_DEV_DPHY_TX0_TAP_TCK 20
1406 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN 0
1407 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 1
1408 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 2
1409 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 3
1410 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT 4
1411 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT 5
1412 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 6
1413 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 7
1414 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 8
1415 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT 9
1416 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT 10
1417 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 11
1418 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 12
1419 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 13
1420 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 14
1421 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 15
1422 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 16
1423 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT 17
1424 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN 18
1425 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 19
1426 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 20
1427 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 21
1428 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT 22
1429 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT 23
1430 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 24
1431 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 25
1432 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 26
1433 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT 27
1434 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT 28
1435 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 29
1436 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 30
1437 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 31
1438 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 32
1439 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 33
1440 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 34
1441 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT 35
1442 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN 36
1443 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 37
1444 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 38
1445 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 39
1446 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT 40
1447 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT 41
1448 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 42
1449 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 43
1450 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 44
1451 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT 45
1452 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT 46
1453 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 47
1454 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 48
1455 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 49
1456 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 50
1457 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 51
1458 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 52
1459 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT 53
1460 #define TISCI_DEV_BOARD0_CLKOUT0_IN 54
1461 #define TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5 55
1462 #define TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10 56
1463 #define TISCI_DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT 61
1464 #define TISCI_DEV_BOARD0_DDR0_CK0_IN 62
1465 #define TISCI_DEV_BOARD0_EXT_REFCLK1_OUT 69
1466 #define TISCI_DEV_BOARD0_GPMC0_CLKLB_IN 70
1467 #define TISCI_DEV_BOARD0_GPMC0_CLKLB_OUT 71
1468 #define TISCI_DEV_BOARD0_GPMC0_CLK_IN 72
1469 #define TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN 73
1470 #define TISCI_DEV_BOARD0_I2C0_SCL_IN 74
1471 #define TISCI_DEV_BOARD0_I2C0_SCL_OUT 75
1472 #define TISCI_DEV_BOARD0_I2C1_SCL_IN 76
1473 #define TISCI_DEV_BOARD0_I2C1_SCL_OUT 77
1474 #define TISCI_DEV_BOARD0_I2C2_SCL_IN 78
1475 #define TISCI_DEV_BOARD0_I2C2_SCL_OUT 79
1476 #define TISCI_DEV_BOARD0_I2C3_SCL_IN 80
1477 #define TISCI_DEV_BOARD0_I2C3_SCL_OUT 81
1478 #define TISCI_DEV_BOARD0_I2C4_SCL_IN 82
1479 #define TISCI_DEV_BOARD0_I2C4_SCL_OUT 83
1480 #define TISCI_DEV_BOARD0_MCASP0_ACLKR_IN 85
1481 #define TISCI_DEV_BOARD0_MCASP0_ACLKR_OUT 86
1482 #define TISCI_DEV_BOARD0_MCASP0_ACLKX_IN 87
1483 #define TISCI_DEV_BOARD0_MCASP0_ACLKX_OUT 88
1484 #define TISCI_DEV_BOARD0_MCASP0_AFSR_IN 89
1485 #define TISCI_DEV_BOARD0_MCASP0_AFSR_OUT 90
1486 #define TISCI_DEV_BOARD0_MCASP0_AFSX_IN 91
1487 #define TISCI_DEV_BOARD0_MCASP0_AFSX_OUT 92
1488 #define TISCI_DEV_BOARD0_MCASP1_ACLKR_IN 93
1489 #define TISCI_DEV_BOARD0_MCASP1_ACLKR_OUT 94
1490 #define TISCI_DEV_BOARD0_MCASP1_ACLKX_IN 95
1491 #define TISCI_DEV_BOARD0_MCASP1_ACLKX_OUT 96
1492 #define TISCI_DEV_BOARD0_MCASP1_AFSR_IN 97
1493 #define TISCI_DEV_BOARD0_MCASP1_AFSR_OUT 98
1494 #define TISCI_DEV_BOARD0_MCASP1_AFSX_IN 99
1495 #define TISCI_DEV_BOARD0_MCASP1_AFSX_OUT 100
1496 #define TISCI_DEV_BOARD0_MCASP2_ACLKR_IN 101
1497 #define TISCI_DEV_BOARD0_MCASP2_ACLKR_OUT 102
1498 #define TISCI_DEV_BOARD0_MCASP2_ACLKX_IN 103
1499 #define TISCI_DEV_BOARD0_MCASP2_ACLKX_OUT 104
1500 #define TISCI_DEV_BOARD0_MCASP2_AFSR_IN 105
1501 #define TISCI_DEV_BOARD0_MCASP2_AFSR_OUT 106
1502 #define TISCI_DEV_BOARD0_MCASP2_AFSX_IN 107
1503 #define TISCI_DEV_BOARD0_MCASP2_AFSX_OUT 108
1504 #define TISCI_DEV_BOARD0_MCASP3_ACLKR_IN 109
1505 #define TISCI_DEV_BOARD0_MCASP3_ACLKR_OUT 110
1506 #define TISCI_DEV_BOARD0_MCASP3_ACLKX_IN 111
1507 #define TISCI_DEV_BOARD0_MCASP3_ACLKX_OUT 112
1508 #define TISCI_DEV_BOARD0_MCASP3_AFSR_IN 113
1509 #define TISCI_DEV_BOARD0_MCASP3_AFSR_OUT 114
1510 #define TISCI_DEV_BOARD0_MCASP3_AFSX_IN 115
1511 #define TISCI_DEV_BOARD0_MCASP3_AFSX_OUT 116
1512 #define TISCI_DEV_BOARD0_MCASP4_ACLKR_IN 117
1513 #define TISCI_DEV_BOARD0_MCASP4_ACLKR_OUT 118
1514 #define TISCI_DEV_BOARD0_MCASP4_ACLKX_IN 119
1515 #define TISCI_DEV_BOARD0_MCASP4_ACLKX_OUT 120
1516 #define TISCI_DEV_BOARD0_MCASP4_AFSR_IN 121
1517 #define TISCI_DEV_BOARD0_MCASP4_AFSR_OUT 122
1518 #define TISCI_DEV_BOARD0_MCASP4_AFSX_IN 123
1519 #define TISCI_DEV_BOARD0_MCASP4_AFSX_OUT 124
1520 #define TISCI_DEV_BOARD0_MCU_EXT_REFCLK0_OUT 125
1521 #define TISCI_DEV_BOARD0_MCU_I2C0_SCL_OUT 127
1522 #define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN 128
1523 #define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 129
1524 #define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 130
1525 #define TISCI_DEV_BOARD0_MCU_SPI0_CLK_IN 131
1526 #define TISCI_DEV_BOARD0_MCU_SPI0_CLK_OUT 132
1527 #define TISCI_DEV_BOARD0_MCU_SPI1_CLK_IN 133
1528 #define TISCI_DEV_BOARD0_MCU_SPI1_CLK_OUT 134
1529 #define TISCI_DEV_BOARD0_MCU_SYSCLKOUT0_IN 135
1530 #define TISCI_DEV_BOARD0_MCU_TIMER_IO0_IN 136
1531 #define TISCI_DEV_BOARD0_MCU_TIMER_IO1_IN 137
1532 #define TISCI_DEV_BOARD0_MCU_TIMER_IO2_IN 138
1533 #define TISCI_DEV_BOARD0_MCU_TIMER_IO3_IN 139
1534 #define TISCI_DEV_BOARD0_MDIO0_MDC_IN 140
1535 #define TISCI_DEV_BOARD0_MMC1_CLKLB_IN 143
1536 #define TISCI_DEV_BOARD0_MMC1_CLKLB_OUT 144
1537 #define TISCI_DEV_BOARD0_MMC1_CLK_IN 145
1538 #define TISCI_DEV_BOARD0_MMC1_CLK_OUT 146
1539 #define TISCI_DEV_BOARD0_MMC2_CLKLB_IN 147
1540 #define TISCI_DEV_BOARD0_MMC2_CLKLB_OUT 148
1541 #define TISCI_DEV_BOARD0_MMC2_CLK_IN 149
1542 #define TISCI_DEV_BOARD0_MMC2_CLK_OUT 150
1543 #define TISCI_DEV_BOARD0_OBSCLK0_IN 151
1544 #define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0 152
1545 #define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 153
1546 #define TISCI_DEV_BOARD0_OBSCLK1_IN 154
1547 #define TISCI_DEV_BOARD0_OBSCLK1_IN_PARENT_MAIN_OBSCLK_DIV_OUT0 155
1548 #define TISCI_DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 156
1549 #define TISCI_DEV_BOARD0_OSPI0_CLK_IN 157
1550 #define TISCI_DEV_BOARD0_OSPI0_DQS_OUT 158
1551 #define TISCI_DEV_BOARD0_OSPI0_LBCLKO_IN 159
1552 #define TISCI_DEV_BOARD0_OSPI0_LBCLKO_OUT 160
1553 #define TISCI_DEV_BOARD0_RGMII1_RXC_OUT 161
1554 #define TISCI_DEV_BOARD0_RGMII2_RXC_OUT 163
1555 #define TISCI_DEV_BOARD0_RMII1_REF_CLK_OUT 165
1556 #define TISCI_DEV_BOARD0_RMII2_REF_CLK_OUT 166
1557 #define TISCI_DEV_BOARD0_SPI0_CLK_IN 167
1558 #define TISCI_DEV_BOARD0_SPI0_CLK_OUT 168
1559 #define TISCI_DEV_BOARD0_SPI1_CLK_IN 169
1560 #define TISCI_DEV_BOARD0_SPI1_CLK_OUT 170
1561 #define TISCI_DEV_BOARD0_SPI2_CLK_IN 171
1562 #define TISCI_DEV_BOARD0_SPI2_CLK_OUT 172
1563 #define TISCI_DEV_BOARD0_SYSCLKOUT0_IN 173
1564 #define TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN 174
1565 #define TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0 175
1566 #define TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 176
1567 #define TISCI_DEV_BOARD0_TCK_OUT 177
1568 #define TISCI_DEV_BOARD0_TIMER_IO0_IN 178
1569 #define TISCI_DEV_BOARD0_TIMER_IO1_IN 179
1570 #define TISCI_DEV_BOARD0_TIMER_IO2_IN 180
1571 #define TISCI_DEV_BOARD0_TIMER_IO3_IN 181
1572 #define TISCI_DEV_BOARD0_TIMER_IO4_IN 182
1573 #define TISCI_DEV_BOARD0_TIMER_IO5_IN 183
1574 #define TISCI_DEV_BOARD0_TIMER_IO6_IN 184
1575 #define TISCI_DEV_BOARD0_TIMER_IO7_IN 185
1576 #define TISCI_DEV_BOARD0_TRC_CLK_IN 186
1577 #define TISCI_DEV_BOARD0_VOUT0_EXTPCLKIN_OUT 187
1578 #define TISCI_DEV_BOARD0_VOUT0_PCLK_IN 188
1579 #define TISCI_DEV_BOARD0_VOUT0_PCLK_IN_PARENT_K3_DSS_UL_MAIN_0_DPI_1_OUT_CLK 190
1580 #define TISCI_DEV_BOARD0_VOUT0_PCLK_IN_PARENT_K3_DSS_UL_MAIN_1_DPI_0_OUT_CLK 191
1581 #define TISCI_DEV_BOARD0_VOUT0_PCLK_IN_PARENT_K3_DSS_UL_MAIN_1_DPI_1_OUT_CLK 192
1582 #define TISCI_DEV_BOARD0_WKUP_I2C0_SCL_OUT 194
1583 #define TISCI_DEV_BOARD0_CSI0_RXCLKN_OUT 195
1584 #define TISCI_DEV_BOARD0_CSI0_RXCLKP_OUT 196
1585 #define TISCI_DEV_BOARD0_CSI1_RXCLKN_OUT 197
1586 #define TISCI_DEV_BOARD0_CSI1_RXCLKP_OUT 198
1587 #define TISCI_DEV_BOARD0_CSI2_RXCLKN_OUT 199
1588 #define TISCI_DEV_BOARD0_CSI2_RXCLKP_OUT 200
1589 #define TISCI_DEV_BOARD0_CSI3_RXCLKN_OUT 201
1590 #define TISCI_DEV_BOARD0_CSI3_RXCLKP_OUT 202
1592 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK 0
1593 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 1
1594 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8 2
1595 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3_DUP0 3
1596 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT 4
1598 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK 0
1599 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT 1
1600 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK 2
1601 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK 3
1602 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK 4
1603 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 5
1604 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
1605 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 7
1607 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK 0
1608 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 1
1609 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
1610 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK 3
1611 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK_DUP0 4
1612 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 5
1613 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 6
1614 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8 7
1615 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK 8
1616 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 9
1618 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK 0
1619 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK 1
1620 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK 2
1621 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 3
1622 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1 4
1623 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 5
1624 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 6
1625 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_16_HSDIVOUT0_CLK8 7
1626 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK 8
1627 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK 9
1628 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 10
1629 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT0_CLK2 11
1630 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM67_C7XV_WRAP_MAIN_0_CLOCK_CONTROL_0_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK 12
1631 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK 13
1632 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM67_GPU_BXS464_WRAP_MAIN_0_GPU_DCC_CLK4 14
1633 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK2 15
1634 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK 16
1635 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM67_DDR_WRAP_MAIN_0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK 17
1636 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 18
1637 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8 19
1638 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 20
1639 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 21
1640 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 22
1642 #define TISCI_DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK 0
1643 #define TISCI_DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK 1
1644 #define TISCI_DEV_DSS1_DPI1_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK 2
1646 #define TISCI_DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK 0
1647 #define TISCI_DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK 1
1648 #define TISCI_DEV_DSS1_DPI0_PLLSEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK 2
1650 #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK 0
1651 #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1652 #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_WKUP_CLKSEL_OUT04 2
1653 #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1654 #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK 4
1655 #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
1656 #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 6
1657 #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 7
1658 #define TISCI_DEV_WKUP_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 8
1660 #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK 0
1661 #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1662 #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 2
1663 #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1664 #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK 4
1665 #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
1666 #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 6
1667 #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 7
1668 #define TISCI_DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 8
1670 #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK 0
1671 #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1672 #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 2
1673 #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
1674 #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK 4
1675 #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
1676 #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 6
1677 #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 7
1678 #define TISCI_DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 8
1680 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK 0
1681 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1682 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1683 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 3
1684 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1 4
1685 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
1686 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
1687 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
1688 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
1689 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 9
1690 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 10
1691 #define TISCI_DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 11
1693 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK 0
1694 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1695 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1696 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 3
1697 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1 4
1698 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
1699 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
1700 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
1701 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
1702 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 9
1703 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 10
1704 #define TISCI_DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 11
1706 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK 0
1707 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1708 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1709 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 3
1710 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1 4
1711 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
1712 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
1713 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
1714 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
1715 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 9
1716 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 10
1717 #define TISCI_DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 11
1719 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK 0
1720 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
1721 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
1722 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF0 3
1723 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_3GUSS_AM67_MAIN_0_CPTS_GENF1 4
1724 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
1725 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
1726 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
1727 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
1728 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 9
1729 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 10
1730 #define TISCI_DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 11
1732 #define TISCI_DEV_DPI0_OUT_SEL_DEV_VD_CLK 0
1733 #define TISCI_DEV_DPI0_OUT_SEL_DEV_VD_CLK_PARENT_K3_DSS_UL_MAIN_0_DPI_1_OUT_CLK 1
1734 #define TISCI_DEV_DPI0_OUT_SEL_DEV_VD_CLK_PARENT_K3_DSS_UL_MAIN_1_DPI_0_OUT_CLK 2
1735 #define TISCI_DEV_DPI0_OUT_SEL_DEV_VD_CLK_PARENT_K3_DSS_UL_MAIN_1_DPI_1_OUT_CLK 3