J722S MCU+ SDK  09.02.00
sdl_ecc_soc.h
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1 /*
2  * Copyright (C) 2024 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31  */
41 #ifndef INCLUDE_SDL_ECC_SOC_H_
42 #define INCLUDE_SDL_ECC_SOC_H_
43 
44 
45 #include <stdint.h>
46 #include <sdl/sdl_ecc.h>
47 #include <sdl/ecc/sdl_ip_ecc.h>
48 #include <sdl/include/sdl_types.h>
49 #include <sdl/esm/soc/j722s/sdl_esm_core.h>
51 #include <sdl/ecc/sdl_ecc_priv.h>
52 #include <sdl/include/j722s/sdlr_soc_ecc_aggr.h>
53 #include <sdl/include/j722s/sdlr_intr_esm0.h>
54 #include <sdl/include/j722s/sdlr_intr_wkup_esm0.h>
55 #include <sdl/include/j722s/sdlr_soc_baseaddress.h>
56 
57 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
58 #define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
59 #define SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
60 #define SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES (0U)
61 #define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
62 #define SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
63 #define SDL_WKUP_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES (0U)
64 #define SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (6U)
65 #define SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
66 #define SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
67 #define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (0U)
68 #define SDL_WKUP_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES (0U)
69 #define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
70 #define SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
71 #define SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (3U)
72 #define SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
73 #define SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
74 #define SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
75 #define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
76 #define SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
77 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
78 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
79 #define SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (16U)
80 #define SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
81 #define SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
82 #define SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
83 #define SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES (2U)
84 #define SDL_WKUP_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (0U)
85 #define SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES (28U)
86 #define SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
87 #define SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
88 #define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
89 #define SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
90 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
91 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
92 #define SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
93 #define SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (6U)
94 #define SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
95 #define SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (62U)
96 #define SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
97 #define SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
98 #define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
99 #define SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
100 #define SDL_MCU_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (2U)
101 #define SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
102 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
103 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
104 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
105 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
106 #define SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (12U)
107 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES (27U)
108 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES (27U)
109 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES (27U)
110 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES (27U)
111 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES (24U)
112 #define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
113 #define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
114 #define SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (4U)
115 #define SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (4U)
116 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (58U)
117 
123 {
124  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
125  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
126  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
127  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
128  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
129  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
130  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
131  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
132  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
133  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
134  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
135  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
136  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
137  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
138  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
139  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
140  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
141  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
142  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
143  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
144  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
145  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
146  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
147  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
148  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
149  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
150  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
151  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
152  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
153  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
154  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
155  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
156  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
157  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
158  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
159  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
160  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
161  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
162  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
163  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
164  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
165  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
166  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
167  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
168  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
169  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
170  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
171  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
172  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
173  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
174  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
175  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
176  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
177  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
178  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
179  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
180  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
181  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
182  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
183  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
184  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
185  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
186  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
187  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID, 0u,
188  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_SIZE, 4u,
189  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
190  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID, 0u,
191  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_SIZE, 4u,
192  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
193  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID, 0u,
194  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_SIZE, 4u,
195  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
196  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID, 0u,
197  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_SIZE, 4u,
198  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
199  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID, 0u,
200  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_SIZE, 4u,
201  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
202  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID, 0u,
203  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_SIZE, 4u,
204  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
205  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID, 0u,
206  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_SIZE, 4u,
207  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ROW_WIDTH, ((bool)false) },
208  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
209  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
210  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
211 };
212 
218 {
219  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
220  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
221  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
222  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
223  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
224  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
225  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
226  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
227  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
228  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
229  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
230  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
231  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
232  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
233  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
234  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
235  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
236  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
237  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
238  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
239  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
240  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
241  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
242  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
243  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
244  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
245  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
246  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
247  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
248  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
249  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
250  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
251  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
252  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
253  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
254  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
255  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
256  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
257  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
258  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
259  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
260  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
261  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
262  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
263  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
264  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
265  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
266  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
267  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
268  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
269  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
270  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
271  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
272  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
273  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
274  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
275  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
276  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
277  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
278  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
279  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
280  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
281  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
282  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID, 0u,
283  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_SIZE, 4u,
284  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
285  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID, 0u,
286  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_SIZE, 4u,
287  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
288  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID, 0u,
289  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_SIZE, 4u,
290  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
291  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID, 0u,
292  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_SIZE, 4u,
293  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
294  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID, 0u,
295  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_SIZE, 4u,
296  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
297  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID, 0u,
298  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_SIZE, 4u,
299  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
300  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID, 0u,
301  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_SIZE, 4u,
302  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ROW_WIDTH, ((bool)false) },
303  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
304  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
305  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
306 };
307 
313 static const SDL_GrpChkConfig_t SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries[SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
314 {
315  { SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
316  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_0_WIDTH },
317  { SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
318  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_1_WIDTH },
319 };
320 
326 {
327  { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0u,
328  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
329  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
330 };
331 
337 {
338  { SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0x0000900000u,
339  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
340  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
341 };
342 
348 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
349 {
350  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
351  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
352  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
353  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
354  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
355  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
356  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
357  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
358  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
359  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
360  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
361  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
362  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
363  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
364  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
365  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
366  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
367  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
368  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
369  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
370  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
371  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
372  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
373  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
374  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
375  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
376  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
377  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
378  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
379  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
380  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
381  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
382  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
383  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
384  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
385  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
386  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
387  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
388  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
389  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
390  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
391  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
392  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
393  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
394  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
395  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
396  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
397  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
398  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
399  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
400  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
401  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
402  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
403  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
404  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
405  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
406  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
407  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
408  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
409  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
410  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
411  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
412  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
413  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
414  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
415  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
416  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
417  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
418  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
419  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
420  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
421  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
422  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
423  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
424  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
425  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
426  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
427  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
428  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
429  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
430  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
431  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
432  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
433  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
434  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
435  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
436  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
437  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
438  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
439  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
440  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
441  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
442  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
443  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
444  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
445  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
446  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
447  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
448  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
449  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
450  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
451  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
452  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
453  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
454  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
455  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
456  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
457  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
458  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
459  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
460  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
461  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
462  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
463  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
464  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
465  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
466  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
467  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
468  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
469  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
470  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
471  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
472  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
473  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
474  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
475  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
476  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
477  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
478  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
479  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
480  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
481  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
482  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
483  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
484  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
485  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
486  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
487  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
488  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
489  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
490  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
491  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
492  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
493  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
494  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
495  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
496  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
497  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
498  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
499  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
500  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
501  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
502  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
503  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
504  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
505  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
506  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
507  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
508  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
509  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
510  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
511  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
512  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
513  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
514  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
515  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
516  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
517  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
518  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
519  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
520  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
521  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
522  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
523  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
524  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
525  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
526  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
527  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
528  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
529  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
530  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
531  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
532  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
533  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
534  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
535  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
536  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
537  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
538  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
539  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
540  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
541  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
542  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
543  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
544  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
545  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
546  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
547  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
548  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
549  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
550  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
551  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
552  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
553  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
554  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
555  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
556  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
557  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
558  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
559  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
560  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
561  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
562  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
563  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
564  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
565  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
566  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
567  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
568  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
569  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
570  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
571  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
572  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
573  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
574  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
575  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
576  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
577  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
578  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
579  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
580  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
581  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
582  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
583  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
584  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
585  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
586  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
587  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
588  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
589  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
590  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
591  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
592  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
593  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
594  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
595  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
596  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
597  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
598  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
599  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
600  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
601  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
602  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
603  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
604  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
605  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
606  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
607  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
608  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
609  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
610  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
611  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
612  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
613  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
614  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
615  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
616  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
617  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
618  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
619  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
620  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
621  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
622  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
623  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
624  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
625  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
626  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
627  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
628  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
629  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
630  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
631  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
632  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
633  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
634  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
635  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
636  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
637  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
638  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
639  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
640  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
641  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
642  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
643  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
644  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
645  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
646  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
647  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
648  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
649  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
650  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
651  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
652  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
653  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
654  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
655  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
656  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
657  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
658  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
659  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
660  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
661  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
662  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
663  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
664  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
665  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
666  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
667  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
668  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
669  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
670  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
671  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
672  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
673  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
674  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
675  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
676  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
677  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
678  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
679  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
680  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
681  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
682  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
683  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
684  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
685  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
686  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
687  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
688  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
689  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
690  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
691  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
692  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
693  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
694  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
695  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
696  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
697  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
698  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
699  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
700  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
701  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
702  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
703  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
704  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
705  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
706  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
707  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
708  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
709  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
710  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
711  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
712  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
713  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
714  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
715  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
716  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
717  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
718  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
719  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
720  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
721  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
722  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
723  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
724  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
725  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
726  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
727  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
728  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
729  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
730  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
731  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
732  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
733  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
734  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
735  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
736  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
737  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
738  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
739  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
740  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
741  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
742  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
743  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
744  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
745  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
746  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
747  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
748  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
749  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
750  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
751  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
752  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
753  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
754  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
755  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
756  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
757  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
758  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
759  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
760  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
761  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
762  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
763  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
764  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
765  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
766  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
767  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
768  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
769  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
770  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
771  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
772  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
773  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
774  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
775  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
776  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
777  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
778  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
779  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
780  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
781  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
782  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
783  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
784  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
785  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
786  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
787  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
788  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
789  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
790  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
791  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
792  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
793  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
794  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
795  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
796  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
797  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
798  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
799  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
800  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
801  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
802  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
803  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
804  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
805  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
806  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
807  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
808  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
809  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
810  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
811  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
812  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
813  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
814  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
815  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
816  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
817  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
818  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
819  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
820  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
821  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
822  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
823  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
824  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
825  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
826  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
827  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
828  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
829  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
830  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
831  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
832  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
833  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
834  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
835  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
836  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
837  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
838  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
839  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
840  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
841  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
842  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
843  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
844  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
845  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
846  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
847  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
848  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
849  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
850  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
851  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
852  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
853  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
854  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
855  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
856  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
857  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
858  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
859  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
860  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
861  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
862 };
863 
869 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
870 {
871  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
872  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
873  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
874  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
875  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
876  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
877  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
878  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
879  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
880  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
881  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
882  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
883  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
884  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
885  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
886  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
887  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
888  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
889  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
890  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
891  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
892  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
893  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
894  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
895  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
896  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
897  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
898  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
899  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
900  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
901  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
902  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
903  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
904  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
905  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
906  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
907  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
908  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
909  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
910  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
911  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
912  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
913  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
914  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
915  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
916  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
917  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
918  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
919  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
920  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
921  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
922  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
923  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
924  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
925  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
926  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
927  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
928  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
929  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
930  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
931  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
932  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
933  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
934  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
935  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
936  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
937  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
938  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
939  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
940  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
941  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
942  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
943  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
944  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
945  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
946  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
947  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
948  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
949  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
950  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
951  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
952  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
953  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
954  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
955  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
956  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
957  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
958  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
959  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
960  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
961  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
962  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
963  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
964  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
965  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
966  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
967  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
968  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
969  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
970  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
971  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
972  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
973  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
974  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
975  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
976  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
977  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
978  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
979  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
980  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
981  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
982  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
983  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
984  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
985  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
986  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
987  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
988  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
989  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
990  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
991  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
992  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
993  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
994  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
995  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
996  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
997  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
998  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
999  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
1000  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
1001  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
1002  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
1003  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
1004  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
1005  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
1006  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
1007  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
1008  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
1009  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
1010  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
1011  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
1012  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
1013  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
1014  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
1015  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
1016  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
1017  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
1018  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
1019  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
1020  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
1021  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
1022  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
1023  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
1024  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
1025  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
1026  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
1027  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
1028  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
1029  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
1030  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
1031  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
1032  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
1033  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
1034  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
1035  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
1036  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
1037  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
1038  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
1039  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
1040  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
1041  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
1042  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
1043  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
1044  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
1045  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
1046  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
1047  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
1048  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
1049  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
1050  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
1051  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
1052  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
1053  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
1054  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
1055  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
1056  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
1057  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
1058  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
1059  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
1060  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
1061  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
1062  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
1063  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
1064  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
1065  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
1066  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
1067  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
1068  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
1069  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
1070  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
1071  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
1072  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
1073  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
1074  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
1075  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
1076  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
1077  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
1078  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
1079  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
1080  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
1081  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
1082  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
1083  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
1084  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
1085  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
1086  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
1087  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
1088  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
1089  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
1090  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
1091  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
1092  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
1093  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
1094  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
1095  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
1096  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
1097  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
1098  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
1099  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
1100  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
1101  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
1102  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
1103  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
1104  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
1105  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
1106  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
1107  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
1108  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
1109  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
1110  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
1111  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
1112  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
1113  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
1114  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
1115  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
1116  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
1117  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
1118  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
1119  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
1120  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
1121  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
1122  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
1123  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
1124  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
1125  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
1126  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
1127  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
1128  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
1129  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
1130  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
1131  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
1132  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
1133  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
1134  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
1135  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
1136  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
1137  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
1138  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
1139  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
1140  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
1141  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
1142  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
1143  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
1144  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
1145  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
1146  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
1147  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
1148  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
1149  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
1150  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
1151  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
1152  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
1153  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
1154  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
1155  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
1156  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
1157  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
1158  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
1159  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
1160  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
1161  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
1162  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
1163  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
1164  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
1165  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
1166  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
1167  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
1168  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
1169  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
1170  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
1171  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
1172  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
1173  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
1174  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
1175  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
1176  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
1177  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
1178  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
1179  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
1180  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
1181  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
1182  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
1183  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
1184  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
1185  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
1186  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
1187  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
1188  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
1189  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
1190  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
1191  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
1192  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
1193  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
1194  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
1195  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
1196  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
1197  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
1198  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
1199  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
1200  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
1201  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
1202  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
1203  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
1204  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
1205  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
1206  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
1207  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
1208  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
1209  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
1210  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
1211  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
1212  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
1213  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
1214  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
1215  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
1216  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
1217  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
1218  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
1219  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
1220  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
1221  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
1222  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
1223  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
1224  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
1225  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
1226  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
1227  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
1228  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
1229  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
1230  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
1231  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
1232  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
1233  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
1234  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
1235  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
1236  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
1237  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
1238  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
1239  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
1240  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
1241  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
1242  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
1243  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
1244  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
1245  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
1246  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
1247  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
1248  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
1249  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
1250  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
1251  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
1252  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
1253  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
1254  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
1255  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
1256  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
1257  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
1258  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
1259  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
1260  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
1261  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
1262  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
1263  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
1264  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
1265  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
1266  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
1267  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
1268  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
1269  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
1270  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
1271  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
1272  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
1273  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
1274  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
1275  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
1276  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
1277  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
1278  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
1279  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
1280  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
1281  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
1282  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
1283  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
1284  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
1285  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
1286  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
1287  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
1288  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
1289  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
1290  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
1291  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
1292  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
1293  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
1294  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
1295  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
1296  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
1297  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
1298  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
1299  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
1300  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
1301  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
1302  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
1303  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
1304  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
1305  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
1306  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
1307  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
1308  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
1309  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
1310  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
1311  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
1312  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
1313  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
1314  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
1315  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
1316  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
1317  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
1318  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
1319  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
1320  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
1321  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
1322  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
1323  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
1324  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
1325  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
1326  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
1327  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
1328  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
1329  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
1330  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
1331  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
1332  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
1333  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
1334  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
1335  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
1336  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
1337  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
1338  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
1339  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
1340  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
1341  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
1342  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
1343  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
1344  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
1345  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
1346  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
1347 };
1348 
1354 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
1355 {
1356  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1357  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1358  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1359  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1360  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1361  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1362  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1363  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1364  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1365  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1366  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1367  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1368  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1369  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1370  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1371  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1372  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1373  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1374  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1375  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1376  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1377  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1378  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1379  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1380  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1381  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1382  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1383  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1384  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1385  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1386  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1387  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1388  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1389  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1390  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1391  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1392  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1393  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1394  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1395  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1396  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1397  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1398  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1399  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1400  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1401  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1402  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1403  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1404  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1405  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1406  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1407  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1408  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1409  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1410  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1411  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1412  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1413  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1414  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1415  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1416  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1417  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1418  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1419  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1420  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1421  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1422  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1423  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1424  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1425  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1426  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1427  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1428  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1429  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1430  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1431  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1432  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1433  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1434  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1435  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1436  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1437  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1438  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1439  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1440  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1441  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1442  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1443  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1444  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1445  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1446  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1447  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1448  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1449  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1450  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1451  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1452  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1453  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1454  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1455  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1456  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1457  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1458  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1459  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1460  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1461  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1462 };
1463 
1469 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
1470 {
1471  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
1472  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
1473  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
1474  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
1475  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
1476  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
1477  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
1478  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
1479  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
1480  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
1481  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
1482  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
1483  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
1484  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
1485  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
1486  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
1487  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
1488  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
1489  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
1490  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
1491  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
1492  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
1493  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
1494  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
1495  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
1496  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
1497  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
1498  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
1499  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
1500  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
1501  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
1502  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
1503  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
1504  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
1505  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
1506  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
1507  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
1508  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
1509  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
1510  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
1511  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
1512  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
1513  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
1514  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
1515  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
1516  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
1517  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
1518  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
1519  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
1520  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
1521  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
1522  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
1523  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
1524  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
1525  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
1526  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
1527  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
1528  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
1529  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
1530  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
1531  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
1532  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
1533  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
1534  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
1535  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
1536  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
1537  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
1538  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
1539  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
1540  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
1541  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
1542  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
1543  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
1544  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
1545  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
1546  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
1547  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
1548  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
1549  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
1550  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
1551  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
1552  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
1553  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
1554  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
1555  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
1556  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
1557  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
1558  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
1559  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
1560  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
1561  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
1562  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
1563  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
1564  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
1565  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
1566  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
1567  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
1568  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
1569  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
1570  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
1571  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
1572  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
1573  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
1574  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
1575  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
1576  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
1577  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
1578  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
1579  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
1580  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
1581  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
1582  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
1583  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
1584  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
1585  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
1586  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
1587  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
1588  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
1589  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
1590  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
1591  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
1592  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
1593  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
1594  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
1595  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
1596  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
1597  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
1598  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
1599  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
1600  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
1601  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
1602  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
1603  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
1604  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
1605  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
1606  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
1607  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
1608  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
1609  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
1610  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
1611  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
1612  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
1613  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
1614  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
1615  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
1616  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
1617  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
1618  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
1619  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
1620  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
1621  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
1622  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
1623  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
1624  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
1625  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
1626  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
1627  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
1628  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
1629  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
1630  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
1631  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
1632  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
1633  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
1634  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
1635  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
1636  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
1637  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
1638  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
1639  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
1640  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
1641  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
1642  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
1643  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
1644  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
1645  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
1646  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
1647  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
1648  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
1649  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
1650  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
1651  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
1652  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
1653  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
1654  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
1655  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
1656  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
1657  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
1658  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
1659  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
1660  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
1661  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
1662  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
1663  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
1664  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
1665  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
1666  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
1667  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
1668  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
1669  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
1670  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
1671  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
1672  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
1673  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
1674  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
1675  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
1676  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
1677  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
1678  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
1679  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
1680  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
1681  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
1682  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
1683  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
1684  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
1685  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
1686  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
1687  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
1688  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
1689  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
1690  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
1691  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
1692  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
1693  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
1694  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
1695  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
1696  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
1697  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
1698  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
1699  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
1700  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
1701  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
1702  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
1703  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
1704  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
1705  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
1706  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
1707  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
1708  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
1709  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
1710  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
1711  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
1712  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
1713  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
1714  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
1715  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
1716  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
1717  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
1718  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
1719  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
1720  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
1721  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
1722  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
1723  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
1724  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
1725  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
1726  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
1727  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
1728  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
1729  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
1730  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
1731  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
1732  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
1733  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
1734  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
1735  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
1736  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
1737  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
1738  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
1739  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
1740  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
1741  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
1742  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
1743  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
1744  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
1745  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
1746  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
1747  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
1748  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
1749  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
1750  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
1751  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
1752  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
1753  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
1754  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
1755  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
1756  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
1757  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
1758  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
1759  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
1760  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
1761  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
1762  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
1763  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
1764  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
1765  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
1766  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
1767  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
1768  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
1769  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
1770  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
1771  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
1772  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
1773  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
1774  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
1775  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
1776  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
1777  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
1778  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
1779  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
1780  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
1781  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
1782  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
1783  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
1784  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
1785  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
1786  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
1787  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
1788  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
1789  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
1790  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
1791  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
1792  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
1793  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
1794  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
1795  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
1796  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
1797  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
1798  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
1799  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
1800  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
1801  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
1802  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
1803  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
1804  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
1805  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
1806  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
1807  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
1808  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
1809  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
1810  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
1811  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
1812  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
1813  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
1814  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
1815  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
1816  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
1817  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
1818  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
1819  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
1820  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
1821  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
1822  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
1823  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
1824  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
1825  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
1826  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
1827  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
1828  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
1829  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
1830  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
1831  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
1832  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
1833  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
1834  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
1835  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
1836  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
1837  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
1838  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
1839  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
1840  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
1841  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
1842  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
1843  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
1844  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
1845  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
1846  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
1847  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
1848  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
1849  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
1850  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
1851  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
1852  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
1853  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
1854  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
1855  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
1856  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
1857  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
1858  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
1859  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
1860  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
1861  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
1862  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
1863  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
1864  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
1865  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
1866  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
1867  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
1868  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
1869  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
1870  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
1871  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
1872  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
1873  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
1874  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
1875  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
1876  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
1877  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
1878  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
1879  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
1880  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
1881  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
1882  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
1883  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
1884  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
1885  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
1886  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
1887  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
1888  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
1889  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
1890  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
1891  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
1892  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
1893  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
1894  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
1895  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
1896  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
1897  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
1898  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
1899  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
1900  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
1901  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
1902  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
1903  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
1904  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
1905  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
1906  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
1907  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
1908  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
1909  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
1910  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
1911  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
1912  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
1913  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
1914  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
1915  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
1916  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
1917  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
1918  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
1919  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
1920  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
1921  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
1922  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
1923  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
1924  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
1925  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
1926  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
1927  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
1928  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
1929  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
1930  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
1931  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
1932  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
1933  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
1934  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
1935  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
1936  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
1937  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
1938  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
1939  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
1940  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
1941  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
1942  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
1943  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
1944  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
1945  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
1946  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
1947  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
1948  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
1949  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
1950  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
1951  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
1952  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
1953  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
1954  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
1955  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
1956  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
1957  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
1958  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
1959  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
1960  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
1961  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
1962  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
1963  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
1964  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
1965  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
1966  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
1967  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
1968  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
1969  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
1970  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
1971  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
1972  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
1973  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
1974  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
1975  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
1976  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
1977  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
1978  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
1979  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
1980  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
1981  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
1982  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
1983 };
1984 
1990 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
1991 {
1992  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
1993  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
1994  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
1995  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
1996  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
1997  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
1998  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
1999  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
2000  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
2001  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
2002  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
2003  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
2004  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
2005  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
2006  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
2007  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
2008  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
2009  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
2010  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
2011  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
2012  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
2013  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
2014  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
2015  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
2016  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
2017  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
2018  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
2019  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
2020  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
2021  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
2022  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
2023  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
2024  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
2025  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
2026  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
2027  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
2028  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
2029  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
2030  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
2031  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
2032  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
2033  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
2034  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
2035  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
2036  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
2037  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
2038  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
2039  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
2040  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
2041  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
2042  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
2043  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
2044  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
2045  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
2046  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
2047  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
2048  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
2049  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
2050  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
2051  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
2052  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
2053  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
2054  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
2055  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
2056  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
2057  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
2058  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
2059  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
2060  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
2061  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
2062  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
2063  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
2064  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
2065  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
2066  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
2067  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
2068  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
2069  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
2070  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
2071  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
2072  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
2073  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
2074  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
2075  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
2076  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
2077  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
2078  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
2079  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
2080  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
2081  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
2082  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
2083  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
2084  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
2085  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
2086  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
2087  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
2088  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
2089  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
2090  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
2091  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
2092  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
2093  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
2094  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
2095  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
2096  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
2097  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
2098  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
2099  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
2100  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
2101  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
2102  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
2103  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
2104  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
2105  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
2106  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
2107  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
2108  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
2109  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
2110  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
2111  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
2112  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
2113  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
2114  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
2115  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
2116  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
2117  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
2118  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
2119  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
2120  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
2121  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
2122  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
2123  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
2124  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
2125  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
2126  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
2127  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
2128  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
2129  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
2130  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
2131  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
2132  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
2133  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
2134  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
2135  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
2136  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
2137  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
2138  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
2139  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
2140  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
2141  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
2142  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
2143  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
2144  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
2145  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
2146  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
2147  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
2148  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
2149  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
2150  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
2151  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
2152  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
2153  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
2154  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
2155  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
2156  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
2157  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
2158  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
2159  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
2160  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
2161  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
2162  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
2163  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
2164  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
2165  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
2166  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
2167  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
2168  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
2169  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
2170  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
2171  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
2172  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
2173  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
2174  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
2175  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
2176  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
2177  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
2178  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
2179  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
2180  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
2181  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
2182  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
2183  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
2184  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
2185  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
2186  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
2187  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
2188  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
2189  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
2190  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
2191  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
2192  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
2193  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
2194  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
2195  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
2196  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
2197  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
2198  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
2199  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
2200  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
2201  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
2202  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
2203  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
2204  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
2205  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
2206  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
2207  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
2208  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
2209  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
2210  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
2211  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
2212  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
2213  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
2214  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
2215  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
2216  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
2217  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
2218  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
2219  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
2220  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
2221  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
2222  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
2223  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
2224  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
2225  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
2226  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
2227  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
2228  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
2229  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
2230  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
2231  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
2232  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
2233  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
2234  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
2235  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
2236  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
2237  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
2238  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
2239  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
2240  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
2241  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
2242  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
2243  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
2244  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
2245  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
2246  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
2247  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
2248  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
2249  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
2250  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
2251  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
2252  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
2253  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
2254  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
2255  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
2256  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
2257  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
2258  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
2259  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
2260  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
2261  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
2262  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
2263  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
2264  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
2265  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
2266  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
2267  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
2268  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
2269  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
2270  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
2271  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
2272  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
2273  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
2274  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
2275  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
2276  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
2277  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
2278  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
2279  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
2280  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
2281  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
2282  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
2283  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
2284  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
2285  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
2286  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
2287  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
2288  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
2289  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
2290  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
2291  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
2292  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
2293  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
2294  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
2295  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
2296  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
2297  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
2298  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
2299  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
2300  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
2301  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
2302  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
2303  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
2304  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
2305  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
2306  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
2307  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
2308  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
2309  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
2310  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
2311  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
2312  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
2313  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
2314  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
2315  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
2316  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
2317  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
2318  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
2319  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
2320  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
2321  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
2322  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
2323  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
2324  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
2325  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
2326  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
2327  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
2328  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
2329  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
2330  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
2331  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
2332  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
2333  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
2334  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
2335  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
2336  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
2337  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
2338  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
2339  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
2340  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
2341  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
2342  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
2343  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
2344  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
2345  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
2346  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
2347  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
2348  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
2349  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
2350  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
2351  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
2352  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
2353  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
2354  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
2355  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
2356  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
2357  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
2358  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
2359  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
2360  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
2361  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
2362  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
2363  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
2364  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
2365  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
2366  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
2367  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
2368  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
2369  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
2370  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
2371  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
2372  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
2373  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
2374  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
2375  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
2376  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
2377  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
2378  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
2379  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
2380  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
2381  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
2382  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
2383  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
2384  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
2385  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
2386  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
2387  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
2388  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
2389  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
2390  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
2391  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
2392  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
2393  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
2394  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
2395  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
2396  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
2397  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
2398  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
2399  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
2400  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
2401  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
2402  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
2403  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
2404  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
2405  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
2406  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
2407  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
2408  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
2409  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
2410  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
2411  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
2412  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
2413  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
2414  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
2415  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
2416  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
2417  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
2418  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
2419  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
2420  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
2421  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
2422  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
2423  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
2424  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
2425  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
2426  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
2427  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
2428  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
2429  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
2430  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
2431  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
2432  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
2433  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
2434  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
2435  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
2436  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
2437  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
2438  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
2439  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
2440  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
2441  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
2442  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
2443  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
2444  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
2445  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
2446  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
2447  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
2448  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
2449  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
2450  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
2451  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
2452  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
2453  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
2454  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
2455  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
2456  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
2457  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
2458  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
2459  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
2460  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
2461  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
2462  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
2463  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
2464  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
2465  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
2466  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
2467  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
2468  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
2469  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
2470  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
2471  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
2472  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
2473  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
2474  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
2475  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
2476  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
2477  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
2478  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
2479  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
2480  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
2481  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
2482  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
2483  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
2484  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
2485  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
2486  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
2487  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
2488  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
2489  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
2490  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
2491  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
2492  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
2493  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
2494  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
2495  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
2496  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
2497  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
2498  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
2499  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
2500  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
2501  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
2502  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
2503  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
2504 };
2505 
2511 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
2512 {
2513  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
2514  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
2515  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
2516  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
2517  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
2518  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
2519  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
2520  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
2521  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
2522  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
2523  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
2524  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
2525  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
2526  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
2527  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
2528  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
2529  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
2530  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
2531  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
2532  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
2533  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
2534  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
2535  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
2536  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
2537  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
2538  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
2539  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
2540  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
2541  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
2542  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
2543  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
2544  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
2545  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
2546  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
2547  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
2548  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
2549  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
2550  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
2551  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
2552  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
2553  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
2554  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
2555  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
2556  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
2557  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
2558  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
2559  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
2560  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
2561  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
2562  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
2563  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
2564  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
2565  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
2566  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
2567  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
2568  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
2569  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
2570  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
2571  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
2572  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
2573  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
2574  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
2575  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
2576  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
2577  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
2578  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
2579  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
2580  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
2581  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
2582  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
2583  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
2584  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
2585  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
2586  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
2587  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
2588  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
2589  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
2590  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
2591  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
2592  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
2593  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
2594  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
2595  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
2596  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
2597  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
2598  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
2599  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
2600  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
2601  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
2602  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
2603  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
2604  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
2605  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
2606  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
2607  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
2608  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
2609  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
2610  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
2611  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
2612  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
2613  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
2614  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
2615  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
2616  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
2617  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
2618  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
2619  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
2620  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
2621  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
2622  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
2623  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
2624  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
2625  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
2626  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
2627  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
2628  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
2629  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
2630  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
2631  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
2632  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
2633  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
2634  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
2635  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
2636  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
2637  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
2638  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
2639  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
2640  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
2641  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
2642  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
2643  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
2644  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
2645  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
2646  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
2647  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
2648  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
2649  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
2650  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
2651  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
2652  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
2653  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
2654  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
2655  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
2656  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
2657  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
2658  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
2659  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
2660  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
2661  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
2662  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
2663  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
2664  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
2665  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
2666  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
2667  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
2668  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
2669  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
2670  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
2671  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
2672  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
2673  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
2674  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
2675  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
2676  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
2677  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
2678  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
2679  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
2680  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
2681  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
2682  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
2683  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
2684  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
2685  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
2686  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
2687  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
2688  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
2689  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
2690  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
2691  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
2692  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
2693  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
2694  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
2695  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
2696  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
2697  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
2698  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
2699  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
2700  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
2701  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
2702  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
2703  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
2704  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
2705  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
2706  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
2707  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
2708  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
2709  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
2710  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
2711  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
2712  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
2713  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
2714  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
2715  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
2716  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
2717  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
2718  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
2719  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
2720  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
2721  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
2722  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
2723  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
2724  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
2725  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
2726  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
2727  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
2728  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
2729  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
2730  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
2731  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
2732  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
2733  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
2734  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
2735  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
2736  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
2737  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
2738  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
2739  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
2740  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
2741  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
2742  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
2743  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
2744  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
2745  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
2746  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
2747  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
2748  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
2749  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
2750  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
2751  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
2752  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
2753  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
2754  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
2755  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
2756  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
2757  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
2758  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
2759  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
2760  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
2761  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
2762  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
2763  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
2764  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
2765  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
2766  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
2767  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
2768  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
2769  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
2770  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
2771  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
2772  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
2773  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
2774  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
2775  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
2776  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
2777  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
2778  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
2779  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
2780  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
2781  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
2782  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
2783  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
2784  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
2785  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
2786  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
2787  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
2788  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
2789  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
2790  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
2791  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
2792  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
2793  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
2794  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
2795  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
2796  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
2797  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
2798  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
2799  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
2800  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
2801  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
2802  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
2803  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
2804  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
2805  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
2806  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
2807  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
2808  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
2809  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
2810  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
2811  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
2812  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
2813  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
2814  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
2815  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
2816  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
2817  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
2818  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
2819  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
2820  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
2821  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
2822  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
2823  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
2824  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
2825  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
2826  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
2827  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
2828  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
2829  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
2830  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
2831  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
2832  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
2833  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
2834  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
2835  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
2836  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
2837  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
2838  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
2839  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
2840  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
2841  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
2842  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
2843  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
2844  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
2845  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
2846  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
2847  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
2848  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
2849  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
2850  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
2851  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
2852  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
2853  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
2854  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
2855  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
2856  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
2857 };
2858 
2864 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
2865 {
2866  { SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
2867  SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
2868 };
2869 
2875 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
2876 {
2877  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
2878  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_WIDTH },
2879  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
2880  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_WIDTH },
2881  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
2882  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_WIDTH },
2883  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
2884  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_WIDTH },
2885  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
2886  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_WIDTH },
2887  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
2888  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_WIDTH },
2889  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
2890  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_WIDTH },
2891  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
2892  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_WIDTH },
2893  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
2894  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_WIDTH },
2895  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
2896  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_WIDTH },
2897  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
2898  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_WIDTH },
2899  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
2900  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_WIDTH },
2901  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
2902  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_WIDTH },
2903  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
2904  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_WIDTH },
2905  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
2906  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_WIDTH },
2907  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
2908  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_WIDTH },
2909  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
2910  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_WIDTH },
2911  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
2912  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_WIDTH },
2913  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
2914  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_WIDTH },
2915  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_CHECKER_TYPE,
2916  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_WIDTH },
2917  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_CHECKER_TYPE,
2918  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_WIDTH },
2919  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_CHECKER_TYPE,
2920  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_WIDTH },
2921  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_CHECKER_TYPE,
2922  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_WIDTH },
2923  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_CHECKER_TYPE,
2924  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_WIDTH },
2925  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_CHECKER_TYPE,
2926  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_WIDTH },
2927  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_CHECKER_TYPE,
2928  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_WIDTH },
2929  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_CHECKER_TYPE,
2930  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_WIDTH },
2931  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_CHECKER_TYPE,
2932  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_WIDTH },
2933  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_CHECKER_TYPE,
2934  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_WIDTH },
2935  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_CHECKER_TYPE,
2936  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_WIDTH },
2937  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_CHECKER_TYPE,
2938  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_WIDTH },
2939 };
2940 
2946 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
2947 {
2948  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
2949  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
2950  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
2951  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
2952  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
2953  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
2954  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
2955  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
2956  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
2957  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
2958  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
2959  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
2960  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
2961  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
2962  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
2963  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
2964  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
2965  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
2966  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
2967  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
2968  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
2969  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
2970  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
2971  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
2972  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
2973  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
2974 };
2975 
2981 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
2982 {
2983  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
2984  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
2985  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
2986  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
2987  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
2988  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
2989  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
2990  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
2991  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
2992  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
2993  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
2994  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
2995  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
2996  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
2997  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
2998  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
2999  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
3000  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
3001  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
3002  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
3003  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
3004  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
3005  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
3006  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
3007  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
3008  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
3009 };
3010 
3016 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
3017 {
3018  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
3019  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
3020  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
3021  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
3022  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
3023  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
3024  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
3025  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
3026  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
3027  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
3028  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
3029  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
3030  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
3031  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
3032  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
3033  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
3034  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
3035  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
3036  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
3037  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
3038  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
3039  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
3040  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
3041  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
3042  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
3043  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
3044  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
3045  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
3046  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
3047  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
3048  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
3049  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
3050  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
3051  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
3052  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
3053  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
3054  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
3055  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
3056  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
3057  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
3058  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
3059  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
3060  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
3061  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
3062  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
3063  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
3064  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
3065  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
3066  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
3067  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
3068  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
3069  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
3070  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
3071  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
3072  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
3073  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
3074  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
3075  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
3076  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
3077  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
3078  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
3079  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
3080  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
3081  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
3082  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
3083  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
3084  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
3085  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
3086  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
3087  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
3088  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
3089  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
3090  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
3091  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
3092  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
3093  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
3094  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
3095  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
3096  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
3097  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
3098  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
3099  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
3100  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
3101  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
3102  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
3103  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
3104  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
3105  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
3106  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
3107  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
3108  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
3109  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
3110  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
3111  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
3112  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
3113  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
3114  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
3115  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
3116  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
3117  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
3118  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
3119  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
3120  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
3121  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
3122  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
3123  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
3124  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
3125  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
3126  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
3127  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
3128  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
3129  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
3130  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
3131  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
3132  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
3133  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
3134  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
3135  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
3136  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
3137  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
3138  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
3139  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
3140  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
3141  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
3142  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
3143  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
3144  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
3145  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
3146  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
3147  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
3148  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
3149  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
3150  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
3151  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
3152  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
3153  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
3154  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
3155  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
3156  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
3157  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
3158  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
3159  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
3160  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
3161  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
3162  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
3163  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
3164  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
3165  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
3166  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
3167  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
3168  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
3169  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
3170  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
3171  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
3172  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
3173  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
3174  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
3175  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
3176  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
3177  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
3178  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
3179  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
3180  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
3181  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
3182  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
3183  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
3184  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
3185  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
3186  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
3187  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
3188  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
3189  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
3190  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
3191  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
3192  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
3193  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
3194  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
3195  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
3196  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
3197  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
3198  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
3199  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
3200  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
3201  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
3202  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
3203  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
3204  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
3205  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
3206  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
3207  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
3208  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
3209  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
3210  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
3211  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
3212  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
3213  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
3214  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
3215  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
3216  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
3217  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
3218  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
3219  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
3220  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
3221  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
3222  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
3223  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
3224  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
3225  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
3226  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
3227  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
3228  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
3229  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
3230  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
3231  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
3232  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
3233  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
3234  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
3235  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
3236  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
3237  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
3238  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
3239  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
3240  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
3241  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
3242  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
3243  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
3244  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
3245  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
3246  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
3247  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
3248  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
3249  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
3250  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
3251  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
3252  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
3253  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
3254  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
3255  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
3256  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
3257  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
3258  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
3259  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
3260  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
3261  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
3262  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
3263  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
3264  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
3265  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
3266  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
3267  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
3268  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
3269  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
3270  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
3271  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
3272  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
3273  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
3274  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
3275  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
3276  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
3277  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
3278  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
3279  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
3280  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
3281  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
3282  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
3283  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
3284  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
3285  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
3286  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
3287  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
3288  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
3289  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
3290  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
3291  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
3292  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
3293  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
3294  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
3295  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
3296  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
3297  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
3298  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
3299  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
3300  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
3301  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
3302  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
3303  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
3304  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
3305  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
3306  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
3307  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
3308  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
3309  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
3310  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
3311  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
3312  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
3313  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
3314  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
3315  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
3316  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
3317  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
3318  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
3319  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
3320  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
3321  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
3322  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
3323  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
3324  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
3325  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
3326  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
3327  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
3328  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
3329  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
3330  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
3331  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
3332  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
3333  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
3334  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
3335  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
3336  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
3337  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
3338  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
3339  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
3340  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
3341  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
3342  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
3343  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
3344  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
3345  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
3346  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
3347  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
3348  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
3349  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
3350  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
3351  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
3352  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
3353  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
3354  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
3355  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
3356  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
3357  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
3358  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
3359  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
3360  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
3361  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
3362  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
3363  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
3364  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
3365  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
3366  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
3367  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
3368  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
3369  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
3370  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
3371  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
3372  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
3373  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
3374  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
3375  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
3376  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
3377  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
3378  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
3379  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
3380  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
3381  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
3382  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
3383  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
3384  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
3385  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
3386  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
3387  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
3388  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
3389  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
3390  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
3391  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
3392  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
3393  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
3394  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
3395  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
3396  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
3397  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
3398  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
3399  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
3400  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
3401  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
3402  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
3403  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
3404  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
3405  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
3406  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
3407  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
3408  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
3409  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
3410  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
3411  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
3412  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
3413  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
3414  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
3415  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
3416  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
3417  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
3418  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
3419  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
3420  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
3421  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
3422  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
3423  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
3424  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
3425  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
3426  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
3427  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
3428  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
3429  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
3430  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
3431  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
3432  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
3433  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
3434  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
3435  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
3436  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
3437  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
3438  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
3439  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
3440  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
3441  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
3442  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
3443  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
3444  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
3445  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
3446  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
3447  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
3448  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
3449  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
3450  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
3451  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
3452  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
3453  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
3454  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
3455  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
3456  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
3457  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
3458  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
3459  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
3460  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
3461  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
3462  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
3463  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
3464  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
3465  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
3466  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
3467  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
3468  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
3469  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
3470  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
3471  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
3472  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
3473  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
3474  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
3475  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
3476  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
3477  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
3478  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
3479  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
3480  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
3481  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
3482  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
3483  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
3484  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
3485  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
3486  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
3487  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
3488  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
3489  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
3490  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
3491  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
3492  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
3493  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
3494  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
3495  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
3496  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
3497  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
3498  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
3499  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
3500  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
3501  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
3502  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
3503  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
3504  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
3505  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
3506  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
3507  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
3508  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
3509  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
3510  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
3511  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
3512  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
3513  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
3514  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
3515  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
3516  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
3517  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
3518  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
3519  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
3520  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
3521  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
3522  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
3523  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
3524  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
3525  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
3526  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
3527  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
3528  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
3529  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
3530 };
3531 
3537 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
3538 {
3539  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
3540  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
3541  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
3542  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
3543  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
3544  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
3545  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
3546  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
3547  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
3548  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
3549  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
3550  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
3551  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
3552  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
3553  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
3554  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
3555  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
3556  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
3557  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
3558  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
3559  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
3560  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
3561  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
3562  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
3563  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
3564  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
3565  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
3566  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
3567  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
3568  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
3569  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
3570  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
3571  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
3572  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
3573  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
3574  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
3575  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
3576  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
3577  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
3578  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
3579  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
3580  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
3581  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
3582  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
3583  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
3584  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
3585  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
3586  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
3587  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
3588  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
3589  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
3590  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
3591  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
3592  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
3593  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
3594  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
3595  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
3596  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
3597  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
3598  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
3599  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
3600  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
3601  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
3602  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
3603  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
3604  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
3605  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
3606  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
3607  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
3608  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
3609  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
3610  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
3611  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
3612  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
3613  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
3614  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
3615  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
3616  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
3617  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
3618  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
3619  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
3620  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
3621  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
3622  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
3623  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
3624  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
3625  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
3626  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
3627  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
3628  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
3629  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
3630  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
3631  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
3632  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
3633  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
3634  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
3635  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
3636  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
3637  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
3638  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
3639  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
3640  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
3641  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
3642  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
3643  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
3644  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
3645  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
3646  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
3647  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
3648  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
3649  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
3650  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
3651  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
3652  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
3653  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
3654  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
3655  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
3656  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
3657  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
3658  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
3659  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
3660  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
3661  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
3662  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
3663  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
3664  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
3665  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
3666  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
3667  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
3668  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
3669  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
3670  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
3671  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
3672  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
3673  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
3674  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
3675  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
3676  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
3677  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
3678  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
3679  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
3680  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
3681  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
3682  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
3683  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
3684  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
3685  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
3686  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
3687  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
3688  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
3689  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
3690  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
3691  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
3692  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
3693  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
3694  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
3695  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
3696  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
3697  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
3698  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
3699  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
3700  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
3701  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
3702  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
3703  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
3704  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
3705  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
3706  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
3707  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
3708  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
3709  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
3710  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
3711  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
3712  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
3713  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
3714  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
3715  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
3716  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
3717  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
3718  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
3719  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
3720  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
3721  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
3722  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
3723  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
3724  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
3725  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
3726  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
3727  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
3728  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
3729  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
3730  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
3731  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
3732  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
3733  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
3734  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
3735  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
3736  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
3737  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
3738  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
3739  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
3740  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
3741  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
3742  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
3743  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
3744  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
3745  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
3746  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
3747  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
3748  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
3749  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
3750  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
3751  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
3752  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
3753  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
3754  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
3755  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
3756  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
3757  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
3758  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
3759  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
3760  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
3761  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
3762  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
3763  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
3764  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
3765  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
3766  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
3767  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
3768  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
3769  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
3770  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
3771  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
3772  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
3773  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
3774  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
3775  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
3776  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
3777  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
3778  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
3779  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
3780  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
3781  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
3782  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
3783  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
3784  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
3785  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
3786  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
3787  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
3788  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
3789  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
3790  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
3791  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
3792  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
3793  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
3794  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
3795  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
3796  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
3797  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
3798  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
3799  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
3800  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
3801  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
3802  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
3803  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
3804  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
3805  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
3806  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
3807  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
3808  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
3809  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
3810  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
3811  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
3812  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
3813  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
3814  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
3815  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
3816  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
3817  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
3818  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
3819  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
3820  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
3821  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
3822  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
3823  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
3824  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
3825  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
3826  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
3827  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
3828  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
3829  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
3830  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
3831  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
3832  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
3833  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
3834  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
3835  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
3836  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
3837  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
3838  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
3839  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
3840  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
3841  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
3842  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
3843  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
3844  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
3845  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
3846  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
3847 };
3848 
3854 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
3855 {
3856  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
3857  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
3858  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
3859  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
3860  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
3861  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
3862  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
3863  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
3864  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
3865  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
3866 };
3867 
3873 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
3874 {
3875  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
3876  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
3877  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
3878  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
3879  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
3880  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
3881  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
3882  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
3883  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
3884  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
3885  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
3886  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
3887  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
3888  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
3889  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
3890  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
3891  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
3892  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
3893  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
3894  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
3895  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
3896  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
3897  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
3898  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
3899  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
3900  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
3901  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
3902  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
3903  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
3904  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
3905  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
3906  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
3907  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
3908  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
3909  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
3910  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
3911  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
3912  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
3913 };
3914 
3920 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
3921 {
3922  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
3923  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
3924  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
3925  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
3926  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
3927  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
3928  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
3929  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
3930  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
3931  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
3932  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
3933  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
3934  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
3935  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
3936  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
3937  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
3938  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
3939  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
3940  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
3941  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
3942  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
3943  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
3944  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
3945  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
3946  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
3947  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
3948  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
3949  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
3950  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
3951  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
3952  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
3953  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
3954  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
3955  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
3956  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
3957  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
3958  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
3959  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
3960  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
3961  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
3962  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
3963  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
3964  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
3965  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
3966  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
3967  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
3968  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
3969  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
3970  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
3971  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
3972  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
3973  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
3974  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
3975  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
3976  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
3977  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
3978  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
3979  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
3980  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
3981  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
3982  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
3983  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
3984  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
3985  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
3986  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
3987  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
3988  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
3989  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
3990  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
3991  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
3992  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
3993  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
3994  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
3995  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
3996  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
3997  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
3998  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
3999  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
4000  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
4001  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
4002  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
4003  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
4004  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
4005  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
4006 };
4007 
4013 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
4014 {
4015  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
4016  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
4017  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
4018  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
4019  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
4020  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
4021  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
4022  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
4023  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
4024  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
4025  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
4026  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
4027  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
4028  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
4029  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
4030  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
4031  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
4032  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
4033  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
4034  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
4035  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
4036  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
4037  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
4038  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
4039  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
4040  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
4041  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
4042  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
4043  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
4044  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
4045  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
4046  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
4047  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
4048  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
4049  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
4050  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
4051  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
4052  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
4053  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
4054  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
4055  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
4056  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
4057  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
4058  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
4059  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
4060  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
4061  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
4062  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
4063  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
4064  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
4065  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
4066  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
4067  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
4068  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
4069  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
4070  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
4071  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
4072  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
4073  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
4074  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
4075  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
4076  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
4077  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
4078  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
4079  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
4080  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
4081  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
4082  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
4083  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
4084  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
4085  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
4086  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
4087  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
4088  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
4089  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
4090  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
4091  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
4092  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
4093  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
4094  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
4095  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
4096  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
4097  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
4098  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
4099  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
4100  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
4101  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
4102  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
4103  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
4104  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
4105  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
4106  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
4107  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
4108  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
4109  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
4110  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
4111  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
4112  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
4113  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
4114  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
4115  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
4116  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
4117  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
4118  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
4119  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
4120  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
4121  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
4122  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
4123  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
4124  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
4125  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
4126  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
4127  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
4128  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
4129  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
4130  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
4131  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
4132  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
4133  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
4134  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
4135  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
4136  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
4137  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
4138  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
4139  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
4140  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
4141  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
4142  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
4143  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
4144  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
4145  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
4146  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
4147  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
4148  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
4149  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
4150  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
4151  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
4152  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
4153  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
4154  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
4155  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
4156  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
4157  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
4158  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
4159  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
4160  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
4161  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
4162  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
4163  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
4164  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
4165  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
4166  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
4167  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
4168  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
4169  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
4170  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
4171  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
4172  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
4173  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
4174  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
4175  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
4176  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
4177  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
4178  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
4179  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
4180  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
4181  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
4182  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
4183  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
4184  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
4185  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
4186  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
4187  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
4188  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
4189  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
4190  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
4191  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
4192  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
4193  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
4194  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
4195  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
4196  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
4197  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
4198  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
4199  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
4200  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
4201  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
4202  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
4203  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
4204  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
4205  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
4206  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
4207  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
4208  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
4209  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
4210  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
4211  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
4212  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
4213  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
4214  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
4215  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_CHECKER_TYPE,
4216  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
4217  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_CHECKER_TYPE,
4218  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
4219  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_CHECKER_TYPE,
4220  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
4221  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_CHECKER_TYPE,
4222  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
4223  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_CHECKER_TYPE,
4224  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
4225  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_CHECKER_TYPE,
4226  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
4227  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_CHECKER_TYPE,
4228  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
4229  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_CHECKER_TYPE,
4230  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
4231  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_CHECKER_TYPE,
4232  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
4233  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_CHECKER_TYPE,
4234  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
4235  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_CHECKER_TYPE,
4236  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
4237  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_CHECKER_TYPE,
4238  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
4239  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_CHECKER_TYPE,
4240  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
4241  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_CHECKER_TYPE,
4242  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
4243  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_CHECKER_TYPE,
4244  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
4245  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_CHECKER_TYPE,
4246  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
4247  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_CHECKER_TYPE,
4248  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
4249  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_CHECKER_TYPE,
4250  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
4251  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_CHECKER_TYPE,
4252  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
4253  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_CHECKER_TYPE,
4254  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
4255  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_CHECKER_TYPE,
4256  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
4257 };
4258 
4264 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
4265 {
4266  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
4267  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
4268  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
4269  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
4270  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
4271  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
4272  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
4273  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
4274  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
4275  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
4276  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
4277  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
4278 };
4279 
4285 {
4286  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID, 0u,
4287  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_RAM_SIZE, 4u,
4288  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_ROW_WIDTH, ((bool)false) },
4289  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID, 0u,
4290  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_RAM_SIZE, 4u,
4291  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_ROW_WIDTH, ((bool)false) },
4292  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID, 0u,
4293  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_RAM_SIZE, 4u,
4294  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_ROW_WIDTH, ((bool)false) },
4295  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID, 0u,
4296  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_RAM_SIZE, 4u,
4297  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_ROW_WIDTH, ((bool)false) },
4298  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_STATE_BUFFER0_RAM_ID, 0u,
4299  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_STATE_BUFFER0_RAM_SIZE, 4u,
4300  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_STATE_BUFFER0_ROW_WIDTH, ((bool)false) },
4301  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RING_MEMORY_RAM_ID, 0u,
4302  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RING_MEMORY_RAM_SIZE, 4u,
4303  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RING_MEMORY_ROW_WIDTH, ((bool)false) },
4304 };
4305 
4311 {
4312  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_ID, 0u,
4313  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_SIZE, 4u,
4314  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_ROW_WIDTH, ((bool)false) },
4315 };
4316 
4322 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
4323 {
4324  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
4325  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
4326  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
4327  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
4328  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
4329  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
4330  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
4331  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
4332  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
4333  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
4334  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
4335  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
4336  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
4337  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
4338  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
4339  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
4340  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
4341  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
4342  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
4343  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
4344  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
4345  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
4346  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
4347  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
4348  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
4349  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
4350 };
4351 
4357 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
4358 {
4359  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
4360  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
4361  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
4362  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
4363  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
4364  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
4365  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
4366  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
4367  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
4368  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
4369  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
4370  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
4371  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
4372  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
4373  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
4374  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
4375  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
4376  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
4377  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
4378  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
4379  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
4380  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
4381  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
4382  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
4383  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
4384  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
4385 };
4386 
4392 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS] =
4393 {
4394  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_CHECKER_TYPE,
4395  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_WIDTH },
4396  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_CHECKER_TYPE,
4397  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_WIDTH },
4398  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_CHECKER_TYPE,
4399  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_WIDTH },
4400  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_CHECKER_TYPE,
4401  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_WIDTH },
4402  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_CHECKER_TYPE,
4403  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_WIDTH },
4404  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_CHECKER_TYPE,
4405  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_WIDTH },
4406  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_CHECKER_TYPE,
4407  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_WIDTH },
4408  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_CHECKER_TYPE,
4409  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_WIDTH },
4410  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_CHECKER_TYPE,
4411  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_WIDTH },
4412  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_CHECKER_TYPE,
4413  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_WIDTH },
4414  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_CHECKER_TYPE,
4415  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_WIDTH },
4416  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_CHECKER_TYPE,
4417  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_WIDTH },
4418  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_CHECKER_TYPE,
4419  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_WIDTH },
4420  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_CHECKER_TYPE,
4421  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_WIDTH },
4422  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_CHECKER_TYPE,
4423  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_WIDTH },
4424  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_CHECKER_TYPE,
4425  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_WIDTH },
4426  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_CHECKER_TYPE,
4427  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_WIDTH },
4428  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_CHECKER_TYPE,
4429  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_WIDTH },
4430  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_CHECKER_TYPE,
4431  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_WIDTH },
4432  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_CHECKER_TYPE,
4433  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_WIDTH },
4434  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_CHECKER_TYPE,
4435  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_WIDTH },
4436  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_CHECKER_TYPE,
4437  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_WIDTH },
4438  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_CHECKER_TYPE,
4439  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_WIDTH },
4440  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_CHECKER_TYPE,
4441  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_WIDTH },
4442  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_CHECKER_TYPE,
4443  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_WIDTH },
4444  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_CHECKER_TYPE,
4445  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_WIDTH },
4446  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_CHECKER_TYPE,
4447  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_WIDTH },
4448  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_CHECKER_TYPE,
4449  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_WIDTH },
4450  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_CHECKER_TYPE,
4451  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_WIDTH },
4452  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_CHECKER_TYPE,
4453  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_WIDTH },
4454  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_CHECKER_TYPE,
4455  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_WIDTH },
4456  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_CHECKER_TYPE,
4457  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_WIDTH },
4458  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_CHECKER_TYPE,
4459  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_WIDTH },
4460  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_CHECKER_TYPE,
4461  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_WIDTH },
4462  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_CHECKER_TYPE,
4463  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_WIDTH },
4464  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_CHECKER_TYPE,
4465  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_WIDTH },
4466  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_CHECKER_TYPE,
4467  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_WIDTH },
4468  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_CHECKER_TYPE,
4469  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_WIDTH },
4470  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_CHECKER_TYPE,
4471  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_WIDTH },
4472  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_CHECKER_TYPE,
4473  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_WIDTH },
4474  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_CHECKER_TYPE,
4475  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_WIDTH },
4476  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_CHECKER_TYPE,
4477  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_WIDTH },
4478  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_CHECKER_TYPE,
4479  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_WIDTH },
4480  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_CHECKER_TYPE,
4481  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_WIDTH },
4482  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_CHECKER_TYPE,
4483  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_WIDTH },
4484  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_CHECKER_TYPE,
4485  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_WIDTH },
4486  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_CHECKER_TYPE,
4487  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_WIDTH },
4488  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_CHECKER_TYPE,
4489  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_WIDTH },
4490  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_CHECKER_TYPE,
4491  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_WIDTH },
4492  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_CHECKER_TYPE,
4493  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_WIDTH },
4494  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_CHECKER_TYPE,
4495  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_WIDTH },
4496  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_CHECKER_TYPE,
4497  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_WIDTH },
4498  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_CHECKER_TYPE,
4499  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_WIDTH },
4500  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_CHECKER_TYPE,
4501  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_WIDTH },
4502  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_CHECKER_TYPE,
4503  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_WIDTH },
4504  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_CHECKER_TYPE,
4505  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_WIDTH },
4506  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_CHECKER_TYPE,
4507  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_WIDTH },
4508  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_CHECKER_TYPE,
4509  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_WIDTH },
4510  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_CHECKER_TYPE,
4511  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_WIDTH },
4512  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_CHECKER_TYPE,
4513  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_WIDTH },
4514  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_CHECKER_TYPE,
4515  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_WIDTH },
4516  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_CHECKER_TYPE,
4517  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_WIDTH },
4518 };
4519 
4525 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] =
4526 {
4527  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
4528  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
4529  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
4530  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
4531  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
4532  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
4533  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
4534  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
4535  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
4536  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
4537  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
4538  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
4539  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
4540  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
4541  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
4542  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
4543  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
4544  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
4545  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
4546  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
4547  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
4548  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
4549  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
4550  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
4551  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_CHECKER_TYPE,
4552  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_WIDTH },
4553  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_CHECKER_TYPE,
4554  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_WIDTH },
4555  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_CHECKER_TYPE,
4556  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_WIDTH },
4557  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_CHECKER_TYPE,
4558  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_WIDTH },
4559  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_CHECKER_TYPE,
4560  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_WIDTH },
4561  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_CHECKER_TYPE,
4562  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_WIDTH },
4563  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_CHECKER_TYPE,
4564  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_WIDTH },
4565  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_CHECKER_TYPE,
4566  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_WIDTH },
4567  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_CHECKER_TYPE,
4568  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_WIDTH },
4569  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_CHECKER_TYPE,
4570  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_WIDTH },
4571  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_CHECKER_TYPE,
4572  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_WIDTH },
4573  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_CHECKER_TYPE,
4574  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_WIDTH },
4575  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_CHECKER_TYPE,
4576  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_WIDTH },
4577  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_CHECKER_TYPE,
4578  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_WIDTH },
4579 };
4580 
4586 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
4587 {
4588  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
4589  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
4590  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
4591  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
4592  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
4593  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
4594  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
4595  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
4596  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
4597  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
4598  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
4599  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
4600  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
4601  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
4602  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
4603  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
4604  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
4605  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
4606  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
4607  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
4608  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
4609  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
4610  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
4611  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
4612  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
4613  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
4614  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
4615  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
4616  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
4617  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
4618 };
4619 
4625 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
4626 {
4627  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
4628  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
4629  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
4630  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
4631  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
4632  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
4633  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
4634  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
4635 };
4636 
4642 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] =
4643 {
4644  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
4645  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
4646  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
4647  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
4648  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
4649  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
4650  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
4651  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
4652  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
4653  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
4654  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
4655  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
4656  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
4657  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
4658  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
4659  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
4660  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
4661  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
4662  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
4663  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
4664  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
4665  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
4666  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
4667  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
4668 };
4669 
4675 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS] =
4676 {
4677  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
4678  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_0_WIDTH },
4679  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
4680  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_1_WIDTH },
4681  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
4682  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_2_WIDTH },
4683  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
4684  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_3_WIDTH },
4685  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
4686  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_4_WIDTH },
4687  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
4688  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_5_WIDTH },
4689  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
4690  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_6_WIDTH },
4691  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
4692  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_7_WIDTH },
4693  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
4694  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_8_WIDTH },
4695  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
4696  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_9_WIDTH },
4697  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
4698  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_10_WIDTH },
4699  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
4700  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_11_WIDTH },
4701  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
4702  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_12_WIDTH },
4703  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
4704  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_13_WIDTH },
4705  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
4706  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_14_WIDTH },
4707 };
4708 
4714 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS] =
4715 {
4716  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_0_CHECKER_TYPE,
4717  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_0_WIDTH },
4718  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_1_CHECKER_TYPE,
4719  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_1_WIDTH },
4720  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_2_CHECKER_TYPE,
4721  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_2_WIDTH },
4722  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_3_CHECKER_TYPE,
4723  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_3_WIDTH },
4724 };
4725 
4731 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS] =
4732 {
4733  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
4734  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_0_WIDTH },
4735  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
4736  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_1_WIDTH },
4737  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
4738  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_2_WIDTH },
4739  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
4740  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_3_WIDTH },
4741  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
4742  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_4_WIDTH },
4743  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
4744  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_5_WIDTH },
4745  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
4746  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_6_WIDTH },
4747  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
4748  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_7_WIDTH },
4749  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
4750  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_8_WIDTH },
4751  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
4752  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_9_WIDTH },
4753  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
4754  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_10_WIDTH },
4755  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
4756  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_11_WIDTH },
4757  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
4758  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_12_WIDTH },
4759  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
4760  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_13_WIDTH },
4761  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
4762  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_14_WIDTH },
4763 };
4764 
4770 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS] =
4771 {
4772  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_0_CHECKER_TYPE,
4773  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_0_WIDTH },
4774  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_1_CHECKER_TYPE,
4775  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_1_WIDTH },
4776  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_2_CHECKER_TYPE,
4777  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_2_WIDTH },
4778  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_3_CHECKER_TYPE,
4779  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_3_WIDTH },
4780 };
4781 
4787 {
4788  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x79140000u,
4789  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
4790  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
4791 };
4792 
4798 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
4799 {
4800  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4801  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
4802  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4803  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
4804  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4805  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
4806  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
4807  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
4808  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
4809  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
4810  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
4811  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
4812  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
4813  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
4814  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
4815  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
4816  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
4817  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
4818  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
4819  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
4820  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
4821  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
4822  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
4823  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
4824  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
4825  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
4826  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
4827  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
4828  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
4829  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
4830  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
4831  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
4832  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
4833  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
4834  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
4835  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
4836  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
4837  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
4838  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
4839  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
4840  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
4841  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
4842  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
4843  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
4844  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
4845  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
4846  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
4847  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
4848  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
4849  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_WIDTH },
4850  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
4851  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_WIDTH },
4852  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
4853  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_WIDTH },
4854  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
4855  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_WIDTH },
4856  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
4857  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_WIDTH },
4858  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
4859  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_WIDTH },
4860  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
4861  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_WIDTH },
4862  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
4863  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_WIDTH },
4864  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
4865  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_WIDTH },
4866  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
4867  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_WIDTH },
4868  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
4869  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_WIDTH },
4870  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
4871  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_WIDTH },
4872  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
4873  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_WIDTH },
4874  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
4875  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_WIDTH },
4876  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
4877  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_WIDTH },
4878  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
4879  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_WIDTH },
4880  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
4881  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_WIDTH },
4882  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
4883  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_WIDTH },
4884  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
4885  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_WIDTH },
4886  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
4887  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_WIDTH },
4888  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
4889  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_WIDTH },
4890  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
4891  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_WIDTH },
4892  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
4893  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_WIDTH },
4894  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
4895  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_WIDTH },
4896  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
4897  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_WIDTH },
4898  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
4899  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_WIDTH },
4900  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
4901  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_WIDTH },
4902  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
4903  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_WIDTH },
4904  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
4905  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_WIDTH },
4906  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
4907  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_WIDTH },
4908  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
4909  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_WIDTH },
4910  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
4911  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_WIDTH },
4912  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
4913  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_WIDTH },
4914  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
4915  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_WIDTH },
4916  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
4917  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_WIDTH },
4918  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
4919  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_WIDTH },
4920  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
4921  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_WIDTH },
4922  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
4923  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_WIDTH },
4924  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
4925  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_WIDTH },
4926  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
4927  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_WIDTH },
4928  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
4929  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_WIDTH },
4930 };
4931 
4937 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
4938 {
4939  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
4940  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
4941  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
4942  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
4943  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
4944  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
4945  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
4946  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
4947  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
4948  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
4949  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
4950  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
4951 };
4952 
4958 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
4959 {
4960  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
4961  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
4962  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
4963  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
4964  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
4965  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
4966  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
4967  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
4968  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
4969  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
4970  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
4971  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
4972 };
4973 
4979 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
4980 {
4981  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4982  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_WIDTH },
4983  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4984  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_WIDTH },
4985  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4986  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_WIDTH },
4987  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
4988  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_WIDTH },
4989  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
4990  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_WIDTH },
4991  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
4992  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_WIDTH },
4993  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
4994  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_WIDTH },
4995  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
4996  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_WIDTH },
4997  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
4998  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_WIDTH },
4999  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5000  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_WIDTH },
5001  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5002  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_WIDTH },
5003  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5004  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_WIDTH },
5005  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5006  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_WIDTH },
5007  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5008  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_WIDTH },
5009  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5010  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_WIDTH },
5011  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5012  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_WIDTH },
5013  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5014  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_WIDTH },
5015  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5016  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_WIDTH },
5017  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5018  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_WIDTH },
5019  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5020  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_WIDTH },
5021  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5022  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_WIDTH },
5023  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5024  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_WIDTH },
5025  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5026  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_WIDTH },
5027  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5028  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_WIDTH },
5029  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5030  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_WIDTH },
5031  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5032  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_WIDTH },
5033  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5034  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_WIDTH },
5035  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5036  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_WIDTH },
5037  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5038  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_WIDTH },
5039  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5040  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_WIDTH },
5041  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5042  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_WIDTH },
5043  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5044  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_WIDTH },
5045  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5046  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_WIDTH },
5047  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5048  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_WIDTH },
5049  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5050  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_WIDTH },
5051  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
5052  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_WIDTH },
5053  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
5054  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_WIDTH },
5055  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
5056  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_WIDTH },
5057  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
5058  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_WIDTH },
5059  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
5060  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_WIDTH },
5061  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
5062  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_WIDTH },
5063  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
5064  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_WIDTH },
5065  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
5066  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_WIDTH },
5067  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
5068  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_WIDTH },
5069  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
5070  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_WIDTH },
5071  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
5072  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_WIDTH },
5073  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
5074  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_WIDTH },
5075  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
5076  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_WIDTH },
5077  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
5078  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_WIDTH },
5079  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
5080  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_WIDTH },
5081  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
5082  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_WIDTH },
5083  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
5084  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_WIDTH },
5085  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
5086  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_WIDTH },
5087  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
5088  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_WIDTH },
5089  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
5090  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_WIDTH },
5091  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
5092  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_WIDTH },
5093  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
5094  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_WIDTH },
5095  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
5096  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_WIDTH },
5097  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
5098  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_WIDTH },
5099  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
5100  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_WIDTH },
5101  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
5102  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_WIDTH },
5103  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
5104  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_WIDTH },
5105  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
5106  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_WIDTH },
5107  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
5108  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_WIDTH },
5109  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
5110  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_WIDTH },
5111  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
5112  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_WIDTH },
5113  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
5114  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_WIDTH },
5115  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
5116  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_WIDTH },
5117  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
5118  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_WIDTH },
5119  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
5120  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_WIDTH },
5121  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
5122  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_WIDTH },
5123  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
5124  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_WIDTH },
5125  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
5126  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_WIDTH },
5127  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
5128  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_WIDTH },
5129  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
5130  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_WIDTH },
5131  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
5132  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_WIDTH },
5133  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
5134  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_WIDTH },
5135  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
5136  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_WIDTH },
5137  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
5138  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_WIDTH },
5139  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
5140  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_WIDTH },
5141  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
5142  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_WIDTH },
5143  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
5144  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_WIDTH },
5145  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
5146  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_WIDTH },
5147  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
5148  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_WIDTH },
5149  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
5150  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_WIDTH },
5151  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
5152  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_WIDTH },
5153  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
5154  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_WIDTH },
5155  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
5156  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_WIDTH },
5157  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
5158  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_WIDTH },
5159  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
5160  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_WIDTH },
5161  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
5162  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_WIDTH },
5163  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
5164  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_WIDTH },
5165  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
5166  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_WIDTH },
5167  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
5168  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_WIDTH },
5169  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
5170  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_WIDTH },
5171  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
5172  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_WIDTH },
5173  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
5174  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_WIDTH },
5175  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
5176  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_WIDTH },
5177  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
5178  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_WIDTH },
5179  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
5180  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_WIDTH },
5181  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
5182  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_WIDTH },
5183  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
5184  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_WIDTH },
5185  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
5186  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_WIDTH },
5187  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
5188  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_WIDTH },
5189  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
5190  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_WIDTH },
5191  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
5192  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_WIDTH },
5193  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
5194  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_WIDTH },
5195  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
5196  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_WIDTH },
5197  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
5198  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_WIDTH },
5199  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
5200  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_WIDTH },
5201  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
5202  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_WIDTH },
5203  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
5204  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_WIDTH },
5205  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
5206  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_WIDTH },
5207  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
5208  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_WIDTH },
5209  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
5210  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_WIDTH },
5211  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
5212  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_WIDTH },
5213  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
5214  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_WIDTH },
5215  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
5216  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_WIDTH },
5217  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
5218  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_WIDTH },
5219  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
5220  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_WIDTH },
5221  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
5222  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_WIDTH },
5223  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
5224  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_WIDTH },
5225  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
5226  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_WIDTH },
5227  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
5228  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_WIDTH },
5229  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
5230  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_WIDTH },
5231  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
5232  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_WIDTH },
5233  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
5234  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_WIDTH },
5235  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
5236  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_WIDTH },
5237  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
5238  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_WIDTH },
5239  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
5240  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_WIDTH },
5241  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
5242  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_WIDTH },
5243  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
5244  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_WIDTH },
5245  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
5246  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_WIDTH },
5247  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
5248  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_WIDTH },
5249  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
5250  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_WIDTH },
5251  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
5252  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_WIDTH },
5253  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
5254  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_WIDTH },
5255  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
5256  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_WIDTH },
5257  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
5258  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_WIDTH },
5259  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
5260  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_WIDTH },
5261  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
5262  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_WIDTH },
5263  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
5264  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_WIDTH },
5265  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
5266  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_WIDTH },
5267  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
5268  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_WIDTH },
5269  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
5270  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_WIDTH },
5271  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
5272  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_WIDTH },
5273  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
5274  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_WIDTH },
5275  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
5276  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_WIDTH },
5277  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
5278  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_WIDTH },
5279  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
5280  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_WIDTH },
5281  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
5282  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_WIDTH },
5283  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
5284  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_WIDTH },
5285  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
5286  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_WIDTH },
5287  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
5288  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_WIDTH },
5289  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
5290  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_WIDTH },
5291  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
5292  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_WIDTH },
5293  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
5294  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_WIDTH },
5295  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
5296  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_WIDTH },
5297  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
5298  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_WIDTH },
5299  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
5300  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_WIDTH },
5301  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
5302  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_WIDTH },
5303  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
5304  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_WIDTH },
5305  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
5306  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_WIDTH },
5307  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
5308  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_WIDTH },
5309  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
5310  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_WIDTH },
5311  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
5312  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_WIDTH },
5313  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
5314  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_WIDTH },
5315  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
5316  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_WIDTH },
5317  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
5318  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_WIDTH },
5319  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
5320  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_WIDTH },
5321  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
5322  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_WIDTH },
5323 };
5324 
5330 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5331 {
5332  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5333  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
5334  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5335  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
5336  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5337  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
5338 };
5339 
5345 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5346 {
5347  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5348  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
5349  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5350  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
5351  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5352  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
5353  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5354  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
5355  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5356  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
5357  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5358  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
5359  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5360  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
5361  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5362  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
5363  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5364  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
5365  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5366  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
5367  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5368  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
5369  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5370  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
5371  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5372  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
5373  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5374  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
5375  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5376  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
5377  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5378  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
5379  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5380  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
5381  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5382  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
5383  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5384  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
5385  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5386  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
5387  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5388  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
5389  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5390  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
5391  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5392  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
5393  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5394  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
5395  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5396  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
5397  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5398  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
5399  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5400  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
5401  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5402  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
5403  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5404  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
5405  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5406  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
5407  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5408  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
5409  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5410  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
5411  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5412  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
5413  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5414  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
5415  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5416  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
5417  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
5418  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
5419  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
5420  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
5421  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
5422  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
5423  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
5424  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
5425  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
5426  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
5427  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
5428  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
5429  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
5430  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
5431  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
5432  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
5433  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
5434  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
5435  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
5436  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
5437  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
5438  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
5439  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
5440  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
5441  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
5442  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
5443  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
5444  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
5445  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
5446  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
5447 };
5448 
5454 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
5455 {
5456  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
5457  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
5458  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
5459  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
5460  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
5461  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
5462  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
5463  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
5464  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
5465  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
5466  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
5467  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
5468  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
5469  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
5470 };
5471 
5477 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
5478 {
5479  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
5480  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
5481  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
5482  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
5483  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
5484  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
5485  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
5486  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
5487  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
5488  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
5489  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
5490  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
5491  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
5492  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
5493  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
5494  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
5495  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
5496  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
5497  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
5498  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
5499  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
5500  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
5501  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
5502  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
5503  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
5504  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
5505  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
5506  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
5507  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
5508  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
5509  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
5510  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
5511  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
5512  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
5513  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
5514  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
5515  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
5516  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
5517  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
5518  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
5519  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
5520  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
5521  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
5522  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
5523  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
5524  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
5525  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
5526  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
5527  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
5528  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
5529  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
5530  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
5531  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
5532  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
5533  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
5534  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
5535  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
5536  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
5537  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
5538  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
5539  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
5540  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
5541  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
5542  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
5543  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
5544  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
5545  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
5546  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
5547  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
5548  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
5549  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
5550  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
5551  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
5552  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
5553  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
5554  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
5555  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
5556  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
5557  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
5558  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
5559  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
5560  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
5561  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
5562  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
5563  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
5564  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
5565  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
5566  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
5567  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
5568  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
5569  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
5570  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
5571  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
5572  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
5573  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
5574  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
5575  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
5576  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
5577  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
5578  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
5579  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
5580  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
5581  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
5582  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
5583  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
5584  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
5585  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
5586  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
5587  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
5588  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
5589  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
5590  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
5591  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
5592  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
5593  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
5594  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
5595  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
5596  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
5597  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
5598  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
5599  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
5600  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
5601  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
5602  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
5603  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
5604  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
5605  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
5606  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
5607  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
5608  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
5609  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
5610  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
5611  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
5612  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
5613  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
5614  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
5615  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
5616  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
5617  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
5618  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
5619 };
5620 
5626 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
5627 {
5628  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
5629  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
5630  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
5631  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
5632  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
5633  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
5634  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
5635  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
5636  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
5637  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
5638  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
5639  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
5640  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
5641  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
5642  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
5643  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
5644  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
5645  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
5646  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
5647  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
5648  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
5649  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
5650  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
5651  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
5652  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
5653  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
5654  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
5655  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
5656  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
5657  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
5658  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
5659  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
5660  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
5661  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
5662  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
5663  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
5664  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
5665  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
5666  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
5667  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
5668  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
5669  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
5670  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
5671  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
5672  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
5673  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
5674  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
5675  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
5676  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
5677  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
5678  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
5679  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
5680  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
5681  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
5682  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
5683  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
5684  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
5685  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
5686  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
5687  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
5688  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
5689  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
5690  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
5691  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
5692  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
5693  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
5694  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
5695  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
5696  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
5697  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
5698  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
5699  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
5700  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
5701  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
5702  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
5703  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
5704  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
5705  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
5706  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
5707  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
5708  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
5709  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
5710  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
5711  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
5712  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
5713  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
5714  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
5715  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
5716  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
5717  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
5718  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
5719  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
5720  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
5721  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
5722  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
5723  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
5724  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
5725  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
5726  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
5727  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
5728  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
5729  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
5730  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
5731  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
5732  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
5733  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
5734  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
5735  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
5736  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
5737  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
5738  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
5739  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
5740  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
5741  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
5742  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
5743  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
5744  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
5745  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
5746  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
5747  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
5748  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
5749  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
5750  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
5751  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
5752  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
5753  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
5754  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
5755  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
5756  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
5757  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
5758  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
5759  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
5760  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
5761  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
5762  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
5763  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
5764  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
5765  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
5766 };
5767 
5773 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
5774 {
5775  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
5776  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
5777  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
5778  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
5779  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
5780  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
5781  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
5782  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
5783  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
5784  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
5785  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
5786  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
5787  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
5788  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
5789  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
5790  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
5791  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
5792  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
5793  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
5794  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
5795  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
5796  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
5797  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
5798  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
5799  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
5800  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
5801  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
5802  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
5803  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
5804  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
5805  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
5806  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
5807  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
5808  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
5809 };
5810 
5816 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
5817 {
5818  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
5819  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
5820  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
5821  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
5822  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
5823  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
5824  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
5825  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
5826  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
5827  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
5828  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
5829  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
5830  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
5831  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
5832 };
5833 
5839 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
5840 {
5841  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
5842  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
5843  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
5844  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
5845  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
5846  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
5847  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
5848  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
5849  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
5850  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
5851  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
5852  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
5853  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
5854  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
5855  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
5856  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
5857  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
5858  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
5859  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
5860  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
5861  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
5862  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
5863 };
5864 
5870 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
5871 {
5872  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
5873  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
5874  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
5875  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
5876  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
5877  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
5878  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
5879  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
5880  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
5881  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
5882  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
5883  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
5884 };
5885 
5891 {
5892  { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
5893  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
5894  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
5895 };
5896 
5902 /* NOTE: For VIM RAM Id, with a 32 bit vector, the 2 LSB bits are not used.
5903 ECC is done only on 30 bits. But need to add a correction of 2 to get the address
5904 calculation to be right */
5905 #define SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION (2U)
5907 {
5908  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
5909  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
5910  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
5911  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
5912  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
5913  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
5914  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
5915  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
5916  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
5917  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
5918  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
5919  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
5920  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
5921  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
5922  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
5923  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
5924  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
5925  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
5926  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
5927  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
5928  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
5929  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
5930  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
5931  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
5932  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
5933  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
5934  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
5935  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
5936  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
5937  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
5938  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
5939  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
5940  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
5941  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
5942  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
5943  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
5944  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
5945  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
5946  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
5947  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
5948  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
5949  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
5950  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
5951  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
5952  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
5953  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
5954  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
5955  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
5956  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
5957  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
5958  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
5959  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
5960  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
5961  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
5962  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
5963  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
5964  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
5965  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
5966  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
5967  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
5968  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
5969  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
5970  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
5971  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_ID, 0u,
5972  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_SIZE, 4u,
5973  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
5974  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_ID, 0x0u, //2
5975  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_SIZE, 4u,
5976  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
5977  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_ID, 0x41010000u, //3
5978  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_SIZE, 4u,
5979  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
5980  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_ID, 0x41010000u, //4
5981  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_SIZE, 4u,
5982  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
5983  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_ID, 0x41010000u, //5
5984  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_SIZE, 4u,
5985  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
5986  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_ID, 0x41010000u, //6
5987  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_SIZE, 4u,
5988  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
5989  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x07FF2000u, //27 /* NOTE: VIM width and size needs correction: see note above */
5990  ((SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE
5991  *(SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH
5993  /SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH), 4u,
5994  (SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH), ((bool)true) },
5995  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
5996  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 4u,
5997  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)false) },
5998 };
5999 
6005 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS] =
6006 {
6007  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_0_CHECKER_TYPE,
6008  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_0_WIDTH },
6009  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_1_CHECKER_TYPE,
6010  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_1_WIDTH },
6011  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_2_CHECKER_TYPE,
6012  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_2_WIDTH },
6013  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_3_CHECKER_TYPE,
6014  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_3_WIDTH },
6015  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_4_CHECKER_TYPE,
6016  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_4_WIDTH },
6017  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_5_CHECKER_TYPE,
6018  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_5_WIDTH },
6019  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_6_CHECKER_TYPE,
6020  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_6_WIDTH },
6021  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_7_CHECKER_TYPE,
6022  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_7_WIDTH },
6023  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_8_CHECKER_TYPE,
6024  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_8_WIDTH },
6025  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_9_CHECKER_TYPE,
6026  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_9_WIDTH },
6027  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_10_CHECKER_TYPE,
6028  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_10_WIDTH },
6029  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_11_CHECKER_TYPE,
6030  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_11_WIDTH },
6031  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_12_CHECKER_TYPE,
6032  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_12_WIDTH },
6033  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_13_CHECKER_TYPE,
6034  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_13_WIDTH },
6035  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_14_CHECKER_TYPE,
6036  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_14_WIDTH },
6037  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_15_CHECKER_TYPE,
6038  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_15_WIDTH },
6039  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_16_CHECKER_TYPE,
6040  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_16_WIDTH },
6041  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_17_CHECKER_TYPE,
6042  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_17_WIDTH },
6043  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_18_CHECKER_TYPE,
6044  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_18_WIDTH },
6045  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_19_CHECKER_TYPE,
6046  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_19_WIDTH },
6047  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_20_CHECKER_TYPE,
6048  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_20_WIDTH },
6049  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_21_CHECKER_TYPE,
6050  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_21_WIDTH },
6051  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_22_CHECKER_TYPE,
6052  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_22_WIDTH },
6053  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_23_CHECKER_TYPE,
6054  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_23_WIDTH },
6055  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_24_CHECKER_TYPE,
6056  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_24_WIDTH },
6057  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_25_CHECKER_TYPE,
6058  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_25_WIDTH },
6059  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_26_CHECKER_TYPE,
6060  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_26_WIDTH },
6061  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_27_CHECKER_TYPE,
6062  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_27_WIDTH },
6063  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_28_CHECKER_TYPE,
6064  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_28_WIDTH },
6065  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_29_CHECKER_TYPE,
6066  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_29_WIDTH },
6067  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_30_CHECKER_TYPE,
6068  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_30_WIDTH },
6069  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_31_CHECKER_TYPE,
6070  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_31_WIDTH },
6071  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_32_CHECKER_TYPE,
6072  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_32_WIDTH },
6073  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_33_CHECKER_TYPE,
6074  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_33_WIDTH },
6075  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_34_CHECKER_TYPE,
6076  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_34_WIDTH },
6077  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_35_CHECKER_TYPE,
6078  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_35_WIDTH },
6079 };
6080 
6086 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6087 {
6088  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6089  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_0_WIDTH },
6090  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6091  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_1_WIDTH },
6092  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6093  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_2_WIDTH },
6094  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6095  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_3_WIDTH },
6096  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6097  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_4_WIDTH },
6098  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6099  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_5_WIDTH },
6100  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6101  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_6_WIDTH },
6102  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6103  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_7_WIDTH },
6104  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6105  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_8_WIDTH },
6106  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6107  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_9_WIDTH },
6108  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6109  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_10_WIDTH },
6110  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6111  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_11_WIDTH },
6112  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6113  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_12_WIDTH },
6114  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6115  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_13_WIDTH },
6116  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6117  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_14_WIDTH },
6118  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6119  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_15_WIDTH },
6120  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6121  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_16_WIDTH },
6122  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6123  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_17_WIDTH },
6124  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6125  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_18_WIDTH },
6126  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6127  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_19_WIDTH },
6128  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6129  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_20_WIDTH },
6130  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6131  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_21_WIDTH },
6132  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6133  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_22_WIDTH },
6134  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6135  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_23_WIDTH },
6136  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6137  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_24_WIDTH },
6138  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6139  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_25_WIDTH },
6140  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6141  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_26_WIDTH },
6142  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6143  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_27_WIDTH },
6144  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6145  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_28_WIDTH },
6146  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6147  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_29_WIDTH },
6148  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6149  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_30_WIDTH },
6150  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6151  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_31_WIDTH },
6152  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6153  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_32_WIDTH },
6154  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6155  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_33_WIDTH },
6156  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6157  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_34_WIDTH },
6158  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6159  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_35_WIDTH },
6160  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
6161  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_36_WIDTH },
6162 };
6163 
6169 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6170 {
6171  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6172  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_0_WIDTH },
6173  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6174  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_1_WIDTH },
6175  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6176  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_2_WIDTH },
6177  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6178  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_3_WIDTH },
6179  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6180  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_4_WIDTH },
6181  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6182  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_5_WIDTH },
6183  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6184  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_6_WIDTH },
6185  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6186  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_7_WIDTH },
6187  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6188  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_8_WIDTH },
6189  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6190  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_9_WIDTH },
6191  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6192  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_10_WIDTH },
6193  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6194  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_11_WIDTH },
6195  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6196  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_12_WIDTH },
6197  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6198  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_13_WIDTH },
6199  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6200  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_14_WIDTH },
6201 };
6202 
6208 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS] =
6209 {
6210  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_0_CHECKER_TYPE,
6211  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_0_WIDTH },
6212  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_1_CHECKER_TYPE,
6213  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_1_WIDTH },
6214  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_2_CHECKER_TYPE,
6215  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_2_WIDTH },
6216  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_3_CHECKER_TYPE,
6217  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_3_WIDTH },
6218  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_4_CHECKER_TYPE,
6219  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_4_WIDTH },
6220  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_5_CHECKER_TYPE,
6221  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_5_WIDTH },
6222  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_6_CHECKER_TYPE,
6223  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_6_WIDTH },
6224  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_7_CHECKER_TYPE,
6225  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_7_WIDTH },
6226  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_8_CHECKER_TYPE,
6227  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_8_WIDTH },
6228  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_9_CHECKER_TYPE,
6229  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_9_WIDTH },
6230  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_10_CHECKER_TYPE,
6231  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_10_WIDTH },
6232 };
6233 
6239 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
6240 {
6241  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
6242  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
6243  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
6244  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
6245  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
6246  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
6247  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
6248  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
6249  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
6250  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
6251  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
6252  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
6253  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
6254  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
6255  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
6256  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
6257  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
6258  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
6259  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
6260  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
6261  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
6262  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
6263  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
6264  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
6265  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
6266  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
6267  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
6268  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
6269  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
6270  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
6271  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
6272  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
6273  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
6274  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
6275  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
6276  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
6277  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
6278  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
6279  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
6280  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
6281  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
6282  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
6283  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
6284  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
6285  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
6286  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
6287  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
6288  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
6289  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
6290  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
6291  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
6292  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
6293  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
6294  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
6295  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
6296  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
6297  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
6298  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
6299  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
6300  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
6301  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
6302  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
6303  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
6304  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
6305  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
6306  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
6307  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
6308  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
6309  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
6310  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
6311  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
6312  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
6313  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
6314  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
6315  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
6316  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
6317  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
6318  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
6319  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
6320  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
6321  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
6322  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
6323  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
6324  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
6325  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
6326  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
6327  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
6328  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
6329  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
6330  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
6331  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
6332  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
6333  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
6334  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
6335  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
6336  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
6337  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
6338  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
6339  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
6340  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
6341  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
6342  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
6343  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
6344  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
6345  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
6346  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
6347  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
6348  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
6349  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
6350  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
6351  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
6352  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
6353  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
6354  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
6355  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
6356  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
6357  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
6358  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
6359  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
6360  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
6361  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
6362  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
6363  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
6364  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
6365  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
6366  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
6367  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
6368  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
6369  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
6370  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
6371  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
6372  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
6373  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
6374  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
6375  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
6376  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
6377 };
6378 
6384 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
6385 {
6386  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6387  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
6388  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6389  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
6390  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6391  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
6392  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6393  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
6394  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6395  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
6396  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6397  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
6398 };
6399 
6405 {
6406  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID, 0u,
6407  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_SIZE, 4u,
6408  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ROW_WIDTH, ((bool)true) },
6409  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID, 0u,
6410  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_SIZE, 4u,
6411  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ROW_WIDTH, ((bool)true) },
6412  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID, 0u,
6413  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_SIZE, 4u,
6414  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ROW_WIDTH, ((bool)true) },
6415 };
6416 
6422 {
6423  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID, 0u,
6424  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_SIZE, 4u,
6425  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ROW_WIDTH, ((bool)false) },
6426  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_RAM_ID, 0u,
6427  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_RAM_SIZE, 4u,
6428  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_ROW_WIDTH, ((bool)false) },
6429  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_RAM_ID, 0u,
6430  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_RAM_SIZE, 4u,
6431  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_ROW_WIDTH, ((bool)false) },
6432  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_RAM_ID, 0u,
6433  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_RAM_SIZE, 4u,
6434  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_ROW_WIDTH, ((bool)false) },
6435  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_RAM_ID, 0u,
6436  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_RAM_SIZE, 4u,
6437  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_ROW_WIDTH, ((bool)false) },
6438  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_RAM_ID, 0u,
6439  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_RAM_SIZE, 4u,
6440  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_ROW_WIDTH, ((bool)false) },
6441  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_RAM_ID, 0u,
6442  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_RAM_SIZE, 4u,
6443  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_ROW_WIDTH, ((bool)false) },
6444  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID, 0u,
6445  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_SIZE, 4u,
6446  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ROW_WIDTH, ((bool)false) },
6447 };
6448 
6454 {
6455  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
6456  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
6457  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
6458  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
6459  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
6460  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
6461  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
6462  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
6463  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
6464  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
6465  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
6466  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
6467  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
6468  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
6469  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
6470  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
6471  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
6472  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
6473  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
6474  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
6475  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
6476 };
6477 
6483 static const SDL_GrpChkConfig_t SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6484 {
6485  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6486  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
6487  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6488  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
6489 };
6490 
6496 {
6497  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
6498  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
6499  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
6500  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
6501  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
6502  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
6503  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
6504  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
6505  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
6506  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
6507  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
6508  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
6509  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
6510  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
6511  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
6512  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
6513  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
6514  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
6515  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
6516  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
6517  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
6518 };
6519 
6525 static const SDL_GrpChkConfig_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6526 {
6527  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6528  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
6529  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6530  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
6531 };
6532 
6538 {
6539  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
6540  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
6541  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
6542  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
6543  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
6544  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
6545  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
6546  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
6547  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
6548  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
6549  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
6550  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
6551  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
6552  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
6553  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
6554  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
6555  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
6556  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
6557  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
6558  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
6559  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
6560 };
6561 
6567 static const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6568 {
6569  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6570  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
6571  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6572  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
6573 };
6574 
6580 {
6581  { SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
6582  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
6583  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
6584 };
6585 
6591 {
6592  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
6593  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
6594  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
6595 };
6596 
6602 {
6603  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
6604  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
6605  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
6606 };
6607 
6613 {
6614  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
6615  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_SIZE, 4u,
6616  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
6617  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID, 0u,
6618  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_SIZE, 4u,
6619  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
6620  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
6621  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_SIZE, 4u,
6622  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
6623  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
6624  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_SIZE, 4u,
6625  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
6626  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
6627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_SIZE, 4u,
6628  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
6629  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
6630  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_SIZE, 4u,
6631  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
6632  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
6633  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
6634  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
6635  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID, 0u,
6636  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_SIZE, 4u,
6637  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
6638  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID, 0u,
6639  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_SIZE, 4u,
6640  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
6641  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
6642  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
6643  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
6644  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID, 0u,
6645  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_SIZE, 4u,
6646  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ROW_WIDTH, ((bool)false) },
6647  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID, 0u,
6648  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_SIZE, 4u,
6649  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ROW_WIDTH, ((bool)false) },
6650  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
6651  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_SIZE, 4u,
6652  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)false) },
6653  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
6654  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 4u,
6655  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)false) },
6656  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
6657  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 4u,
6658  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
6659  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
6660  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_SIZE, 4u,
6661  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)false) },
6662 };
6663 
6669 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
6670 {
6671  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6672  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
6673  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6674  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
6675  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6676  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
6677  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
6679  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6680  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
6681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
6683 };
6684 
6690 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6691 {
6692  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6693  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_WIDTH },
6694  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6695  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_WIDTH },
6696  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6697  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_WIDTH },
6698  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6699  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_WIDTH },
6700  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6701  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_WIDTH },
6702  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6703  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_WIDTH },
6704  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6705  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_WIDTH },
6706  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6707  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_WIDTH },
6708  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6709  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_WIDTH },
6710  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6711  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_WIDTH },
6712  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6713  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_WIDTH },
6714  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6715  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_WIDTH },
6716  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6717  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_WIDTH },
6718  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6719  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_WIDTH },
6720  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6721  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_WIDTH },
6722  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6723  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_WIDTH },
6724  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6725  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_WIDTH },
6726  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6727  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_WIDTH },
6728  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6729  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_WIDTH },
6730  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6731  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_WIDTH },
6732  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6733  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_WIDTH },
6734  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6735  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_WIDTH },
6736  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6737  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_WIDTH },
6738  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6739  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_WIDTH },
6740  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6741  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_WIDTH },
6742  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6743  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_WIDTH },
6744  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6745  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_WIDTH },
6746  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6747  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_WIDTH },
6748  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6749  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_WIDTH },
6750  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6751  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_WIDTH },
6752  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6753  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_WIDTH },
6754  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6755  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_WIDTH },
6756  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6757  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_WIDTH },
6758  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6759  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_WIDTH },
6760  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6761  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_WIDTH },
6762  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6763  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_WIDTH },
6764  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
6765  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_WIDTH },
6766  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
6767  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_WIDTH },
6768  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
6769  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_WIDTH },
6770  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
6771  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_WIDTH },
6772  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
6773  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_WIDTH },
6774  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
6775  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_WIDTH },
6776  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
6777  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_WIDTH },
6778  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
6779  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_WIDTH },
6780  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
6781  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_WIDTH },
6782  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
6783  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_WIDTH },
6784  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
6785  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_WIDTH },
6786  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
6787  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_WIDTH },
6788  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
6789  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_WIDTH },
6790  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
6791  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_WIDTH },
6792  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
6793  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_WIDTH },
6794  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
6795  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_WIDTH },
6796  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
6797  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_WIDTH },
6798  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
6799  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_WIDTH },
6800  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
6801  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_WIDTH },
6802  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
6803  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_WIDTH },
6804  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
6805  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_WIDTH },
6806  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
6807  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_WIDTH },
6808  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
6809  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_WIDTH },
6810  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
6811  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_WIDTH },
6812  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
6813  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_WIDTH },
6814  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
6815  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_WIDTH },
6816  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
6817  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_WIDTH },
6818  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
6819  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_WIDTH },
6820  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
6821  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_WIDTH },
6822  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
6823  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_WIDTH },
6824  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
6825  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_WIDTH },
6826  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
6827  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_WIDTH },
6828  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
6829  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_WIDTH },
6830  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
6831  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_WIDTH },
6832  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
6833  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_WIDTH },
6834  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
6835  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_WIDTH },
6836 };
6837 
6843 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6844 {
6845  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6846  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
6847  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6848  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
6849  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6850  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
6851  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6852  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
6853  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6854  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
6855  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6856  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
6857  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6858  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_WIDTH },
6859  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6860  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_WIDTH },
6861  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6862  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_WIDTH },
6863  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6864  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_WIDTH },
6865  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6866  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_WIDTH },
6867  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6868  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_WIDTH },
6869  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6870  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_WIDTH },
6871  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6872  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_WIDTH },
6873  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6874  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_WIDTH },
6875  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6876  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_WIDTH },
6877  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6878  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_WIDTH },
6879  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6880  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_WIDTH },
6881 };
6882 
6888 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6889 {
6890  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6891  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_WIDTH },
6892  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6893  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_WIDTH },
6894  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6895  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_WIDTH },
6896  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6897  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_WIDTH },
6898  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6899  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_WIDTH },
6900  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6901  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_WIDTH },
6902  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6903  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_WIDTH },
6904  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6905  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_WIDTH },
6906  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6907  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_WIDTH },
6908  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6909  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_WIDTH },
6910  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6911  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_WIDTH },
6912  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6913  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_WIDTH },
6914  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6915  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_WIDTH },
6916  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6917  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_WIDTH },
6918  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6919  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_WIDTH },
6920  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6921  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_WIDTH },
6922  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6923  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_WIDTH },
6924  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6925  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_WIDTH },
6926  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6927  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_WIDTH },
6928  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6929  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_WIDTH },
6930  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6931  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_WIDTH },
6932  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6933  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_WIDTH },
6934  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6935  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_WIDTH },
6936  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6937  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_WIDTH },
6938  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6939  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_WIDTH },
6940  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6941  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_WIDTH },
6942  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6943  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_WIDTH },
6944  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6945  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_WIDTH },
6946  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6947  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_WIDTH },
6948  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6949  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_WIDTH },
6950  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6951  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_WIDTH },
6952  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6953  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_WIDTH },
6954  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6955  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_WIDTH },
6956  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6957  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_WIDTH },
6958  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6959  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_WIDTH },
6960  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6961  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_WIDTH },
6962  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
6963  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_WIDTH },
6964  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
6965  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_WIDTH },
6966  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
6967  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_WIDTH },
6968  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
6969  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_WIDTH },
6970  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
6971  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_WIDTH },
6972  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
6973  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_WIDTH },
6974  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
6975  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_WIDTH },
6976  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
6977  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_WIDTH },
6978  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
6979  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_WIDTH },
6980  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
6981  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_WIDTH },
6982  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
6983  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_WIDTH },
6984  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
6985  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_WIDTH },
6986  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
6987  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_WIDTH },
6988  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
6989  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_WIDTH },
6990  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
6991  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_WIDTH },
6992  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
6993  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_WIDTH },
6994  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
6995  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_WIDTH },
6996  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
6997  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_WIDTH },
6998  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
6999  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_WIDTH },
7000  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7001  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_WIDTH },
7002  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7003  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_WIDTH },
7004  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7005  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_WIDTH },
7006  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7007  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_WIDTH },
7008  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7009  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_WIDTH },
7010  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7011  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_WIDTH },
7012  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7013  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_WIDTH },
7014  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7015  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_WIDTH },
7016  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7017  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_WIDTH },
7018  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7019  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_WIDTH },
7020  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7021  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_WIDTH },
7022  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7023  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_WIDTH },
7024  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7025  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_WIDTH },
7026  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7027  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_WIDTH },
7028  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7029  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_WIDTH },
7030  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7031  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_WIDTH },
7032  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7033  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_WIDTH },
7034  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
7035  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_WIDTH },
7036  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
7037  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_WIDTH },
7038  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
7039  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_WIDTH },
7040  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
7041  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_WIDTH },
7042  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
7043  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_WIDTH },
7044  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
7045  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_WIDTH },
7046  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
7047  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_WIDTH },
7048  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
7049  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_WIDTH },
7050  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
7051  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_WIDTH },
7052  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
7053  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_WIDTH },
7054  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
7055  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_WIDTH },
7056  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
7057  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_WIDTH },
7058  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
7059  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_WIDTH },
7060  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
7061  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_WIDTH },
7062  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
7063  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_WIDTH },
7064  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
7065  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_WIDTH },
7066  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
7067  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_WIDTH },
7068  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
7069  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_WIDTH },
7070  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
7071  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_WIDTH },
7072  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
7073  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_WIDTH },
7074  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
7075  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_WIDTH },
7076  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
7077  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_WIDTH },
7078  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
7079  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_WIDTH },
7080  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
7081  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_WIDTH },
7082  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
7083  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_WIDTH },
7084  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
7085  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_WIDTH },
7086  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
7087  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_WIDTH },
7088  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
7089  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_WIDTH },
7090  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
7091  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_WIDTH },
7092  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
7093  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_WIDTH },
7094  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
7095  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_WIDTH },
7096  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
7097  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_WIDTH },
7098  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
7099  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_WIDTH },
7100  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
7101  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_WIDTH },
7102  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
7103  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_WIDTH },
7104  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
7105  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_WIDTH },
7106  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
7107  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_WIDTH },
7108  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
7109  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_WIDTH },
7110  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
7111  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_WIDTH },
7112  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
7113  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_WIDTH },
7114  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
7115  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_WIDTH },
7116  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
7117  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_WIDTH },
7118  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
7119  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_WIDTH },
7120  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
7121  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_WIDTH },
7122  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
7123  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_WIDTH },
7124  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
7125  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_WIDTH },
7126  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
7127  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_WIDTH },
7128  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
7129  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_WIDTH },
7130  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
7131  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_WIDTH },
7132  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
7133  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_WIDTH },
7134  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
7135  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_WIDTH },
7136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
7137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_WIDTH },
7138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
7139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_WIDTH },
7140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
7141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_WIDTH },
7142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
7143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_WIDTH },
7144  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
7145  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_WIDTH },
7146  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
7147  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_WIDTH },
7148  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
7149  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_WIDTH },
7150  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
7151  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_WIDTH },
7152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
7153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_WIDTH },
7154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
7155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_WIDTH },
7156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
7157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_WIDTH },
7158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
7159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_WIDTH },
7160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
7161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_WIDTH },
7162  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
7163  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_WIDTH },
7164  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
7165  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_WIDTH },
7166  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
7167  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_WIDTH },
7168  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
7169  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_WIDTH },
7170  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
7171  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_WIDTH },
7172  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
7173  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_WIDTH },
7174  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
7175  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_WIDTH },
7176  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
7177  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_WIDTH },
7178  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
7179  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_WIDTH },
7180  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
7181  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_WIDTH },
7182  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
7183  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_WIDTH },
7184  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
7185  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_WIDTH },
7186  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
7187  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_WIDTH },
7188  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
7189  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_WIDTH },
7190  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
7191  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_WIDTH },
7192  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
7193  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_WIDTH },
7194  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
7195  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_WIDTH },
7196  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
7197  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_WIDTH },
7198  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
7199  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_WIDTH },
7200  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
7201  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_WIDTH },
7202  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
7203  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_WIDTH },
7204  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
7205  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_WIDTH },
7206  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
7207  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_WIDTH },
7208  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
7209  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_WIDTH },
7210  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
7211  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_WIDTH },
7212  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
7213  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_WIDTH },
7214  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
7215  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_WIDTH },
7216  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
7217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_WIDTH },
7218  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
7219  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_WIDTH },
7220  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
7221  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_WIDTH },
7222  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
7223  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_WIDTH },
7224  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
7225  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_WIDTH },
7226  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
7227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_WIDTH },
7228  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
7229  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_WIDTH },
7230  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
7231  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_WIDTH },
7232  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
7233  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_WIDTH },
7234  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
7235  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_WIDTH },
7236  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
7237  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_WIDTH },
7238  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
7239  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_WIDTH },
7240  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
7241  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_WIDTH },
7242  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
7243  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_WIDTH },
7244  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
7245  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_WIDTH },
7246  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
7247  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_WIDTH },
7248  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
7249  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_WIDTH },
7250  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
7251  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_WIDTH },
7252  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
7253  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_WIDTH },
7254  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
7255  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_WIDTH },
7256  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
7257  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_WIDTH },
7258  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
7259  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_WIDTH },
7260  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
7261  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_WIDTH },
7262  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
7263  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_WIDTH },
7264  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
7265  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_WIDTH },
7266  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
7267  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_WIDTH },
7268  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
7269  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_WIDTH },
7270  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
7271  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_WIDTH },
7272  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
7273  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_WIDTH },
7274  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
7275  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_WIDTH },
7276  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
7277  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_WIDTH },
7278  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
7279  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_WIDTH },
7280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
7281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_WIDTH },
7282  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
7283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_WIDTH },
7284  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
7285  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_WIDTH },
7286  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
7287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_WIDTH },
7288  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
7289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_WIDTH },
7290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
7291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_WIDTH },
7292  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
7293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_WIDTH },
7294  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
7295  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_WIDTH },
7296  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
7297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_WIDTH },
7298  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
7299  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_WIDTH },
7300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
7301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_WIDTH },
7302  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
7303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_WIDTH },
7304  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
7305  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_WIDTH },
7306  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
7307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_WIDTH },
7308  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
7309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_WIDTH },
7310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
7311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_WIDTH },
7312  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
7313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_WIDTH },
7314  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
7315  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_WIDTH },
7316  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
7317  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_WIDTH },
7318  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
7319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_WIDTH },
7320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
7321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_WIDTH },
7322  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
7323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_WIDTH },
7324  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
7325  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_WIDTH },
7326  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
7327  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_WIDTH },
7328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
7329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_WIDTH },
7330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
7331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_WIDTH },
7332  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
7333  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_WIDTH },
7334  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
7335  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_WIDTH },
7336  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
7337  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_WIDTH },
7338  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
7339  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_WIDTH },
7340  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
7341  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_WIDTH },
7342  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
7343  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_WIDTH },
7344  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
7345  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_WIDTH },
7346  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
7347  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_WIDTH },
7348  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
7349  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_WIDTH },
7350  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
7351  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_WIDTH },
7352  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
7353  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_WIDTH },
7354  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
7355  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_WIDTH },
7356  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
7357  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_WIDTH },
7358  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
7359  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_WIDTH },
7360  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
7361  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_WIDTH },
7362  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
7363  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_WIDTH },
7364  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
7365  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_WIDTH },
7366  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
7367  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_WIDTH },
7368  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
7369  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_WIDTH },
7370  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
7371  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_WIDTH },
7372  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
7373  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_WIDTH },
7374  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
7375  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_WIDTH },
7376  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
7377  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_WIDTH },
7378  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
7379  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_WIDTH },
7380  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
7381  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_WIDTH },
7382  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
7383  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_WIDTH },
7384  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
7385  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_WIDTH },
7386  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
7387  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_WIDTH },
7388  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
7389  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_WIDTH },
7390  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
7391  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_WIDTH },
7392  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
7393  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_WIDTH },
7394  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
7395  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_WIDTH },
7396  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
7397  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_WIDTH },
7398  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
7399  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_WIDTH },
7400  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
7401  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_WIDTH },
7402 };
7403 
7409 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS] =
7410 {
7411  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
7412  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_WIDTH },
7413  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
7414  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_WIDTH },
7415  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
7416  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_WIDTH },
7417  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
7418  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_WIDTH },
7419  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
7420  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_WIDTH },
7421  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
7422  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_WIDTH },
7423  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
7424  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_WIDTH },
7425  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
7426  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_WIDTH },
7427  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
7428  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_WIDTH },
7429  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
7430  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_WIDTH },
7431  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
7432  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_WIDTH },
7433  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
7434  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_WIDTH },
7435  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
7436  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_WIDTH },
7437  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
7438  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_WIDTH },
7439  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
7440  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_WIDTH },
7441  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
7442  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_WIDTH },
7443  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
7444  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_WIDTH },
7445  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
7446  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_WIDTH },
7447  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
7448  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_WIDTH },
7449  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
7450  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_WIDTH },
7451  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
7452  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_WIDTH },
7453  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
7454  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_WIDTH },
7455  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
7456  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_WIDTH },
7457  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
7458  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_WIDTH },
7459  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
7460  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_WIDTH },
7461  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
7462  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_WIDTH },
7463  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
7464  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_WIDTH },
7465  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
7466  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_WIDTH },
7467  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
7468  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_WIDTH },
7469  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
7470  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_WIDTH },
7471  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
7472  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_WIDTH },
7473  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
7474  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_WIDTH },
7475  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
7476  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_WIDTH },
7477  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
7478  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_WIDTH },
7479  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
7480  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_WIDTH },
7481  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
7482  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_WIDTH },
7483  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
7484  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_WIDTH },
7485  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
7486  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_WIDTH },
7487  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
7488  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_WIDTH },
7489  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
7490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_WIDTH },
7491  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
7492  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_WIDTH },
7493  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
7494  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_WIDTH },
7495  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
7496  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_WIDTH },
7497  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
7498  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_WIDTH },
7499  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
7500  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_WIDTH },
7501  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
7502  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_WIDTH },
7503  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
7504  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_WIDTH },
7505  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
7506  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_WIDTH },
7507  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
7508  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_WIDTH },
7509  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
7510  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_WIDTH },
7511  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
7512  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_WIDTH },
7513  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
7514  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_WIDTH },
7515  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
7516  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_WIDTH },
7517  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
7518  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_WIDTH },
7519  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
7520  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_WIDTH },
7521  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
7522  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_WIDTH },
7523  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
7524  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_WIDTH },
7525 };
7526 
7532 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7533 {
7534  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7535  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_WIDTH },
7536  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7537  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_WIDTH },
7538  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7539  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_WIDTH },
7540  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7541  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_WIDTH },
7542  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7543  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_WIDTH },
7544  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7545  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_WIDTH },
7546  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7547  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_WIDTH },
7548  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7549  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_WIDTH },
7550  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_WIDTH },
7552  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7553  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_WIDTH },
7554  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_WIDTH },
7556  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7557  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_WIDTH },
7558  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7559  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_WIDTH },
7560  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7561  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_WIDTH },
7562  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7563  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_WIDTH },
7564  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7565  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_WIDTH },
7566  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7567  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_WIDTH },
7568  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7569  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_WIDTH },
7570  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7571  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_WIDTH },
7572  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7573  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_WIDTH },
7574  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7575  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_WIDTH },
7576  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7577  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_WIDTH },
7578  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7579  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_WIDTH },
7580  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7581  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_WIDTH },
7582  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7583  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_WIDTH },
7584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_WIDTH },
7586  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_WIDTH },
7588  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7589  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_WIDTH },
7590  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7591  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_WIDTH },
7592  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_WIDTH },
7594  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_WIDTH },
7596  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7597  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_WIDTH },
7598  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7599  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_WIDTH },
7600  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7601  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_WIDTH },
7602  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7603  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_WIDTH },
7604  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7605  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_WIDTH },
7606  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7607  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_WIDTH },
7608  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7609  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_WIDTH },
7610  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7611  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_WIDTH },
7612  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7613  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_WIDTH },
7614  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7615  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_WIDTH },
7616  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7617  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_WIDTH },
7618  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7619  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_WIDTH },
7620  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7621  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_WIDTH },
7622  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7623  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_WIDTH },
7624  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7625  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_WIDTH },
7626  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_WIDTH },
7628  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7629  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_WIDTH },
7630  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7631  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_WIDTH },
7632  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7633  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_WIDTH },
7634  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7635  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_WIDTH },
7636  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7637  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_WIDTH },
7638  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7639  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_WIDTH },
7640  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7641  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_WIDTH },
7642  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7643  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_WIDTH },
7644  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7645  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_WIDTH },
7646  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7647  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_WIDTH },
7648  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7649  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_WIDTH },
7650  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7651  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_WIDTH },
7652  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7653  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_WIDTH },
7654  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7655  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_WIDTH },
7656  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7657  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_WIDTH },
7658  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7659  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_WIDTH },
7660  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7661  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_WIDTH },
7662  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7663  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_WIDTH },
7664  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7665  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_WIDTH },
7666  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7667  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_WIDTH },
7668 };
7669 
7675 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7676 {
7677  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
7679  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7680  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
7681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
7683  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7684  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
7685  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7686  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
7687  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
7689  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7690  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
7691  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7692  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
7693  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7694  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
7695  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7696  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
7697  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7698  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
7699  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7700  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
7701  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7702  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
7703  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7704  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
7705  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7706  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
7707  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7708  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
7709  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7710  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
7711  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7712  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
7713  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7714  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
7715  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7716  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
7717  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7718  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
7719  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7720  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
7721  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7722  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
7723  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7724  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
7725  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7726  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
7727  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7728  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
7729  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7730  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
7731  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7732  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
7733  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7734  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
7735  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7736  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
7737  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7738  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
7739  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7740  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
7741  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7742  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
7743  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7744  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
7745  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7746  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
7747  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7748  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
7749  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7750  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
7751  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7752  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
7753  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7754  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
7755  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7756  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
7757  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7758  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
7759  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7760  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
7761  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7762  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
7763  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7764  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_WIDTH },
7765  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7766  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_WIDTH },
7767  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7768  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_WIDTH },
7769  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_WIDTH },
7771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_WIDTH },
7773  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_WIDTH },
7775  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7776  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_WIDTH },
7777  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_WIDTH },
7779  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_WIDTH },
7781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_WIDTH },
7783  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_WIDTH },
7785  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7786  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_WIDTH },
7787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_WIDTH },
7789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_WIDTH },
7791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_WIDTH },
7793  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_WIDTH },
7795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_WIDTH },
7797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_WIDTH },
7799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_WIDTH },
7801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_WIDTH },
7803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_WIDTH },
7805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_WIDTH },
7807  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_WIDTH },
7809  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_WIDTH },
7811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_WIDTH },
7813  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_WIDTH },
7815  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7816  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_WIDTH },
7817  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_WIDTH },
7819  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_WIDTH },
7821 };
7822 
7828 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7829 {
7830  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7831  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
7832  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7833  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
7834  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7835  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
7836  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7837  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
7838  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7839  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
7840  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7841  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
7842  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7843  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
7844  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7845  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
7846  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7847  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
7848  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7849  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
7850  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7851  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
7852  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7853  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
7854  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7855  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
7856  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7857  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
7858  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7859  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
7860  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7861  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
7862  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7863  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
7864  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7865  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
7866  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7867  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
7868  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7869  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
7870  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7871  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
7872  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7873  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
7874  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7875  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
7876  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7877  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
7878  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7879  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
7880  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7881  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
7882  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7883  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
7884  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7885  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
7886  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7887  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
7888  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7889  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
7890  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7891  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
7892  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7893  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
7894  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7895  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
7896  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7897  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
7898  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7899  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
7900  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7901  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
7902  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7903  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
7904  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7905  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
7906  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7907  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
7908  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7909  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
7910  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7911  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
7912  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7913  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
7914  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7915  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
7916  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7917  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
7918  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7919  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
7920  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7921  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
7922  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7923  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
7924  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7925  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
7926  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7927  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
7928  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7929  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
7930  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7931  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
7932  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7933  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
7934  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7935  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
7936  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7937  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
7938  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7939  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
7940  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7941  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
7942  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7943  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
7944  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7945  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
7946  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7947  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
7948  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7949  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
7950  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7951  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
7952  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7953  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
7954  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7955  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
7956  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7957  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
7958  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7959  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
7960  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7961  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
7962  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7963  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
7964  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7965  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
7966  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7967  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
7968  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7969  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
7970  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7971  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
7972  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7973  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
7974  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
7975  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
7976  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
7977  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
7978  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
7979  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
7980  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
7981  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
7982  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
7983  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
7984  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
7985  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
7986  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
7987  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
7988  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
7989  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
7990  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
7991  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
7992  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
7993  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
7994  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
7995  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
7996  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
7997  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
7998  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
7999  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
8000  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
8001  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
8002  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
8003  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
8004  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
8005  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
8006  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
8007  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
8008  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
8009  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
8010  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
8011  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
8012  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
8013  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
8014  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
8015  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
8016  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
8017  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
8018  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
8019  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
8020  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
8021  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
8022  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
8023  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
8024  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
8025  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
8026  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
8027  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
8028  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
8029  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
8030  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
8031  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
8032  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
8033  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
8034  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
8035  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
8036  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
8037  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
8038  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
8039  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
8040  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
8041  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
8042  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
8043  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
8044  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
8045  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
8046  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
8047  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
8048  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
8049  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
8050  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
8051  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
8052  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
8053  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
8054  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
8055  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
8056  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
8057  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
8058  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
8059  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
8060  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
8061  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
8062  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
8063  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
8064  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
8065  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
8066  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
8067  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
8068  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
8069  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
8070  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
8071  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
8072  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
8073  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
8074  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
8075  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
8076  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
8077  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
8078  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
8079  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
8080  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
8081  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
8082  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
8083  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
8084  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
8085  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
8086  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
8087  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
8088  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
8089  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
8090  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
8091  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
8092  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
8093  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
8094 };
8095 
8101 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8102 {
8103  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8104  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
8105  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8106  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
8107  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8108  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
8109 };
8110 
8116 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8117 {
8118  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8119  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_WIDTH },
8120  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8121  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_WIDTH },
8122  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8123  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_WIDTH },
8124  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8125  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_WIDTH },
8126  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8127  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_WIDTH },
8128  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8129  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_WIDTH },
8130  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8131  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_WIDTH },
8132  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8133  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_WIDTH },
8134  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8135  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_WIDTH },
8136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_WIDTH },
8138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_WIDTH },
8140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_WIDTH },
8142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_WIDTH },
8144  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8145  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_WIDTH },
8146  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8147  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_WIDTH },
8148  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8149  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_WIDTH },
8150  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8151  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_WIDTH },
8152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_WIDTH },
8154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_WIDTH },
8156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_WIDTH },
8158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_WIDTH },
8160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_WIDTH },
8162  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8163  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_WIDTH },
8164  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8165  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_WIDTH },
8166  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8167  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_WIDTH },
8168  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8169  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_WIDTH },
8170  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8171  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_WIDTH },
8172  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8173  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_WIDTH },
8174  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8175  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_WIDTH },
8176  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8177  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_WIDTH },
8178  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8179  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_WIDTH },
8180  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8181  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_WIDTH },
8182  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8183  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_WIDTH },
8184  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8185  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_WIDTH },
8186  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8187  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_WIDTH },
8188  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8189  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_WIDTH },
8190  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8191  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_WIDTH },
8192  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8193  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_WIDTH },
8194  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8195  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_WIDTH },
8196  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8197  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_WIDTH },
8198  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8199  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_WIDTH },
8200  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8201  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_WIDTH },
8202  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8203  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_WIDTH },
8204  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8205  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_WIDTH },
8206  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8207  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_WIDTH },
8208  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8209  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_WIDTH },
8210  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8211  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_WIDTH },
8212  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8213  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_WIDTH },
8214  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8215  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_WIDTH },
8216  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_WIDTH },
8218  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8219  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_WIDTH },
8220  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8221  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_WIDTH },
8222  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8223  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_WIDTH },
8224  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8225  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_WIDTH },
8226  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_WIDTH },
8228  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8229  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_WIDTH },
8230  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8231  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_WIDTH },
8232  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8233  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_WIDTH },
8234  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8235  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_WIDTH },
8236  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8237  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_WIDTH },
8238  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8239  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_WIDTH },
8240  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8241  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_WIDTH },
8242  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8243  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_WIDTH },
8244 };
8245 
8251 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8252 {
8253  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8254  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8255  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8256  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8257  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8258  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8259  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8260  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8261  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8262  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8263  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8264  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8265  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8266  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8267  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8268  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8269  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8270  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8271  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8272  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8273  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8274  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8275  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8276  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8277  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8278  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8279  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8280  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8281  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8282  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8283  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8284  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8285  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8286  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8287  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8288  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8289  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8290  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8291  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8292  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8293  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8294  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8295  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8296  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8297  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8298  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8299  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8300  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8301  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8302  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8303  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8304  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8305  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8306  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8307  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8308  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8309  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8310  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8311  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8312  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8313  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8314  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
8315  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8316  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
8317  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8318  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
8319 };
8320 
8326 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8327 {
8328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8332  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8333  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8334  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8335  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8336  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8337  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8338  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8339  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8340  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8341  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8342  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8343  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8344  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8345  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8346  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8347  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8348  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8349  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8350  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8351  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8352  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8353  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8354  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8355  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8356  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8357  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8358  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8359  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8360  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8361  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8362  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8363  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8364  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8365  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8366  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8367  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8368  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8369  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8370  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8371  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8372  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8373  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8374  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8375  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8376  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8377  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8378  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8379  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8380  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8381  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8382  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8383  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8384  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8385  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8386  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8387  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8388  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8389  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
8390  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8391  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
8392  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8393  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
8394 };
8395 
8401 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8402 {
8403  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8404  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8405  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8406  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8407  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8408  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8409  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8410  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8411  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8412  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8413  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8414  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8415  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8416  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8417  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8418  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8419  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8420  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8421  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8422  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8423  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8424  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8425  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8426  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8427  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8428  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8429  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8430  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8431  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8432  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8433  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8434  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8435  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8436  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8437  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8438  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8439  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8440  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8441  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8442  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8443  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8444  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8445  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8446  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8447  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8448  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8449  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8450  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8451  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8452  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8453  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8454  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8455  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8456  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8457  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8458  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8459  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8460  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8461  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8462  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8463 };
8464 
8470 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8471 {
8472  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8473  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
8474  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8475  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
8476  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8477  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
8478  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8479  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
8480  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8481  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
8482  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8483  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
8484  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8485  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
8486  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8487  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
8488  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8489  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
8490  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8491  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
8492  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8493  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
8494  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8495  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
8496  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8497  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
8498  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8499  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
8500  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8501  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
8502  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8503  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
8504  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
8506  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8507  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
8508  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8509  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
8510  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8511  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
8512  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8513  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
8514  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8515  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
8516  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8517  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
8518  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8519  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
8520  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8521  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
8522  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8523  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
8524  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8525  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
8526  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8527  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
8528  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8529  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
8530  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
8532 };
8533 
8539 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8540 {
8541  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8542  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
8543  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8544  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
8545  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8546  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
8547  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8548  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
8549  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8550  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
8551  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8552  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
8553  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8554  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
8555  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8556  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
8557  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8558  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
8559  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8560  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
8561  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8562  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
8563  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8564  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
8565  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8566  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
8567  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8568  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
8569  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8570  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
8571  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8572  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
8573  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8574  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
8575  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8576  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
8577  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8578  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
8579  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8580  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
8581  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8582  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
8583  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8584  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
8585  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8586  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
8587  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8588  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
8589  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8590  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
8591  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8592  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
8593  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8594  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
8595  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8596  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
8597  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8598  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
8599  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8600  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
8601  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8602  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
8603  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8604  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
8605  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8606  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
8607  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8608  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
8609  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8610  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
8611  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8612  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
8613  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8614  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
8615  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8616  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
8617  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8618  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
8619  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8620  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
8621  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8622  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
8623  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8624  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
8625  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8626  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
8627  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8628  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
8629  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8630  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
8631  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8632  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
8633  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8634  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
8635  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8636  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
8637  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8638  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
8639  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8640  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
8641  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8642  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
8643  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8644  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
8645  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8646  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
8647  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8648  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
8649  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8650  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
8651  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8652  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
8653  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8654  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
8655  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8656  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
8657  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8658  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
8659  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8660  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
8661  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8662  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
8663  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8664  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
8665  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8666  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
8667  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8668  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
8669  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8670  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
8671  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8672  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
8673  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8674  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
8675  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
8676  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
8677  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
8678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
8679  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
8680  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
8681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
8682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
8683  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
8684  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
8685  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
8686  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
8687  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
8688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
8689  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
8690  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
8691  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
8692  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
8693  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
8694  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
8695  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
8696  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
8697  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
8698  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
8699  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
8700  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
8701  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
8702  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
8703  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
8704  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
8705  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
8706  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
8707  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
8708  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
8709  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
8710  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
8711  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
8712  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
8713  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
8714  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
8715  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
8716  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
8717  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
8718  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
8719  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
8720  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
8721  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
8722  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
8723  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
8724  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
8725  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
8726  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
8727  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
8728  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
8729  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
8730  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
8731  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
8732  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
8733  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
8734  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
8735  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
8736  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
8737  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
8738  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
8739  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
8740  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
8741  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
8742  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
8743 };
8744 
8750 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8751 {
8752  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8753  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
8754  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8755  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
8756  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8757  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
8758  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8759  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
8760  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8761  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
8762  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8763  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
8764  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8765  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
8766  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8767  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
8768  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8769  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
8770  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8771  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
8772  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8773  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
8774  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8775  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
8776  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8777  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
8778  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8779  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
8780  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8781  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
8782  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8783  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
8784  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8785  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
8786  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8787  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
8788  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8789  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
8790  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8791  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
8792  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8793  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
8794  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8795  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
8796  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8797  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
8798  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8799  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
8800  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8801  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
8802  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8803  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
8804  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8805  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
8806  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8807  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
8808  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8809  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
8810  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8811  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
8812  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8813  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
8814  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8815  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
8816  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8817  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
8818  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8819  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
8820  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8821  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
8822  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8823  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
8824  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8825  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
8826  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8827  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
8828  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8829  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
8830  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8831  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
8832  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8833  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
8834  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8835  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
8836  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8837  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
8838  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8839  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
8840  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8841  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
8842  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8843  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
8844  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8845  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
8846  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8847  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
8848  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8849  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
8850  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8851  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
8852  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8853  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
8854  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8855  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
8856  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8857  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
8858  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8859  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
8860  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8861  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
8862  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8863  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
8864  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8865  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
8866  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8867  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
8868  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8869  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
8870  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8871  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
8872  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8873  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
8874  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8875  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
8876  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8877  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
8878  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8879  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
8880  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8881  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
8882  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8883  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
8884  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8885  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
8886  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
8887  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
8888  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
8889  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
8890  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
8891  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
8892  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
8893  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
8894  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
8895  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
8896  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
8897  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
8898  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
8899  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
8900  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
8901  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
8902  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
8903  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
8904  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
8905  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
8906  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
8907  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
8908  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
8909  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
8910  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
8911  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
8912  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
8913  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
8914  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
8915  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
8916  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
8917  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
8918  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
8919  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
8920  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
8921  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
8922  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
8923  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
8924  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
8925  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
8926  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
8927  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
8928  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
8929  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
8930  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
8931  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
8932  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
8933  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
8934  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
8935  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
8936  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
8937  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
8938  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
8939  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
8940  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
8941  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
8942  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
8943  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
8944  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
8945  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
8946  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
8947  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
8948  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
8949  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
8950  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
8951  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
8952  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
8953  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
8954 };
8955 
8961 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8962 {
8963  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8964  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
8965  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8966  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
8967  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8968  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
8969  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8970  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
8971  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8972  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
8973  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8974  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
8975  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8976  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
8977  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8978  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
8979  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8980  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
8981  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8982  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
8983  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8984  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
8985  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8986  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
8987  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8988  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
8989  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8990  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
8991  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8992  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
8993  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8994  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
8995  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8996  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
8997  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8998  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
8999  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9000  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
9001  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9002  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
9003  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9004  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
9005  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9006  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
9007  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9008  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
9009  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9010  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
9011  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9012  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
9013  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9014  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
9015  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9016  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
9017  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9018  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
9019  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9020  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
9021  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9022  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
9023  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9024  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
9025  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9026  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
9027  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9028  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
9029  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9030  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
9031  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9032  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
9033 };
9034 
9040 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9041 {
9042  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9043  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_WIDTH },
9044  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9045  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_WIDTH },
9046  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9047  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_WIDTH },
9048  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9049  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_WIDTH },
9050  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9051  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_WIDTH },
9052  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9053  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_WIDTH },
9054  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9055  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_WIDTH },
9056  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9057  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_WIDTH },
9058  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9059  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_WIDTH },
9060  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9061  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_WIDTH },
9062  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9063  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_WIDTH },
9064  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9065  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_WIDTH },
9066  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9067  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_WIDTH },
9068  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9069  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_WIDTH },
9070  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9071  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_WIDTH },
9072  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9073  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_WIDTH },
9074  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9075  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_WIDTH },
9076  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9077  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_WIDTH },
9078  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9079  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_WIDTH },
9080  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9081  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_WIDTH },
9082  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9083  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_WIDTH },
9084  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9085  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_WIDTH },
9086  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9087  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_WIDTH },
9088  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9089  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_WIDTH },
9090  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9091  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_WIDTH },
9092  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9093  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_WIDTH },
9094  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9095  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_WIDTH },
9096  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9097  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_WIDTH },
9098  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9099  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_WIDTH },
9100  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9101  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_WIDTH },
9102  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9103  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_WIDTH },
9104  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9105  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_WIDTH },
9106  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9107  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_WIDTH },
9108  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9109  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_WIDTH },
9110  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9111  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_WIDTH },
9112 };
9113 
9119 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9120 {
9121  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9122  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
9123  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9124  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
9125  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9126  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
9127  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9128  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
9129  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9130  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
9131  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9132  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
9133  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9134  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
9135  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9136  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
9137  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9138  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
9139  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9140  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
9141  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9142  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
9143  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9144  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
9145  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9146  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
9147  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9148  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
9149  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9150  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
9151  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9152  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
9153  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9154  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
9155  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9156  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
9157  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9158  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
9159  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9160  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
9161  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9162  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
9163  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9164  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
9165  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9166  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
9167  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9168  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
9169  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9170  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
9171  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9172  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
9173  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9174  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
9175  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9176  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
9177  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9178  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
9179  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9180  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
9181  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9182  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
9183  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9184  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
9185  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9186  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
9187  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9188  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
9189  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9190  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
9191 };
9192 
9198 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9199 {
9200  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9201  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
9202  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9203  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
9204 };
9205 
9211 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9212 {
9213  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9214  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
9215  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9216  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
9217 };
9218 
9224 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9225 {
9226  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
9228  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9229  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
9230 };
9231 
9237 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9238 {
9239  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9240  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
9241  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9242  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
9243  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9244  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
9245  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9246  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
9247  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9248  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
9249  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9250  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
9251  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9252  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
9253  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9254  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
9255  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9256  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
9257  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9258  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
9259  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9260  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
9261  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9262  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
9263  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9264  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
9265  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9266  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
9267  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9268  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
9269  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9270  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
9271  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9272  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
9273  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9274  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
9275  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9276  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
9277  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9278  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
9279  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9280  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
9281  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9282  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
9283  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9284  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
9285  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9286  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
9287  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9288  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
9289  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9290  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
9291  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9292  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
9293  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9294  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
9295  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9296  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
9297  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9298  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
9299  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9300  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
9301  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9302  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
9303  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9304  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
9305  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9306  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
9307  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9308  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
9309 };
9310 
9316 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9317 {
9318  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
9320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
9322  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
9324 };
9325 
9331 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9332 {
9333  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9334  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9335  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9336  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9337  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9338  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9339  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9340  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9341  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9342  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9343  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9344  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9345  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9346  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9347  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9348  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9349  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9350  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9351  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9352  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9353  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9354  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
9355  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9356  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
9357  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9358  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
9359  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9360  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
9361  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9362  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
9363  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9364  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
9365  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9366  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
9367  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9368  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
9369  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9370  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
9371  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9372  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
9373  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9374  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
9375  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9376  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
9377  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9378  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
9379  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9380  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
9381  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9382  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
9383  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9384  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
9385  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9386  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
9387  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9388  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
9389  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9390  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
9391  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9392  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
9393  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9394  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
9395  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9396  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
9397  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9398  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
9399  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9400  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
9401  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9402  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
9403  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9404  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
9405  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9406  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
9407  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9408  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
9409  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9410  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
9411  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9412  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
9413  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9414  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
9415  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9416  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
9417  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9418  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
9419  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9420  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
9421  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9422  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
9423  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9424  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
9425  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9426  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
9427  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9428  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
9429  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9430  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
9431  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9432  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
9433  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9434  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
9435  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9436  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
9437  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9438  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
9439  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9440  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
9441  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9442  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
9443  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9444  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
9445  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9446  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
9447  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9448  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
9449  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9450  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
9451  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9452  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
9453  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9454  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
9455  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9456  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
9457  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9458  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
9459  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9460  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
9461  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9462  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
9463  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9464  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
9465  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9466  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
9467  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9468  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
9469  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9470  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
9471  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9472  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
9473  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9474  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
9475  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9476  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
9477  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9478  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
9479  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9480  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
9481  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9482  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
9483  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9484  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
9485  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9486  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
9487  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9488  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
9489  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
9491  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9492  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
9493  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9494  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
9495  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9496  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
9497  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9498  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
9499  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9500  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
9501  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9502  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
9503  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9504  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
9505  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9506  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
9507  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9508  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
9509  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9510  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
9511  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9512  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
9513  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9514  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
9515  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9516  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
9517  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9518  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
9519  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9520  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
9521  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9522  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
9523  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9524  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
9525  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9526  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
9527  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9528  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
9529  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9530  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
9531  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9532  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
9533  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9534  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
9535  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
9536  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
9537  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
9538  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
9539  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
9540  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
9541  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
9542  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
9543  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
9544  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
9545 };
9546 
9552 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9553 {
9554  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9556  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9557  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9558  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9559  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9560  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9561  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9562  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9563  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9564  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9565  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9566  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9567  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9568  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9569  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9570  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9571  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9572  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9573  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9574  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9575  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
9576  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9577  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
9578  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9579  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
9580  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9581  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
9582  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9583  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
9584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
9586  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
9588  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9589  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
9590  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9591  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
9592  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
9594  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
9596  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9597  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
9598  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9599  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
9600  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9601  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
9602  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9603  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
9604  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9605  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
9606  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9607  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
9608  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9609  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
9610  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9611  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
9612  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9613  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
9614  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9615  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
9616  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9617  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
9618  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9619  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
9620  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9621  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
9622  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9623  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
9624  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9625  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
9626  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
9628  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9629  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
9630  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9631  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
9632  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9633  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
9634  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9635  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
9636  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9637  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
9638  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9639  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
9640  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9641  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
9642  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9643  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
9644  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9645  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
9646  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9647  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
9648  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9649  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
9650  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9651  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
9652  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9653  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
9654  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9655  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
9656  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9657  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
9658  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9659  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
9660  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9661  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
9662  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9663  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
9664  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9665  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
9666  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9667  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
9668  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9669  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
9670  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9671  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
9672  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9673  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
9674  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9675  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
9676  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9677  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
9678  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9679  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
9680  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9681  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
9682  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9683  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
9684  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9685  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
9686  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9687  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
9688  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9689  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
9690  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9691  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
9692  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9693  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
9694  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9695  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
9696  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9697  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
9698  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9699  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
9700  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9701  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
9702  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9703  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
9704  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9705  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
9706  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9707  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
9708  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9709  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
9710  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9711  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
9712  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9713  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
9714  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9715  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
9716  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9717  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
9718  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9719  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
9720  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9721  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
9722  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9723  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
9724  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9725  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
9726  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9727  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
9728  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9729  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
9730  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9731  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
9732  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9733  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
9734  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9735  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
9736  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9737  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
9738  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9739  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
9740  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9741  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
9742  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9743  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
9744  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9745  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
9746  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9747  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
9748  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9749  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
9750  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9751  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
9752  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9753  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
9754  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9755  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
9756  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
9757  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
9758  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
9759  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
9760 };
9761 
9767 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9768 {
9769  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9773  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9775  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9776  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9777  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9779  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9783  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9785  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9786  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
9791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
9793  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
9795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
9797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
9799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
9801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
9803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
9805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
9807  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
9809  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
9811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
9813  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
9815  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9816  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
9817  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
9819  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
9821  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9822  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
9823  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9824  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
9825  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9826  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
9827  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9828  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
9829  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9830  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
9831  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9832  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
9833  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9834  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
9835  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9836  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
9837  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9838  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
9839  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9840  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
9841  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9842  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
9843  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9844  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
9845  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9846  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
9847  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9848  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
9849  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9850  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
9851  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9852  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
9853  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9854  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
9855  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9856  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
9857  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9858  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
9859  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9860  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
9861  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9862  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
9863  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9864  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
9865  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9866  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
9867  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9868  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
9869  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9870  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
9871  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9872  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
9873  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9874  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
9875  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9876  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
9877  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9878  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
9879  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9880  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
9881  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9882  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
9883  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9884  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
9885  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9886  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
9887  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9888  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
9889  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9890  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
9891  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9892  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
9893  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9894  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
9895  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9896  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
9897  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9898  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
9899  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9900  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
9901  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9902  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
9903  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9904  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
9905  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9906  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
9907  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9908  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
9909  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9910  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
9911  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9912  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
9913  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9914  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
9915  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9916  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
9917  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9918  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
9919  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9920  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
9921  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9922  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
9923  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9924  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
9925  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9926  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
9927  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9928  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
9929  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9930  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
9931  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9932  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
9933  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9934  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
9935  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9936  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
9937  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9938  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
9939  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9940  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
9941  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9942  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
9943  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9944  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
9945  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9946  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
9947  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9948  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
9949  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9950  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
9951  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9952  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
9953  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9954  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
9955  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9956  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
9957  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9958  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
9959  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9960  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
9961  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9962  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
9963  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9964  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
9965  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9966  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
9967  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9968  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
9969  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9970  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
9971  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
9972  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
9973  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
9974  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
9975  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
9976  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
9977  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
9978  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
9979  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
9980  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
9981  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
9982  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
9983  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
9984  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
9985  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
9986  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
9987  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
9988  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
9989  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
9990  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
9991  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
9992  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
9993  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
9994  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
9995  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
9996  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
9997  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
9998  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
9999  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
10000  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
10001  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
10002  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
10003  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
10004  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
10005  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
10006  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
10007  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
10008  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
10009  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
10010  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
10011  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
10012  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
10013  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
10014  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
10015  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
10016  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
10017  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
10018  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
10019  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
10020  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
10021  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
10022  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
10023  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
10024  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
10025  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
10026  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
10027  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
10028  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
10029  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
10030  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
10031 };
10032 
10038 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10039 {
10040  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10041  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
10042  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10043  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
10044  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10045  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
10046  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10047  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
10048  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10049  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
10050  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10051  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
10052  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10053  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
10054  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10055  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
10056  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10057  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
10058  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10059  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
10060 };
10061 
10067 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10068 {
10069  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10070  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
10071  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10072  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
10073  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10074  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
10075  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10076  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
10077  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10078  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
10079  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10080  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
10081  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10082  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
10083 };
10084 
10090 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10091 {
10092  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10093  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
10094  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10095  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
10096  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10097  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
10098  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10099  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
10100  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10101  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
10102  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10103  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
10104  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10105  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
10106  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10107  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
10108  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10109  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
10110  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10111  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
10112  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10113  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
10114  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10115  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
10116  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10117  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
10118  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10119  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
10120  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10121  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
10122  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10123  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
10124  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10125  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
10126  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10127  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
10128  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10129  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
10130  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10131  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
10132  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10133  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
10134  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10135  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
10136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
10138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
10140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
10142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
10144  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10145  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
10146  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10147  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
10148  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10149  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
10150  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10151  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
10152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
10154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
10156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
10158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
10160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
10162  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10163  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
10164  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10165  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
10166  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10167  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
10168  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10169  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
10170  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10171  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
10172  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10173  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
10174  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10175  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
10176  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10177  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
10178  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10179  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
10180  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10181  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
10182  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10183  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
10184  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10185  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
10186  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10187  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
10188  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10189  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
10190  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10191  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
10192  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10193  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
10194  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10195  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
10196  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10197  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
10198  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10199  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
10200  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10201  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
10202  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10203  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
10204  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10205  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
10206  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10207  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
10208  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10209  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
10210  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10211  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
10212  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10213  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
10214  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10215  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
10216  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
10217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
10218  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
10219  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
10220  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
10221  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
10222  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
10223  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
10224  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
10225  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
10226  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
10227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
10228  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
10229  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
10230  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
10231  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
10232  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
10233  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
10234  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
10235  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
10236  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
10237  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
10238  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
10239  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
10240  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
10241  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
10242  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
10243  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
10244  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
10245  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
10246  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
10247  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
10248  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
10249  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
10250  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
10251  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
10252  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
10253  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
10254  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
10255  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
10256  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
10257  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
10258  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
10259  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
10260  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
10261  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
10262  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
10263  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
10264  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
10265  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
10266  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
10267  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
10268  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
10269  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
10270  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
10271  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
10272  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
10273  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
10274 };
10275 
10281 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10282 {
10283  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10284  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
10285  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10286  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
10287  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10288  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
10289  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10290  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
10291  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10292  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
10293  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10294  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
10295  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10296  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
10297  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10298  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
10299  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10300  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
10301  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10302  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
10303  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10304  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
10305  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10306  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
10307  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10308  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
10309  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10310  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
10311  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10312  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
10313  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10314  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
10315  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10316  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
10317  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10318  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
10319  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10320  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
10321  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10322  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
10323  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10324  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
10325  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10326  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
10327  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10328  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
10329  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10330  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
10331  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10332  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
10333  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10334  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
10335  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10336  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
10337  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10338  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
10339  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10340  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
10341  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10342  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
10343  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10344  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
10345  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10346  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
10347  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10348  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_WIDTH },
10349  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10350  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_WIDTH },
10351  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10352  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_WIDTH },
10353  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10354  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_WIDTH },
10355  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10356  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_WIDTH },
10357  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10358  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_WIDTH },
10359  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10360  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_WIDTH },
10361  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10362  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_WIDTH },
10363  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10364  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_WIDTH },
10365  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10366  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_WIDTH },
10367  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10368  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_WIDTH },
10369  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10370  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_WIDTH },
10371  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10372  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_WIDTH },
10373  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10374  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_WIDTH },
10375  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10376  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_WIDTH },
10377  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10378  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_WIDTH },
10379  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10380  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_WIDTH },
10381  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10382  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_WIDTH },
10383  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10384  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_WIDTH },
10385  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10386  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_WIDTH },
10387  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10388  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_WIDTH },
10389  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10390  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_WIDTH },
10391  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10392  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_WIDTH },
10393  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10394  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_WIDTH },
10395  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10396  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_WIDTH },
10397  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10398  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_WIDTH },
10399  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10400  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_WIDTH },
10401  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10402  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_WIDTH },
10403  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10404  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_WIDTH },
10405  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10406  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_WIDTH },
10407 };
10408 
10414 {
10415  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_ID, 0u,
10416  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_SIZE, 4u,
10417  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_ROW_WIDTH, ((bool)false) },
10418  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_ID, 0u,
10419  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_SIZE, 4u,
10420  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_ROW_WIDTH, ((bool)false) },
10421  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_ID, 0u,
10422  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_SIZE, 4u,
10423  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_ROW_WIDTH, ((bool)false) },
10424  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_ID, 0u,
10425  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
10426  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
10427  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_ID, 0u,
10428  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
10429  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
10430  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_ID, 0u,
10431  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_SIZE, 4u,
10432  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_ROW_WIDTH, ((bool)false) },
10433  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_ID, 0u,
10434  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
10435  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
10436  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_ID, 0u,
10437  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
10438  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
10439  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_ID, 0u,
10440  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_SIZE, 4u,
10441  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_ROW_WIDTH, ((bool)false) },
10442  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_ID, 0u,
10443  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_SIZE, 4u,
10444  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_ROW_WIDTH, ((bool)false) },
10445  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_ID, 0u,
10446  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_SIZE, 4u,
10447  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_ROW_WIDTH, ((bool)false) },
10448  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_ID, 0u,
10449  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_SIZE, 4u,
10450  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_ROW_WIDTH, ((bool)false) },
10451 };
10452 
10458 {
10459  { SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_MSRAM8KX256E_MSRAM0_ECC0_RAM_ID, 0u,
10460  SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_MSRAM8KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
10461  SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_MSRAM8KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)false) },
10462 };
10463 
10469 {
10470  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
10471  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
10472  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
10473  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_RAM_ID, 0u,
10474  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_RAM_SIZE, 4u,
10475  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_ROW_WIDTH, ((bool)false) },
10476 };
10477 
10483 static const SDL_GrpChkConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_groupEntries[SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10484 {
10485  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10486  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_GROUP_0_WIDTH },
10487  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10488  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_GROUP_1_WIDTH },
10489  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10490  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_GROUP_2_WIDTH },
10491  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10492  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_GROUP_3_WIDTH },
10493 };
10494 
10500 {
10501  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
10502  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
10503  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
10504  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
10505  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
10506  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
10507 };
10508 
10514 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
10515 {
10516  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
10517  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
10518  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
10519  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
10520  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
10521  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
10522  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
10523  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
10524  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
10525  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
10526  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
10527  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
10528  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
10529  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
10530  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
10531  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
10532  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
10533  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
10534  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
10535  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
10536  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
10537  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
10538  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
10539  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
10540  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
10541  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
10542  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
10543  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
10544  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
10545  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
10546  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
10547  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
10548  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
10549  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
10550  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
10551  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
10552  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
10553  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
10554  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
10555  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
10556  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
10557  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
10558  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
10559  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
10560  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
10561  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
10562  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
10563  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
10564  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
10565  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
10566  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
10567  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
10568  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
10569  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
10570  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
10571  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
10572  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
10573  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
10574  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
10575  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
10576  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
10577  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
10578  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
10579  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
10580  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
10581  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
10582  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
10583  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
10584  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
10585  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
10586  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
10587  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
10588  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
10589  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
10590  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
10591  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
10592  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
10593  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
10594  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
10595  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
10596  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
10597  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
10598  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
10599  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
10600  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
10601  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
10602  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
10603  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
10604  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
10605  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
10606  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
10607  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
10608  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
10609  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
10610  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
10611  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
10612  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
10613  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
10614  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
10615  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
10616  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
10617  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
10618  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
10619  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
10620  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
10621  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
10622  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
10623  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
10624  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
10625  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
10626  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
10627  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
10628  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
10629  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
10630  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
10631  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
10632  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
10633  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
10634  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
10635  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
10636  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
10637  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
10638  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
10639  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
10640  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
10641  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
10642  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
10643  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
10644  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
10645  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
10646  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
10647  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
10648  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
10649  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
10650  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
10651  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
10652  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
10653  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
10654  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
10655  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
10656  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
10657  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
10658  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
10659  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
10660  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
10661  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
10662  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
10663  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
10664  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
10665  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
10666  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
10667  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
10668  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
10669  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
10670  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
10671  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
10672 };
10673 
10679 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
10680 {
10681  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
10682  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
10683  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
10684  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
10685  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
10686  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
10687  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
10688  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
10689  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
10690  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
10691  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
10692  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
10693  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
10694  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
10695  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
10696  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
10697  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
10698  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
10699  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
10700  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
10701  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
10702  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
10703  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
10704  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
10705  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
10706  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
10707  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
10708  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
10709  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
10710  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
10711  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
10712  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
10713  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
10714  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
10715  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
10716  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
10717  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
10718  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
10719  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
10720  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
10721  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
10722  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
10723  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
10724  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
10725  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
10726  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
10727  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
10728  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
10729  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
10730  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
10731  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
10732  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
10733  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
10734  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
10735  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
10736  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
10737  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
10738  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
10739  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
10740  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
10741  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
10742  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
10743  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
10744  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
10745  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
10746  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
10747  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
10748  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
10749  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
10750  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
10751  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
10752  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
10753  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
10754  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
10755  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
10756  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
10757  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
10758  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
10759  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
10760  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
10761  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
10762  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
10763  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
10764  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
10765  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
10766  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
10767  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
10768  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
10769  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
10770  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
10771  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
10772  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
10773  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
10774  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
10775  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
10776  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
10777  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
10778  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
10779  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
10780  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
10781  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
10782  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
10783  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
10784  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
10785  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
10786  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
10787  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
10788  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
10789  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
10790  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
10791  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
10792  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
10793  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
10794  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
10795  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
10796  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
10797  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
10798  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
10799  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
10800  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
10801  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
10802  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
10803  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
10804  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
10805  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
10806  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
10807  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
10808  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
10809  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
10810  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
10811  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
10812  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
10813  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
10814  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
10815  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
10816  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
10817  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
10818  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
10819  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
10820  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
10821  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
10822  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
10823  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
10824  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
10825  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
10826  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
10827  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
10828  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
10829  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
10830  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
10831  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
10832  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
10833  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
10834  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
10835  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
10836  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
10837  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
10838  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
10839  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
10840  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
10841  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
10842  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
10843 };
10844 
10850 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
10851 {
10852  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
10853  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
10854  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
10855  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
10856  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
10857  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
10858  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
10859  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
10860  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
10861  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
10862  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
10863  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
10864  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
10865  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
10866  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
10867  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
10868  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
10869  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
10870  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
10871  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
10872  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
10873  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
10874  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
10875  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
10876  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
10877  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
10878  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
10879  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
10880  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
10881  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
10882  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
10883  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
10884  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
10885  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
10886 };
10887 
10893 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
10894 {
10895  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
10896  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_WIDTH },
10897  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
10898  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_WIDTH },
10899  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
10900  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_WIDTH },
10901  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
10902  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_3_WIDTH },
10903  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
10904  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_4_WIDTH },
10905  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
10906  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_5_WIDTH },
10907  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
10908  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_6_WIDTH },
10909  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
10910  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_7_WIDTH },
10911  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
10912  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_8_WIDTH },
10913  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
10914  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_9_WIDTH },
10915  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
10916  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_10_WIDTH },
10917  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
10918  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_11_WIDTH },
10919  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
10920  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_12_WIDTH },
10921 };
10922 
10928 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
10929 {
10930  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
10931  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
10932  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
10933  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
10934  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
10935  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
10936  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
10937  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
10938  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
10939  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
10940  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
10941  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
10942  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
10943  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
10944  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
10945  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
10946  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
10947  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
10948  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
10949  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
10950  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
10951  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
10952  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
10953  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
10954  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
10955  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
10956  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
10957  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
10958  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
10959  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
10960  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
10961  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
10962  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
10963  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
10964 };
10965 
10971 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
10972 {
10973  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
10974  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
10975  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
10976  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
10977  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
10978  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
10979  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
10980  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
10981  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
10982  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
10983  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
10984  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
10985  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
10986  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
10987 };
10988 
10994 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
10995 {
10996  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
10997  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
10998  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
10999  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
11000  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
11001  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
11002  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
11003  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
11004  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
11005  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
11006  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
11007  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
11008  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
11009  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
11010  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
11011  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
11012  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
11013  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
11014  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
11015  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
11016  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
11017  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
11018  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
11019  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
11020  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
11021  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
11022  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
11023  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
11024  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
11025  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
11026  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
11027  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
11028  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
11029  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
11030  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
11031  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
11032  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
11033  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
11034  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
11035  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
11036  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
11037  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
11038  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
11039  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
11040  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
11041  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
11042  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
11043  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
11044  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
11045  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
11046  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
11047  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
11048  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
11049  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
11050  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
11051  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
11052  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
11053  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
11054  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
11055  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
11056  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
11057  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
11058  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
11059  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
11060  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
11061  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
11062  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
11063  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
11064  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
11065  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
11066  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
11067  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
11068  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
11069  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
11070  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
11071  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
11072  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
11073  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
11074  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
11075  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
11076  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
11077  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
11078  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
11079  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
11080  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
11081  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
11082  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
11083  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
11084  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
11085  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
11086  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
11087  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
11088  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
11089  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
11090  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
11091  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
11092  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
11093  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
11094  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
11095  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
11096  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
11097  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
11098  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
11099  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
11100  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
11101  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
11102  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
11103  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
11104  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
11105  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
11106  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
11107  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
11108  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
11109  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
11110  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
11111  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
11112  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
11113  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
11114  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
11115  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
11116  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
11117  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
11118  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
11119  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
11120  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
11121  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
11122  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
11123  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
11124  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
11125  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
11126  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
11127  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
11128  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
11129  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
11130  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
11131  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
11132  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
11133  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
11134  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
11135  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
11136 };
11137 
11143 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
11144 {
11145  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
11146  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
11147  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
11148  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
11149  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
11150  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
11151  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
11152  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
11153  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
11154  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
11155  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
11156  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
11157  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
11158  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
11159  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
11160  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
11161  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
11162  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
11163  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
11164  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
11165  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
11166  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
11167  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
11168  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
11169  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
11170  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
11171  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
11172  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
11173  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
11174  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
11175  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
11176  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
11177  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
11178  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
11179  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
11180  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
11181  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
11182  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
11183  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
11184  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
11185  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
11186  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
11187  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
11188  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
11189  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
11190  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
11191  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
11192  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
11193  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
11194  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
11195  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
11196  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
11197  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
11198  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
11199  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
11200  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
11201  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
11202  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
11203  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
11204  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
11205  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
11206  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
11207  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
11208  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
11209  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
11210  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
11211  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
11212  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
11213  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
11214  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
11215  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
11216  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
11217  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
11218  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
11219  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
11220  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
11221  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
11222  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
11223  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
11224  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
11225  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
11226  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
11227  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
11228  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
11229  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
11230  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
11231  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
11232  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
11233  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
11234  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
11235  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
11236  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
11237  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
11238  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
11239  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
11240  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
11241  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
11242  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
11243  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
11244  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
11245  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
11246  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
11247  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
11248  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
11249  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
11250  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
11251  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
11252  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
11253  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
11254  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
11255  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
11256  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
11257  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
11258  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
11259  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
11260  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
11261  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
11262  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
11263  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
11264  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
11265  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
11266  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
11267  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
11268  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
11269  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
11270  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
11271  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
11272  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
11273  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
11274  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
11275  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
11276  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
11277  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
11278  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
11279  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
11280  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
11281 };
11282 
11288 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS] =
11289 {
11290  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_CHECKER_TYPE,
11291  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_WIDTH },
11292  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_CHECKER_TYPE,
11293  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_WIDTH },
11294  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_CHECKER_TYPE,
11295  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_WIDTH },
11296  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_CHECKER_TYPE,
11297  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_WIDTH },
11298  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_CHECKER_TYPE,
11299  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_WIDTH },
11300  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_CHECKER_TYPE,
11301  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_WIDTH },
11302  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_CHECKER_TYPE,
11303  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_WIDTH },
11304  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_CHECKER_TYPE,
11305  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_WIDTH },
11306  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_CHECKER_TYPE,
11307  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_WIDTH },
11308  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_CHECKER_TYPE,
11309  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_WIDTH },
11310  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_CHECKER_TYPE,
11311  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_WIDTH },
11312  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_CHECKER_TYPE,
11313  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_WIDTH },
11314  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_CHECKER_TYPE,
11315  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_WIDTH },
11316  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_CHECKER_TYPE,
11317  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_WIDTH },
11318  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_CHECKER_TYPE,
11319  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_WIDTH },
11320  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_CHECKER_TYPE,
11321  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_WIDTH },
11322  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_CHECKER_TYPE,
11323  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_WIDTH },
11324  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_CHECKER_TYPE,
11325  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_WIDTH },
11326  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_CHECKER_TYPE,
11327  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_WIDTH },
11328  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_CHECKER_TYPE,
11329  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_WIDTH },
11330  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_CHECKER_TYPE,
11331  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_WIDTH },
11332  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_CHECKER_TYPE,
11333  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_WIDTH },
11334  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_CHECKER_TYPE,
11335  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_WIDTH },
11336  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_CHECKER_TYPE,
11337  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_WIDTH },
11338  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_CHECKER_TYPE,
11339  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_WIDTH },
11340  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_CHECKER_TYPE,
11341  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_WIDTH },
11342  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_26_CHECKER_TYPE,
11343  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_26_WIDTH },
11344  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_27_CHECKER_TYPE,
11345  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_27_WIDTH },
11346  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_28_CHECKER_TYPE,
11347  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_28_WIDTH },
11348  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_29_CHECKER_TYPE,
11349  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_29_WIDTH },
11350  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_30_CHECKER_TYPE,
11351  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_30_WIDTH },
11352  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_31_CHECKER_TYPE,
11353  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_31_WIDTH },
11354  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_32_CHECKER_TYPE,
11355  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_32_WIDTH },
11356  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_33_CHECKER_TYPE,
11357  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_33_WIDTH },
11358  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_34_CHECKER_TYPE,
11359  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_34_WIDTH },
11360  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_35_CHECKER_TYPE,
11361  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_35_WIDTH },
11362  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_36_CHECKER_TYPE,
11363  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_36_WIDTH },
11364  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_37_CHECKER_TYPE,
11365  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_37_WIDTH },
11366  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_38_CHECKER_TYPE,
11367  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_38_WIDTH },
11368  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_39_CHECKER_TYPE,
11369  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_39_WIDTH },
11370  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_40_CHECKER_TYPE,
11371  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_40_WIDTH },
11372  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_41_CHECKER_TYPE,
11373  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_41_WIDTH },
11374  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_42_CHECKER_TYPE,
11375  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_42_WIDTH },
11376  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_43_CHECKER_TYPE,
11377  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_43_WIDTH },
11378  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_44_CHECKER_TYPE,
11379  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_44_WIDTH },
11380  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_45_CHECKER_TYPE,
11381  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_45_WIDTH },
11382  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_46_CHECKER_TYPE,
11383  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_46_WIDTH },
11384  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_47_CHECKER_TYPE,
11385  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_47_WIDTH },
11386  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_48_CHECKER_TYPE,
11387  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_48_WIDTH },
11388  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_49_CHECKER_TYPE,
11389  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_49_WIDTH },
11390  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_50_CHECKER_TYPE,
11391  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_50_WIDTH },
11392  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_51_CHECKER_TYPE,
11393  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_51_WIDTH },
11394  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_52_CHECKER_TYPE,
11395  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_52_WIDTH },
11396  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_53_CHECKER_TYPE,
11397  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_53_WIDTH },
11398  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_54_CHECKER_TYPE,
11399  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_54_WIDTH },
11400  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_55_CHECKER_TYPE,
11401  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_55_WIDTH },
11402  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_56_CHECKER_TYPE,
11403  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_56_WIDTH },
11404  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_57_CHECKER_TYPE,
11405  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_57_WIDTH },
11406  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_58_CHECKER_TYPE,
11407  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_58_WIDTH },
11408  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_59_CHECKER_TYPE,
11409  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_59_WIDTH },
11410  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_60_CHECKER_TYPE,
11411  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_60_WIDTH },
11412  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_61_CHECKER_TYPE,
11413  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_61_WIDTH },
11414  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_62_CHECKER_TYPE,
11415  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_62_WIDTH },
11416  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_63_CHECKER_TYPE,
11417  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_63_WIDTH },
11418  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_64_CHECKER_TYPE,
11419  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_64_WIDTH },
11420  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_65_CHECKER_TYPE,
11421  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_65_WIDTH },
11422  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_66_CHECKER_TYPE,
11423  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_66_WIDTH },
11424  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_67_CHECKER_TYPE,
11425  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_67_WIDTH },
11426  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_68_CHECKER_TYPE,
11427  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_68_WIDTH },
11428  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_69_CHECKER_TYPE,
11429  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_69_WIDTH },
11430  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_70_CHECKER_TYPE,
11431  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_70_WIDTH },
11432  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_71_CHECKER_TYPE,
11433  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_71_WIDTH },
11434  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_72_CHECKER_TYPE,
11435  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_72_WIDTH },
11436  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_73_CHECKER_TYPE,
11437  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_73_WIDTH },
11438  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_74_CHECKER_TYPE,
11439  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_74_WIDTH },
11440  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_75_CHECKER_TYPE,
11441  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_75_WIDTH },
11442  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_76_CHECKER_TYPE,
11443  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_76_WIDTH },
11444  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_77_CHECKER_TYPE,
11445  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_77_WIDTH },
11446 };
11447 
11453 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS] =
11454 {
11455  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_CHECKER_TYPE,
11456  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_WIDTH },
11457  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_CHECKER_TYPE,
11458  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_WIDTH },
11459  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_CHECKER_TYPE,
11460  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_WIDTH },
11461  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_CHECKER_TYPE,
11462  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_WIDTH },
11463  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_CHECKER_TYPE,
11464  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_WIDTH },
11465  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_CHECKER_TYPE,
11466  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_WIDTH },
11467  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_CHECKER_TYPE,
11468  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_WIDTH },
11469  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_CHECKER_TYPE,
11470  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_WIDTH },
11471  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_CHECKER_TYPE,
11472  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_WIDTH },
11473  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_CHECKER_TYPE,
11474  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_WIDTH },
11475  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_CHECKER_TYPE,
11476  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_WIDTH },
11477  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_CHECKER_TYPE,
11478  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_WIDTH },
11479  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_CHECKER_TYPE,
11480  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_WIDTH },
11481  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_CHECKER_TYPE,
11482  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_WIDTH },
11483  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_CHECKER_TYPE,
11484  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_WIDTH },
11485  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_CHECKER_TYPE,
11486  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_WIDTH },
11487  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_CHECKER_TYPE,
11488  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_WIDTH },
11489  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_CHECKER_TYPE,
11490  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_WIDTH },
11491  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_CHECKER_TYPE,
11492  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_WIDTH },
11493  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_CHECKER_TYPE,
11494  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_WIDTH },
11495  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_CHECKER_TYPE,
11496  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_WIDTH },
11497  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_CHECKER_TYPE,
11498  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_WIDTH },
11499  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_22_CHECKER_TYPE,
11500  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_22_WIDTH },
11501  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_23_CHECKER_TYPE,
11502  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_23_WIDTH },
11503  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_24_CHECKER_TYPE,
11504  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_24_WIDTH },
11505  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_25_CHECKER_TYPE,
11506  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_25_WIDTH },
11507  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_26_CHECKER_TYPE,
11508  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_26_WIDTH },
11509  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_27_CHECKER_TYPE,
11510  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_27_WIDTH },
11511  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_28_CHECKER_TYPE,
11512  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_28_WIDTH },
11513  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_29_CHECKER_TYPE,
11514  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_29_WIDTH },
11515  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_30_CHECKER_TYPE,
11516  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_30_WIDTH },
11517  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_31_CHECKER_TYPE,
11518  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_31_WIDTH },
11519  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_32_CHECKER_TYPE,
11520  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_32_WIDTH },
11521 };
11522 
11528 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
11529 {
11530  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
11531  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
11532  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
11533  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
11534  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
11535  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
11536  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
11537  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
11538  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
11539  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
11540  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
11541  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
11542 };
11543 
11549 {
11550  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
11551  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_RAM_SIZE, 4u,
11552  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
11553  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_RAM_ID, 0u,
11554  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_RAM_SIZE, 4u,
11555  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
11556  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
11557  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_RAM_SIZE, 4u,
11558  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
11559  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
11560  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_RAM_SIZE, 4u,
11561  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
11562  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
11563  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_RAM_SIZE, 4u,
11564  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
11565  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
11566  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_RAM_SIZE, 4u,
11567  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
11568  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
11569  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
11570  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
11571  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_RAM_ID, 0u,
11572  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_RAM_SIZE, 4u,
11573  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
11574  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_RAM_ID, 0u,
11575  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_RAM_SIZE, 4u,
11576  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
11577  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
11578  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
11579  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
11580  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_RAM_ID, 0u,
11581  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_RAM_SIZE, 4u,
11582  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
11583  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_RAM_ID, 0u,
11584  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_RAM_SIZE, 4u,
11585  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
11586  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_RAM_ID, 0u,
11587  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_RAM_SIZE, 4u,
11588  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_ROW_WIDTH, ((bool)false) },
11589  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_RAM_ID, 0u,
11590  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_RAM_SIZE, 4u,
11591  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_ROW_WIDTH, ((bool)false) },
11592  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_RAM_ID, 0u,
11593  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_RAM_SIZE, 4u,
11594  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
11595  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_RAM_ID, 0u,
11596  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_RAM_SIZE, 4u,
11597  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
11598  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
11599  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_RAM_SIZE, 4u,
11600  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
11601  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
11602  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_RAM_SIZE, 4u,
11603  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
11604  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
11605  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
11606  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
11607  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_RAM_ID, 0u,
11608  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_RAM_SIZE, 4u,
11609  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
11610  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_RAM_ID, 0u,
11611  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_RAM_SIZE, 4u,
11612  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
11613  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
11614  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
11615  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
11616  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID, 0u,
11617  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_SIZE, 4u,
11618  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ROW_WIDTH, ((bool)false) },
11619  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_ID, 0u,
11620  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_SIZE, 4u,
11621  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_ROW_WIDTH, ((bool)false) },
11622  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
11623  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_RAM_SIZE, 4u,
11624  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)false) },
11625  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
11626  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 4u,
11627  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)false) },
11628  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
11629  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 4u,
11630  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
11631  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
11632  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_RAM_SIZE, 4u,
11633  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)false) },
11634 };
11635 
11641 {
11642  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
11643  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
11644  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)false) },
11645  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
11646  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
11647  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)false) },
11648  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
11649  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
11650  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)false) },
11651  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
11652  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
11653  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)false) },
11654 };
11655 
11661 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
11662 {
11663  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
11664  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_0_WIDTH },
11665  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
11666  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_1_WIDTH },
11667  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
11668  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_2_WIDTH },
11669  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
11670  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_3_WIDTH },
11671  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
11672  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_4_WIDTH },
11673  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
11674  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_5_WIDTH },
11675  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
11676  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_6_WIDTH },
11677  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
11678  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_7_WIDTH },
11679  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
11680  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_8_WIDTH },
11681  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
11682  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_9_WIDTH },
11683  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
11684  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_10_WIDTH },
11685  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
11686  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_11_WIDTH },
11687  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
11688  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_12_WIDTH },
11689  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
11690  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_13_WIDTH },
11691  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
11692  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_14_WIDTH },
11693  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
11694  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_15_WIDTH },
11695  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
11696  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_16_WIDTH },
11697  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
11698  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_17_WIDTH },
11699  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
11700  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_18_WIDTH },
11701  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
11702  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_19_WIDTH },
11703  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
11704  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_20_WIDTH },
11705  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
11706  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_21_WIDTH },
11707  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
11708  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_22_WIDTH },
11709  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
11710  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_23_WIDTH },
11711  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
11712  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_24_WIDTH },
11713  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
11714  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_25_WIDTH },
11715  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
11716  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_26_WIDTH },
11717  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
11718  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_27_WIDTH },
11719  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
11720  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_28_WIDTH },
11721  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
11722  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_29_WIDTH },
11723  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
11724  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_30_WIDTH },
11725  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
11726  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_31_WIDTH },
11727  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
11728  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_32_WIDTH },
11729  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
11730  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_33_WIDTH },
11731  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
11732  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_34_WIDTH },
11733  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
11734  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_35_WIDTH },
11735  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
11736  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_36_WIDTH },
11737  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
11738  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_37_WIDTH },
11739  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
11740  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_38_WIDTH },
11741  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
11742  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_39_WIDTH },
11743  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
11744  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_40_WIDTH },
11745  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
11746  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_41_WIDTH },
11747  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
11748  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_42_WIDTH },
11749  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
11750  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_43_WIDTH },
11751  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
11752  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_44_WIDTH },
11753  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
11754  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_45_WIDTH },
11755  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
11756  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_46_WIDTH },
11757  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
11758  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_47_WIDTH },
11759  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
11760  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_48_WIDTH },
11761  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
11762  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_49_WIDTH },
11763  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
11764  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_50_WIDTH },
11765  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
11766  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_51_WIDTH },
11767  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
11768  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_52_WIDTH },
11769  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
11770  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_53_WIDTH },
11771  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
11772  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_54_WIDTH },
11773  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
11774  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_55_WIDTH },
11775  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
11776  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_56_WIDTH },
11777  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
11778  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_57_WIDTH },
11779  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
11780  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_58_WIDTH },
11781  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
11782  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_59_WIDTH },
11783  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
11784  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_60_WIDTH },
11785  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
11786  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_61_WIDTH },
11787  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
11788  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_62_WIDTH },
11789  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
11790  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_63_WIDTH },
11791  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
11792  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_64_WIDTH },
11793  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_65_CHECKER_TYPE,
11794  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_65_WIDTH },
11795  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_66_CHECKER_TYPE,
11796  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_66_WIDTH },
11797  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_67_CHECKER_TYPE,
11798  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_67_WIDTH },
11799  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_68_CHECKER_TYPE,
11800  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_68_WIDTH },
11801 };
11802 
11808 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS] =
11809 {
11810  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_0_CHECKER_TYPE,
11811  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_0_WIDTH },
11812  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_1_CHECKER_TYPE,
11813  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_1_WIDTH },
11814  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_2_CHECKER_TYPE,
11815  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_2_WIDTH },
11816  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_3_CHECKER_TYPE,
11817  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_3_WIDTH },
11818  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_4_CHECKER_TYPE,
11819  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_4_WIDTH },
11820  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_5_CHECKER_TYPE,
11821  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_5_WIDTH },
11822  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_6_CHECKER_TYPE,
11823  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_6_WIDTH },
11824  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_7_CHECKER_TYPE,
11825  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_7_WIDTH },
11826  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_8_CHECKER_TYPE,
11827  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_8_WIDTH },
11828  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_9_CHECKER_TYPE,
11829  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_9_WIDTH },
11830  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_10_CHECKER_TYPE,
11831  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_10_WIDTH },
11832  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_11_CHECKER_TYPE,
11833  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_11_WIDTH },
11834  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_12_CHECKER_TYPE,
11835  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_12_WIDTH },
11836  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_13_CHECKER_TYPE,
11837  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_13_WIDTH },
11838  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_14_CHECKER_TYPE,
11839  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_14_WIDTH },
11840  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_15_CHECKER_TYPE,
11841  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_15_WIDTH },
11842  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_16_CHECKER_TYPE,
11843  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_16_WIDTH },
11844  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_17_CHECKER_TYPE,
11845  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_17_WIDTH },
11846  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_18_CHECKER_TYPE,
11847  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_18_WIDTH },
11848  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_19_CHECKER_TYPE,
11849  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_19_WIDTH },
11850  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_20_CHECKER_TYPE,
11851  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_20_WIDTH },
11852  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_21_CHECKER_TYPE,
11853  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_21_WIDTH },
11854  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_22_CHECKER_TYPE,
11855  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_22_WIDTH },
11856  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_23_CHECKER_TYPE,
11857  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_23_WIDTH },
11858  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_24_CHECKER_TYPE,
11859  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_24_WIDTH },
11860  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_25_CHECKER_TYPE,
11861  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_25_WIDTH },
11862  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_26_CHECKER_TYPE,
11863  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_26_WIDTH },
11864  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_27_CHECKER_TYPE,
11865  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_27_WIDTH },
11866  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_28_CHECKER_TYPE,
11867  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_28_WIDTH },
11868  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_29_CHECKER_TYPE,
11869  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_29_WIDTH },
11870  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_30_CHECKER_TYPE,
11871  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_30_WIDTH },
11872  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_31_CHECKER_TYPE,
11873  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_31_WIDTH },
11874  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_32_CHECKER_TYPE,
11875  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_32_WIDTH },
11876  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_33_CHECKER_TYPE,
11877  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_33_WIDTH },
11878  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_34_CHECKER_TYPE,
11879  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_34_WIDTH },
11880  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_35_CHECKER_TYPE,
11881  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_35_WIDTH },
11882  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_36_CHECKER_TYPE,
11883  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_36_WIDTH },
11884  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_37_CHECKER_TYPE,
11885  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_37_WIDTH },
11886  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_38_CHECKER_TYPE,
11887  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_38_WIDTH },
11888  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_39_CHECKER_TYPE,
11889  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_39_WIDTH },
11890  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_40_CHECKER_TYPE,
11891  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_40_WIDTH },
11892  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_41_CHECKER_TYPE,
11893  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_41_WIDTH },
11894  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_42_CHECKER_TYPE,
11895  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_42_WIDTH },
11896  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_43_CHECKER_TYPE,
11897  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_43_WIDTH },
11898  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_44_CHECKER_TYPE,
11899  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_44_WIDTH },
11900  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_45_CHECKER_TYPE,
11901  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_45_WIDTH },
11902  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_46_CHECKER_TYPE,
11903  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_46_WIDTH },
11904  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_47_CHECKER_TYPE,
11905  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_47_WIDTH },
11906  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_48_CHECKER_TYPE,
11907  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_48_WIDTH },
11908  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_49_CHECKER_TYPE,
11909  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_49_WIDTH },
11910  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_50_CHECKER_TYPE,
11911  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_50_WIDTH },
11912  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_51_CHECKER_TYPE,
11913  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_51_WIDTH },
11914  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_52_CHECKER_TYPE,
11915  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_52_WIDTH },
11916  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_53_CHECKER_TYPE,
11917  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_53_WIDTH },
11918  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_54_CHECKER_TYPE,
11919  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_54_WIDTH },
11920  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_55_CHECKER_TYPE,
11921  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_55_WIDTH },
11922  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_56_CHECKER_TYPE,
11923  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_56_WIDTH },
11924  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_57_CHECKER_TYPE,
11925  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_57_WIDTH },
11926  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_58_CHECKER_TYPE,
11927  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_58_WIDTH },
11928  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_59_CHECKER_TYPE,
11929  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_59_WIDTH },
11930  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_60_CHECKER_TYPE,
11931  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_60_WIDTH },
11932  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_61_CHECKER_TYPE,
11933  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_61_WIDTH },
11934  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_62_CHECKER_TYPE,
11935  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_62_WIDTH },
11936  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_63_CHECKER_TYPE,
11937  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_63_WIDTH },
11938  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_64_CHECKER_TYPE,
11939  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_64_WIDTH },
11940 };
11941 
11947 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
11948 {
11949  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
11950  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_0_WIDTH },
11951  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
11952  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_1_WIDTH },
11953  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
11954  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_2_WIDTH },
11955  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
11956  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_3_WIDTH },
11957  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
11958  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_4_WIDTH },
11959  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
11960  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_5_WIDTH },
11961  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
11962  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_6_WIDTH },
11963  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
11964  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_7_WIDTH },
11965  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
11966  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_8_WIDTH },
11967  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
11968  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_9_WIDTH },
11969  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
11970  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_10_WIDTH },
11971  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
11972  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_11_WIDTH },
11973  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
11974  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_12_WIDTH },
11975  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
11976  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_13_WIDTH },
11977  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
11978  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_14_WIDTH },
11979  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
11980  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_15_WIDTH },
11981  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
11982  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_16_WIDTH },
11983  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
11984  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_17_WIDTH },
11985  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
11986  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_18_WIDTH },
11987  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
11988  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_19_WIDTH },
11989  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
11990  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_20_WIDTH },
11991  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
11992  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_21_WIDTH },
11993  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
11994  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_22_WIDTH },
11995  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
11996  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_23_WIDTH },
11997  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
11998  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_24_WIDTH },
11999  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
12000  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_25_WIDTH },
12001  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
12002  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_26_WIDTH },
12003  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
12004  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_27_WIDTH },
12005  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
12006  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_28_WIDTH },
12007  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
12008  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_29_WIDTH },
12009  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
12010  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_30_WIDTH },
12011  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
12012  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_31_WIDTH },
12013  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
12014  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_32_WIDTH },
12015  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
12016  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_33_WIDTH },
12017  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
12018  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_34_WIDTH },
12019  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
12020  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_35_WIDTH },
12021  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
12022  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_36_WIDTH },
12023  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
12024  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_37_WIDTH },
12025  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
12026  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_38_WIDTH },
12027  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
12028  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_39_WIDTH },
12029  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
12030  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_40_WIDTH },
12031  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
12032  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_41_WIDTH },
12033  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
12034  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_42_WIDTH },
12035  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
12036  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_43_WIDTH },
12037  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
12038  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_44_WIDTH },
12039  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
12040  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_45_WIDTH },
12041  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
12042  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_46_WIDTH },
12043  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
12044  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_47_WIDTH },
12045  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
12046  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_48_WIDTH },
12047  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
12048  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_49_WIDTH },
12049  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
12050  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_50_WIDTH },
12051  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
12052  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_51_WIDTH },
12053  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
12054  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_52_WIDTH },
12055  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
12056  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_53_WIDTH },
12057  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
12058  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_54_WIDTH },
12059  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
12060  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_55_WIDTH },
12061  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
12062  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_56_WIDTH },
12063  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
12064  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_57_WIDTH },
12065  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
12066  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_58_WIDTH },
12067  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
12068  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_59_WIDTH },
12069  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
12070  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_60_WIDTH },
12071  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
12072  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_61_WIDTH },
12073  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
12074  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_62_WIDTH },
12075  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
12076  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_63_WIDTH },
12077  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
12078  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_64_WIDTH },
12079  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_65_CHECKER_TYPE,
12080  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_65_WIDTH },
12081  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_66_CHECKER_TYPE,
12082  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_66_WIDTH },
12083  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_67_CHECKER_TYPE,
12084  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_67_WIDTH },
12085  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_68_CHECKER_TYPE,
12086  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_68_WIDTH },
12087 };
12088 
12094 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS] =
12095 {
12096  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_0_CHECKER_TYPE,
12097  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_0_WIDTH },
12098  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_1_CHECKER_TYPE,
12099  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_1_WIDTH },
12100  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_2_CHECKER_TYPE,
12101  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_2_WIDTH },
12102  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_3_CHECKER_TYPE,
12103  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_3_WIDTH },
12104 };
12105 
12111 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
12112 {
12113  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
12114  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_0_WIDTH },
12115  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
12116  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_1_WIDTH },
12117  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
12118  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_2_WIDTH },
12119  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
12120  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_3_WIDTH },
12121  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
12122  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_4_WIDTH },
12123  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
12124  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_5_WIDTH },
12125  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
12126  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_6_WIDTH },
12127  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
12128  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_7_WIDTH },
12129  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
12130  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_8_WIDTH },
12131  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
12132  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_9_WIDTH },
12133  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
12134  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_10_WIDTH },
12135  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
12136  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_11_WIDTH },
12137  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
12138  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_12_WIDTH },
12139  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
12140  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_13_WIDTH },
12141  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
12142  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_14_WIDTH },
12143 };
12144 
12150 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS] =
12151 {
12152  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_0_CHECKER_TYPE,
12153  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_0_WIDTH },
12154  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_1_CHECKER_TYPE,
12155  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_1_WIDTH },
12156  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_2_CHECKER_TYPE,
12157  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_2_WIDTH },
12158  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_3_CHECKER_TYPE,
12159  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_3_WIDTH },
12160 };
12161 
12167 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
12168 {
12169  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
12170  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
12171  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
12172  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
12173  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
12174  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
12175  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
12176  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
12177  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
12178  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
12179  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
12180  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
12181 };
12182 
12188 {
12189  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
12190  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
12191  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
12192  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
12193  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 4u,
12194  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
12195 };
12196 
12202 {
12203  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x79100000u,
12204  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4U,
12205  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
12206 };
12207 
12213 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12214 {
12215  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12216  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
12217  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12218  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
12219  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12220  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
12221  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12222  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
12223  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12224  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
12225  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12226  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
12227  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12228  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
12229  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12230  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
12231  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12232  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
12233  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12234  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
12235  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12236  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
12237  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12238  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
12239  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12240  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
12241  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12242  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
12243  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12244  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
12245  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12246  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
12247  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12248  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
12249  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12250  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
12251  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12252  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
12253  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12254  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
12255  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12256  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
12257  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12258  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
12259  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12260  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
12261  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12262  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
12263  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12264  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_WIDTH },
12265  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12266  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_WIDTH },
12267  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12268  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_WIDTH },
12269  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12270  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_WIDTH },
12271  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12272  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_WIDTH },
12273  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12274  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_WIDTH },
12275  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12276  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_WIDTH },
12277  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12278  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_WIDTH },
12279  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12280  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_WIDTH },
12281  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12282  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_WIDTH },
12283  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12284  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_WIDTH },
12285  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
12286  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_WIDTH },
12287  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
12288  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_WIDTH },
12289  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
12290  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_WIDTH },
12291  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
12292  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_WIDTH },
12293  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
12294  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_WIDTH },
12295  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
12296  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_WIDTH },
12297  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
12298  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_WIDTH },
12299  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
12300  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_WIDTH },
12301  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
12302  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_WIDTH },
12303  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
12304  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_WIDTH },
12305  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
12306  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_WIDTH },
12307  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
12308  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_WIDTH },
12309  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
12310  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_WIDTH },
12311  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
12312  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_WIDTH },
12313  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
12314  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_WIDTH },
12315  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
12316  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_WIDTH },
12317  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
12318  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_WIDTH },
12319  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
12320  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_WIDTH },
12321  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
12322  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_WIDTH },
12323  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
12324  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_WIDTH },
12325  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
12326  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_WIDTH },
12327  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
12328  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_WIDTH },
12329  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
12330  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_WIDTH },
12331  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
12332  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_WIDTH },
12333  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
12334  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_WIDTH },
12335  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
12336  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_WIDTH },
12337  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
12338  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_WIDTH },
12339  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
12340  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_WIDTH },
12341  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
12342  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_WIDTH },
12343  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
12344  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_WIDTH },
12345 };
12346 
12352 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
12353 {
12354  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
12355  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
12356  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
12357  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
12358  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
12359  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
12360  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
12361  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
12362  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
12363  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
12364  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
12365  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
12366 };
12367 
12373 {
12374  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
12375  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
12376  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
12377 };
12378 
12384 {
12385  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
12386  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
12387  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
12388 };
12389 
12395 {
12396  { SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
12397  SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
12398  SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
12399 };
12400 
12406 {
12407  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID, 0u,
12408  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_RAM_SIZE, 4u,
12409  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_ROW_WIDTH, ((bool)false) },
12410  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID, 0u,
12411  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_RAM_SIZE, 4u,
12412  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_ROW_WIDTH, ((bool)false) },
12413  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID, 0u,
12414  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_RAM_SIZE, 4u,
12415  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_ROW_WIDTH, ((bool)false) },
12416  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID, 0u,
12417  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_RAM_SIZE, 4u,
12418  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_ROW_WIDTH, ((bool)false) },
12419  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_RAM_ID, 0u,
12420  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_RAM_SIZE, 4u,
12421  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_ROW_WIDTH, ((bool)false) },
12422  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_RAM_ID, 0u,
12423  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_RAM_SIZE, 4u,
12424  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_ROW_WIDTH, ((bool)false) },
12425 };
12426 
12432 {
12433  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_RAM_ID, 0u,
12434  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_RAM_SIZE, 4u,
12435  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_ROW_WIDTH, ((bool)false) },
12436  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_RAM_ID, 0u,
12437  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_RAM_SIZE, 4u,
12438  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_ROW_WIDTH, ((bool)false) },
12439  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_RAM_ID, 0u,
12440  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_RAM_SIZE, 4u,
12441  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_ROW_WIDTH, ((bool)false) },
12442  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_RAM_ID, 0u,
12443  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_RAM_SIZE, 4u,
12444  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_ROW_WIDTH, ((bool)false) },
12445  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_RAM_ID, 0u,
12446  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_RAM_SIZE, 4u,
12447  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_ROW_WIDTH, ((bool)false) },
12448  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_RAM_ID, 0u,
12449  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_RAM_SIZE, 4u,
12450  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_ROW_WIDTH, ((bool)false) },
12451  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_RAM_ID, 0u,
12452  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_RAM_SIZE, 4u,
12453  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_ROW_WIDTH, ((bool)false) },
12454  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_RAM_ID, 0u,
12455  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_RAM_SIZE, 4u,
12456  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_ROW_WIDTH, ((bool)false) },
12457  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_RAM_ID, 0u,
12458  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_RAM_SIZE, 4u,
12459  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_ROW_WIDTH, ((bool)false) },
12460  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_RAM_ID, 0u,
12461  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_RAM_SIZE, 4u,
12462  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_ROW_WIDTH, ((bool)false) },
12463  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_RAM_ID, 0u,
12464  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_RAM_SIZE, 4u,
12465  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_ROW_WIDTH, ((bool)false) },
12466  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_RAM_ID, 0u,
12467  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_RAM_SIZE, 4u,
12468  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_ROW_WIDTH, ((bool)false) },
12469 };
12470 
12476 {
12477  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_RAM_ID, 0u,
12478  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_RAM_SIZE, 4u,
12479  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
12480  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_RAM_ID, 0u,
12481  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_RAM_SIZE, 4u,
12482  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
12483  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_RAM_ID, 0u,
12484  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_RAM_SIZE, 4u,
12485  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
12486  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_RAM_ID, 0u,
12487  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_RAM_SIZE, 4u,
12488  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
12489  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_RAM_ID, 0u,
12490  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_RAM_SIZE, 4u,
12491  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
12492  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_RAM_ID, 0u,
12493  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_RAM_SIZE, 4u,
12494  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
12495  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_RAM_ID, 0u,
12496  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_RAM_SIZE, 4u,
12497  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
12498  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_RAM_ID, 0u,
12499  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_RAM_SIZE, 4u,
12500  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
12501  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_RAM_ID, 0u,
12502  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_RAM_SIZE, 4u,
12503  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
12504  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_RAM_ID, 0u,
12505  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_RAM_SIZE, 4u,
12506  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
12507  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_RAM_ID, 0u,
12508  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_RAM_SIZE, 4u,
12509  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
12510  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_RAM_ID, 0u,
12511  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_RAM_SIZE, 4u,
12512  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
12513  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_RAM_ID, 0u,
12514  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_RAM_SIZE, 4u,
12515  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_ROW_WIDTH, ((bool)false) },
12516  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_RAM_ID, 0u,
12517  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_RAM_SIZE, 4u,
12518  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_ROW_WIDTH, ((bool)false) },
12519  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_RAM_ID, 0u,
12520  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_RAM_SIZE, 4u,
12521  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_ROW_WIDTH, ((bool)false) },
12522  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_RAM_ID, 0u,
12523  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_RAM_SIZE, 4u,
12524  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_ROW_WIDTH, ((bool)false) },
12525  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_RAM_ID, 0u,
12526  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_RAM_SIZE, 4u,
12527  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_ROW_WIDTH, ((bool)false) },
12528  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_RAM_ID, 0u,
12529  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_RAM_SIZE, 4u,
12530  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_ROW_WIDTH, ((bool)false) },
12531  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_RAM_ID, 0u,
12532  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_RAM_SIZE, 4u,
12533  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_ROW_WIDTH, ((bool)false) },
12534  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_RAM_ID, 0u,
12535  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_RAM_SIZE, 4u,
12536  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_ROW_WIDTH, ((bool)false) },
12537  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_RAM_ID, 0u,
12538  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_RAM_SIZE, 4u,
12539  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_ROW_WIDTH, ((bool)false) },
12540  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_RAM_ID, 0u,
12541  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_RAM_SIZE, 4u,
12542  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
12543  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_RAM_ID, 0u,
12544  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_RAM_SIZE, 4u,
12545  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
12546  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_RAM_ID, 0u,
12547  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_RAM_SIZE, 4u,
12548  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
12549  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_RAM_ID, 0u,
12550  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_RAM_SIZE, 4u,
12551  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
12552  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_RAM_ID, 0u,
12553  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_RAM_SIZE, 4u,
12554  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
12555  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_RAM_ID, 0u,
12556  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_RAM_SIZE, 4u,
12557  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
12558  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_RAM_ID, 0u,
12559  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_RAM_SIZE, 4u,
12560  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
12561  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_RAM_ID, 0u,
12562  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_RAM_SIZE, 4u,
12563  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
12564  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_RAM_ID, 0u,
12565  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_RAM_SIZE, 4u,
12566  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
12567  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_RAM_ID, 0u,
12568  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_RAM_SIZE, 4u,
12569  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
12570  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_RAM_ID, 0u,
12571  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_RAM_SIZE, 4u,
12572  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
12573  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_RAM_ID, 0u,
12574  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_RAM_SIZE, 4u,
12575  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
12576  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_RAM_ID, 0u,
12577  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_RAM_SIZE, 4u,
12578  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
12579  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_RAM_ID, 0u,
12580  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_RAM_SIZE, 4u,
12581  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
12582  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_RAM_ID, 0u,
12583  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_RAM_SIZE, 4u,
12584  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_ROW_WIDTH, ((bool)false) },
12585  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_RAM_ID, 0u,
12586  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_RAM_SIZE, 4u,
12587  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_ROW_WIDTH, ((bool)false) },
12588  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_RAM_ID, 0u,
12589  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_RAM_SIZE, 4u,
12590  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_ROW_WIDTH, ((bool)false) },
12591  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_RAM_ID, 0u,
12592  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_RAM_SIZE, 4u,
12593  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_ROW_WIDTH, ((bool)false) },
12594  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_RAM_ID, 0u,
12595  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_RAM_SIZE, 4u,
12596  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_ROW_WIDTH, ((bool)false) },
12597  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_RAM_ID, 0u,
12598  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_RAM_SIZE, 4u,
12599  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_ROW_WIDTH, ((bool)false) },
12600  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_RAM_ID, 0u,
12601  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_RAM_SIZE, 4u,
12602  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_ROW_WIDTH, ((bool)false) },
12603  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_RAM_ID, 0u,
12604  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_RAM_SIZE, 4u,
12605  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_ROW_WIDTH, ((bool)false) },
12606  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_RAM_ID, 0u,
12607  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_RAM_SIZE, 4u,
12608  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_ROW_WIDTH, ((bool)false) },
12609  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_RAM_ID, 0u,
12610  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_RAM_SIZE, 4u,
12611  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_ROW_WIDTH, ((bool)false) },
12612  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_RAM_ID, 0u,
12613  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_RAM_SIZE, 4u,
12614  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_ROW_WIDTH, ((bool)false) },
12615  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_RAM_ID, 0u,
12616  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_RAM_SIZE, 4u,
12617  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_ROW_WIDTH, ((bool)false) },
12618  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_RAM_ID, 0u,
12619  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_RAM_SIZE, 4u,
12620  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_ROW_WIDTH, ((bool)false) },
12621  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_RAM_ID, 0u,
12622  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_RAM_SIZE, 4u,
12623  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_ROW_WIDTH, ((bool)false) },
12624  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_RAM_ID, 0u,
12625  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_RAM_SIZE, 4u,
12626  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_ROW_WIDTH, ((bool)false) },
12627  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_RAM_ID, 0u,
12628  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_RAM_SIZE, 4u,
12629  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_ROW_WIDTH, ((bool)false) },
12630  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_RAM_ID, 0u,
12631  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_RAM_SIZE, 4u,
12632  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_ROW_WIDTH, ((bool)false) },
12633  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_RAM_ID, 0u,
12634  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_RAM_SIZE, 4u,
12635  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_ROW_WIDTH, ((bool)false) },
12636  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_RAM_ID, 0u,
12637  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_RAM_SIZE, 4u,
12638  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_ROW_WIDTH, ((bool)false) },
12639  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_RAM_ID, 0u,
12640  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_RAM_SIZE, 4u,
12641  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_ROW_WIDTH, ((bool)false) },
12642  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_RAM_ID, 0u,
12643  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_RAM_SIZE, 4u,
12644  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_ROW_WIDTH, ((bool)false) },
12645  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_RAM_ID, 0u,
12646  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_RAM_SIZE, 4u,
12647  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_ROW_WIDTH, ((bool)false) },
12648  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_RAM_ID, 0u,
12649  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_RAM_SIZE, 4u,
12650  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_ROW_WIDTH, ((bool)false) },
12651  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_RAM_ID, 0u,
12652  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_RAM_SIZE, 4u,
12653  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_ROW_WIDTH, ((bool)false) },
12654  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_RAM_ID, 0u,
12655  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_RAM_SIZE, 4u,
12656  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_ROW_WIDTH, ((bool)false) },
12657  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_RAM_ID, 0u,
12658  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_RAM_SIZE, 4u,
12659  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_ROW_WIDTH, ((bool)false) },
12660  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_RAM_ID, 0u,
12661  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_RAM_SIZE, 4u,
12662  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_ROW_WIDTH, ((bool)false) },
12663 };
12664 
12670 {
12671  { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID, 0x0041880000u,
12672  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_SIZE, 4u,
12673  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
12674 };
12675 
12681 {
12682  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_RAM_ID, 0u,
12683  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_RAM_SIZE, 4u,
12684  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_ROW_WIDTH, ((bool)false) },
12685 };
12686 
12692 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS] =
12693 {
12694  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_CHECKER_TYPE,
12695  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_WIDTH },
12696  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_CHECKER_TYPE,
12697  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_WIDTH },
12698  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_CHECKER_TYPE,
12699  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_WIDTH },
12700  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_CHECKER_TYPE,
12701  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_WIDTH },
12702 };
12703 
12709 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12710 {
12711  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12712  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_WIDTH },
12713  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12714  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_WIDTH },
12715  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12716  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_WIDTH },
12717 };
12718 
12724 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12725 {
12726  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12727  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_WIDTH },
12728  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12729  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_WIDTH },
12730  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12731  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_WIDTH },
12732  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12733  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_WIDTH },
12734  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12735  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_WIDTH },
12736  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12737  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_WIDTH },
12738  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12739  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_WIDTH },
12740  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12741  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_WIDTH },
12742  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12743  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_WIDTH },
12744  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12745  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_WIDTH },
12746  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12747  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_WIDTH },
12748  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12749  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_WIDTH },
12750  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12751  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_WIDTH },
12752  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12753  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_WIDTH },
12754  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12755  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_WIDTH },
12756  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12757  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_WIDTH },
12758  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12759  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_WIDTH },
12760  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12761  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_WIDTH },
12762  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12763  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_WIDTH },
12764  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12765  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_WIDTH },
12766  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12767  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_WIDTH },
12768  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12769  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_WIDTH },
12770  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12771  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_WIDTH },
12772  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12773  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_WIDTH },
12774  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12775  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_WIDTH },
12776  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12777  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_WIDTH },
12778  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12779  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_WIDTH },
12780  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12781  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_WIDTH },
12782  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12783  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_WIDTH },
12784  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12785  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_WIDTH },
12786  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12787  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_WIDTH },
12788  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12789  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_WIDTH },
12790  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12791  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_WIDTH },
12792  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12793  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_WIDTH },
12794  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12795  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_WIDTH },
12796  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
12797  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_WIDTH },
12798  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
12799  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_WIDTH },
12800  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
12801  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_WIDTH },
12802  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
12803  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_WIDTH },
12804  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
12805  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_WIDTH },
12806  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
12807  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_WIDTH },
12808  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
12809  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_WIDTH },
12810  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
12811  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_WIDTH },
12812  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
12813  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_WIDTH },
12814  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
12815  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_WIDTH },
12816  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
12817  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_WIDTH },
12818  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
12819  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_WIDTH },
12820  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
12821  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_WIDTH },
12822  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
12823  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_WIDTH },
12824  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
12825  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_WIDTH },
12826  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
12827  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_WIDTH },
12828  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
12829  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_WIDTH },
12830  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
12831  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_WIDTH },
12832  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
12833  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_WIDTH },
12834  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
12835  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_WIDTH },
12836  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
12837  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_WIDTH },
12838  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
12839  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_WIDTH },
12840  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
12841  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_WIDTH },
12842  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
12843  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_WIDTH },
12844  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
12845  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_WIDTH },
12846  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
12847  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_WIDTH },
12848  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
12849  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_WIDTH },
12850  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
12851  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_WIDTH },
12852  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
12853  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_WIDTH },
12854  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
12855  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_WIDTH },
12856  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
12857  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_WIDTH },
12858  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
12859  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_WIDTH },
12860  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
12861  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_WIDTH },
12862  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
12863  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_WIDTH },
12864  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
12865  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_WIDTH },
12866  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
12867  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_WIDTH },
12868  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
12869  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_WIDTH },
12870  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
12871  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_WIDTH },
12872  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
12873  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_WIDTH },
12874  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
12875  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_WIDTH },
12876  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
12877  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_WIDTH },
12878  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
12879  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_WIDTH },
12880  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
12881  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_WIDTH },
12882  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
12883  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_WIDTH },
12884  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
12885  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_WIDTH },
12886  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
12887  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_WIDTH },
12888  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
12889  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_WIDTH },
12890  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
12891  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_WIDTH },
12892  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
12893  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_WIDTH },
12894  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
12895  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_WIDTH },
12896  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
12897  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_WIDTH },
12898  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
12899  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_WIDTH },
12900  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
12901  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_WIDTH },
12902  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
12903  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_WIDTH },
12904  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
12905  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_WIDTH },
12906  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
12907  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_WIDTH },
12908  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
12909  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_WIDTH },
12910  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
12911  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_WIDTH },
12912  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
12913  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_WIDTH },
12914  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
12915  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_WIDTH },
12916  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
12917  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_WIDTH },
12918  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
12919  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_WIDTH },
12920  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
12921  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_WIDTH },
12922  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
12923  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_WIDTH },
12924  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
12925  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_WIDTH },
12926  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
12927  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_WIDTH },
12928  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
12929  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_WIDTH },
12930  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
12931  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_WIDTH },
12932  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
12933  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_WIDTH },
12934  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
12935  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_WIDTH },
12936  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
12937  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_WIDTH },
12938  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
12939  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_WIDTH },
12940  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
12941  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_WIDTH },
12942  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
12943  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_WIDTH },
12944  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
12945  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_WIDTH },
12946  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
12947  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_WIDTH },
12948  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
12949  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_WIDTH },
12950  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
12951  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_WIDTH },
12952  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
12953  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_WIDTH },
12954  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
12955  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_WIDTH },
12956  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
12957  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_WIDTH },
12958  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
12959  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_WIDTH },
12960  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
12961  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_WIDTH },
12962  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
12963  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_WIDTH },
12964  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
12965  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_WIDTH },
12966  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
12967  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_WIDTH },
12968  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
12969  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_WIDTH },
12970  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
12971  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_WIDTH },
12972  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
12973  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_WIDTH },
12974  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
12975  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_WIDTH },
12976  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
12977  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_WIDTH },
12978  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
12979  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_WIDTH },
12980  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
12981  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_WIDTH },
12982  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
12983  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_WIDTH },
12984  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
12985  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_WIDTH },
12986  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
12987  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_WIDTH },
12988  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
12989  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_WIDTH },
12990  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
12991  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_WIDTH },
12992  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
12993  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_WIDTH },
12994  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
12995  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_WIDTH },
12996  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
12997  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_WIDTH },
12998  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
12999  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_WIDTH },
13000  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
13001  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_WIDTH },
13002  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
13003  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_WIDTH },
13004  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
13005  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_WIDTH },
13006  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
13007  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_WIDTH },
13008  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
13009  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_WIDTH },
13010  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
13011  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_WIDTH },
13012  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
13013  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_WIDTH },
13014  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
13015  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_WIDTH },
13016  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
13017  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_WIDTH },
13018  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
13019  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_WIDTH },
13020  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
13021  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_WIDTH },
13022  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
13023  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_WIDTH },
13024  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
13025  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_WIDTH },
13026  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
13027  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_WIDTH },
13028  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
13029  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_WIDTH },
13030  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
13031  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_WIDTH },
13032  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
13033  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_WIDTH },
13034  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
13035  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_WIDTH },
13036  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
13037  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_WIDTH },
13038  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
13039  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_WIDTH },
13040  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
13041  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_WIDTH },
13042  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
13043  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_WIDTH },
13044  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
13045  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_WIDTH },
13046  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
13047  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_WIDTH },
13048  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
13049  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_WIDTH },
13050  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
13051  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_WIDTH },
13052  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
13053  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_WIDTH },
13054  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
13055  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_WIDTH },
13056  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
13057  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_WIDTH },
13058  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
13059  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_WIDTH },
13060  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
13061  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_WIDTH },
13062 };
13063 
13069 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13070 {
13071  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13072  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
13073  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13074  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
13075  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13076  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
13077  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13078  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
13079 };
13080 
13086 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13087 {
13088  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13089  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
13090 };
13091 
13097 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13098 {
13099  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13100  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_WIDTH },
13101 };
13102 
13108 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS] =
13109 {
13110  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_CHECKER_TYPE,
13111  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_WIDTH },
13112  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_CHECKER_TYPE,
13113  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_WIDTH },
13114  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_CHECKER_TYPE,
13115  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_WIDTH },
13116  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_CHECKER_TYPE,
13117  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_WIDTH },
13118  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_CHECKER_TYPE,
13119  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_WIDTH },
13120  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_CHECKER_TYPE,
13121  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_WIDTH },
13122  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_CHECKER_TYPE,
13123  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_WIDTH },
13124  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_CHECKER_TYPE,
13125  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_WIDTH },
13126  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_CHECKER_TYPE,
13127  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_WIDTH },
13128  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_CHECKER_TYPE,
13129  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_WIDTH },
13130  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_CHECKER_TYPE,
13131  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_WIDTH },
13132  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_CHECKER_TYPE,
13133  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_WIDTH },
13134  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_CHECKER_TYPE,
13135  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_WIDTH },
13136  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_CHECKER_TYPE,
13137  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_WIDTH },
13138  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_CHECKER_TYPE,
13139  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_WIDTH },
13140  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_CHECKER_TYPE,
13141  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_WIDTH },
13142 };
13143 
13149 {
13150  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
13151  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
13152  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
13153  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
13154  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
13155  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
13156  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
13157  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
13158  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
13159  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
13160  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
13161  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
13162 };
13163 
13169 {
13170  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_RAM_ID, 0u,
13171  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_RAM_SIZE, 4u,
13172  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_ROW_WIDTH, ((bool)false) },
13173 };
13174 
13180 static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS] =
13181 {
13182  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_CHECKER_TYPE,
13183  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_WIDTH },
13184  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_CHECKER_TYPE,
13185  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_WIDTH },
13186  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_CHECKER_TYPE,
13187  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_WIDTH },
13188  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_CHECKER_TYPE,
13189  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_WIDTH },
13190 };
13191 
13197 static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13198 {
13199  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13200  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_WIDTH },
13201  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13202  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_WIDTH },
13203  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13204  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_WIDTH },
13205 };
13206 
13212 static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13213 {
13214  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13215  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_WIDTH },
13216  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13217  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_WIDTH },
13218  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13219  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_WIDTH },
13220  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13221  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_WIDTH },
13222  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13223  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_WIDTH },
13224  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13225  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_WIDTH },
13226  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13227  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_WIDTH },
13228  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13229  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_WIDTH },
13230  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13231  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_WIDTH },
13232  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13233  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_WIDTH },
13234  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13235  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_WIDTH },
13236  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13237  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_WIDTH },
13238  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13239  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_WIDTH },
13240  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13241  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_WIDTH },
13242  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13243  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_WIDTH },
13244  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13245  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_WIDTH },
13246  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13247  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_WIDTH },
13248  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13249  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_WIDTH },
13250  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13251  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_WIDTH },
13252  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13253  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_WIDTH },
13254  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13255  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_WIDTH },
13256  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13257  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_WIDTH },
13258  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13259  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_WIDTH },
13260  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13261  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_WIDTH },
13262  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13263  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_WIDTH },
13264  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13265  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_WIDTH },
13266  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13267  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_WIDTH },
13268  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13269  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_WIDTH },
13270  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13271  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_WIDTH },
13272  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13273  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_WIDTH },
13274  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13275  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_WIDTH },
13276  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13277  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_WIDTH },
13278  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13279  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_WIDTH },
13280  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
13281  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_WIDTH },
13282  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
13283  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_WIDTH },
13284  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
13285  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_WIDTH },
13286  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
13287  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_WIDTH },
13288  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
13289  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_WIDTH },
13290  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
13291  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_WIDTH },
13292  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
13293  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_WIDTH },
13294  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
13295  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_WIDTH },
13296  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
13297  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_WIDTH },
13298  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
13299  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_WIDTH },
13300  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
13301  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_WIDTH },
13302  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
13303  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_WIDTH },
13304  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
13305  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_WIDTH },
13306  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
13307  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_WIDTH },
13308  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
13309  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_WIDTH },
13310  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
13311  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_WIDTH },
13312  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
13313  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_WIDTH },
13314  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
13315  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_WIDTH },
13316  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
13317  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_WIDTH },
13318  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
13319  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_WIDTH },
13320  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
13321  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_WIDTH },
13322  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
13323  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_WIDTH },
13324  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
13325  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_WIDTH },
13326  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
13327  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_WIDTH },
13328  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
13329  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_WIDTH },
13330  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
13331  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_WIDTH },
13332  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
13333  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_WIDTH },
13334  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
13335  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_WIDTH },
13336  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
13337  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_WIDTH },
13338  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
13339  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_WIDTH },
13340  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
13341  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_WIDTH },
13342  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
13343  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_WIDTH },
13344  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
13345  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_WIDTH },
13346  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
13347  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_WIDTH },
13348  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
13349  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_WIDTH },
13350  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
13351  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_WIDTH },
13352  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
13353  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_WIDTH },
13354  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
13355  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_WIDTH },
13356  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
13357  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_WIDTH },
13358  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
13359  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_WIDTH },
13360  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
13361  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_WIDTH },
13362  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
13363  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_WIDTH },
13364  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
13365  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_WIDTH },
13366  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
13367  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_WIDTH },
13368  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
13369  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_WIDTH },
13370  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
13371  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_WIDTH },
13372  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
13373  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_WIDTH },
13374  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
13375  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_WIDTH },
13376  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
13377  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_WIDTH },
13378  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
13379  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_WIDTH },
13380  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
13381  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_WIDTH },
13382  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
13383  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_WIDTH },
13384  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
13385  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_WIDTH },
13386  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
13387  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_WIDTH },
13388  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
13389  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_WIDTH },
13390  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
13391  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_WIDTH },
13392  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
13393  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_WIDTH },
13394  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
13395  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_WIDTH },
13396  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
13397  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_WIDTH },
13398  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
13399  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_WIDTH },
13400  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
13401  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_WIDTH },
13402  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
13403  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_WIDTH },
13404  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
13405  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_WIDTH },
13406  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
13407  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_WIDTH },
13408  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
13409  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_WIDTH },
13410  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
13411  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_WIDTH },
13412  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
13413  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_WIDTH },
13414  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
13415  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_WIDTH },
13416  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
13417  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_WIDTH },
13418  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
13419  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_WIDTH },
13420  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
13421  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_WIDTH },
13422  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
13423  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_WIDTH },
13424  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
13425  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_WIDTH },
13426  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
13427  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_WIDTH },
13428  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
13429  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_WIDTH },
13430  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
13431  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_WIDTH },
13432  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
13433  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_WIDTH },
13434  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
13435  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_WIDTH },
13436  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
13437  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_WIDTH },
13438  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
13439  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_WIDTH },
13440  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
13441  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_WIDTH },
13442  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
13443  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_WIDTH },
13444  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
13445  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_WIDTH },
13446  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
13447  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_WIDTH },
13448  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
13449  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_WIDTH },
13450  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
13451  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_WIDTH },
13452  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
13453  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_WIDTH },
13454  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
13455  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_WIDTH },
13456  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
13457  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_WIDTH },
13458  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
13459  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_WIDTH },
13460  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
13461  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_WIDTH },
13462  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
13463  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_WIDTH },
13464  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
13465  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_WIDTH },
13466  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
13467  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_WIDTH },
13468  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
13469  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_WIDTH },
13470  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
13471  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_WIDTH },
13472  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
13473  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_WIDTH },
13474  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
13475  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_WIDTH },
13476  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
13477  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_WIDTH },
13478  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
13479  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_WIDTH },
13480  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
13481  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_WIDTH },
13482  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
13483  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_WIDTH },
13484  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
13485  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_WIDTH },
13486  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
13487  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_WIDTH },
13488  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
13489  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_WIDTH },
13490  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
13491  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_WIDTH },
13492  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
13493  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_WIDTH },
13494  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
13495  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_WIDTH },
13496  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
13497  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_WIDTH },
13498  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
13499  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_WIDTH },
13500  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
13501  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_WIDTH },
13502  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
13503  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_WIDTH },
13504  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
13505  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_WIDTH },
13506  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
13507  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_WIDTH },
13508  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
13509  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_WIDTH },
13510  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
13511  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_WIDTH },
13512  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
13513  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_WIDTH },
13514  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
13515  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_WIDTH },
13516  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
13517  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_WIDTH },
13518  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
13519  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_WIDTH },
13520  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
13521  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_WIDTH },
13522  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
13523  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_WIDTH },
13524  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
13525  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_WIDTH },
13526  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
13527  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_WIDTH },
13528  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
13529  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_WIDTH },
13530  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
13531  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_WIDTH },
13532  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
13533  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_WIDTH },
13534  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
13535  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_WIDTH },
13536  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
13537  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_WIDTH },
13538  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
13539  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_WIDTH },
13540  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
13541  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_WIDTH },
13542  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
13543  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_WIDTH },
13544  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
13545  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_WIDTH },
13546  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
13547  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_WIDTH },
13548  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
13549  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_WIDTH },
13550 };
13551 
13557 static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13558 {
13559  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13560  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
13561  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13562  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
13563  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13564  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
13565  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13566  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
13567 };
13568 
13574 static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13575 {
13576  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13577  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
13578 };
13579 
13585 static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13586 {
13587  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13588  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_WIDTH },
13589 };
13590 
13596 static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS] =
13597 {
13598  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_CHECKER_TYPE,
13599  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_WIDTH },
13600  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_CHECKER_TYPE,
13601  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_WIDTH },
13602  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_CHECKER_TYPE,
13603  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_WIDTH },
13604  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_CHECKER_TYPE,
13605  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_WIDTH },
13606  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_CHECKER_TYPE,
13607  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_WIDTH },
13608  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_CHECKER_TYPE,
13609  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_WIDTH },
13610  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_CHECKER_TYPE,
13611  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_WIDTH },
13612  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_CHECKER_TYPE,
13613  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_WIDTH },
13614  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_CHECKER_TYPE,
13615  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_WIDTH },
13616  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_CHECKER_TYPE,
13617  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_WIDTH },
13618  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_CHECKER_TYPE,
13619  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_WIDTH },
13620  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_CHECKER_TYPE,
13621  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_WIDTH },
13622  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_CHECKER_TYPE,
13623  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_WIDTH },
13624  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_CHECKER_TYPE,
13625  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_WIDTH },
13626  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_CHECKER_TYPE,
13627  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_WIDTH },
13628  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_CHECKER_TYPE,
13629  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_WIDTH },
13630 };
13631 
13637 {
13638  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID, 0u,
13639  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_SIZE, 4u,
13640  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ROW_WIDTH, ((bool)false) },
13641  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID, 0u,
13642  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_SIZE, 4u,
13643  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ROW_WIDTH, ((bool)false) },
13644 };
13645 
13651 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS] =
13652 {
13653  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
13654  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_0_WIDTH },
13655  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
13656  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_1_WIDTH },
13657  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
13658  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_2_WIDTH },
13659  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
13660  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_3_WIDTH },
13661  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
13662  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_4_WIDTH },
13663  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
13664  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_5_WIDTH },
13665  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
13666  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_6_WIDTH },
13667  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
13668  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_7_WIDTH },
13669  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
13670  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_8_WIDTH },
13671  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
13672  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_9_WIDTH },
13673  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
13674  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_10_WIDTH },
13675  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
13676  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_11_WIDTH },
13677  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
13678  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_12_WIDTH },
13679  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
13680  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_13_WIDTH },
13681  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
13682  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_14_WIDTH },
13683  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
13684  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_15_WIDTH },
13685  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
13686  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_16_WIDTH },
13687  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
13688  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_17_WIDTH },
13689  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
13690  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_18_WIDTH },
13691  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
13692  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_19_WIDTH },
13693  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
13694  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_20_WIDTH },
13695  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
13696  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_21_WIDTH },
13697  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
13698  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_22_WIDTH },
13699  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
13700  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_23_WIDTH },
13701  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
13702  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_24_WIDTH },
13703  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
13704  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_25_WIDTH },
13705  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
13706  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_26_WIDTH },
13707  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
13708  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_27_WIDTH },
13709  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
13710  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_28_WIDTH },
13711  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
13712  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_29_WIDTH },
13713  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
13714  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_30_WIDTH },
13715  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
13716  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_31_WIDTH },
13717  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
13718  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_32_WIDTH },
13719  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
13720  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_33_WIDTH },
13721  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
13722  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_34_WIDTH },
13723  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
13724  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_35_WIDTH },
13725  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
13726  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_36_WIDTH },
13727  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
13728  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_37_WIDTH },
13729  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
13730  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_38_WIDTH },
13731  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
13732  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_39_WIDTH },
13733  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
13734  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_40_WIDTH },
13735  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
13736  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_41_WIDTH },
13737  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
13738  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_42_WIDTH },
13739  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
13740  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_43_WIDTH },
13741  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
13742  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_44_WIDTH },
13743  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
13744  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_45_WIDTH },
13745  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
13746  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_46_WIDTH },
13747  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
13748  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_47_WIDTH },
13749  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
13750  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_48_WIDTH },
13751  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
13752  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_49_WIDTH },
13753  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
13754  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_50_WIDTH },
13755  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
13756  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_51_WIDTH },
13757  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
13758  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_52_WIDTH },
13759  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
13760  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_53_WIDTH },
13761  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
13762  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_54_WIDTH },
13763  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
13764  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_55_WIDTH },
13765  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
13766  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_56_WIDTH },
13767  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
13768  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_57_WIDTH },
13769  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
13770  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_58_WIDTH },
13771  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
13772  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_59_WIDTH },
13773  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
13774  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_60_WIDTH },
13775  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
13776  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_61_WIDTH },
13777  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
13778  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_62_WIDTH },
13779  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
13780  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_63_WIDTH },
13781  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
13782  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_64_WIDTH },
13783 };
13784 
13790 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS] =
13791 {
13792  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
13793  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_0_WIDTH },
13794  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
13795  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_1_WIDTH },
13796  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
13797  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_2_WIDTH },
13798  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
13799  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_3_WIDTH },
13800  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
13801  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_4_WIDTH },
13802  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
13803  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_5_WIDTH },
13804  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
13805  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_6_WIDTH },
13806  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
13807  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_7_WIDTH },
13808  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
13809  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_8_WIDTH },
13810  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
13811  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_9_WIDTH },
13812  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
13813  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_10_WIDTH },
13814  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
13815  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_11_WIDTH },
13816  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
13817  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_12_WIDTH },
13818  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
13819  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_13_WIDTH },
13820  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
13821  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_14_WIDTH },
13822 };
13823 
13829 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS] =
13830 {
13831  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
13832  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_0_WIDTH },
13833  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
13834  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_1_WIDTH },
13835  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
13836  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_2_WIDTH },
13837  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
13838  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_3_WIDTH },
13839 };
13840 
13846 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS] =
13847 {
13848  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
13849  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_0_WIDTH },
13850  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
13851  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_1_WIDTH },
13852  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
13853  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_2_WIDTH },
13854  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
13855  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_3_WIDTH },
13856  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_4_CHECKER_TYPE,
13857  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_4_WIDTH },
13858  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_5_CHECKER_TYPE,
13859  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_5_WIDTH },
13860  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_6_CHECKER_TYPE,
13861  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_6_WIDTH },
13862  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_7_CHECKER_TYPE,
13863  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_7_WIDTH },
13864  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_8_CHECKER_TYPE,
13865  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_8_WIDTH },
13866  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_9_CHECKER_TYPE,
13867  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_9_WIDTH },
13868  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_10_CHECKER_TYPE,
13869  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_10_WIDTH },
13870  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_11_CHECKER_TYPE,
13871  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_11_WIDTH },
13872  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_12_CHECKER_TYPE,
13873  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_12_WIDTH },
13874  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_13_CHECKER_TYPE,
13875  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_13_WIDTH },
13876  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_14_CHECKER_TYPE,
13877  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_14_WIDTH },
13878  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_15_CHECKER_TYPE,
13879  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_15_WIDTH },
13880  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_16_CHECKER_TYPE,
13881  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_16_WIDTH },
13882  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_17_CHECKER_TYPE,
13883  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_17_WIDTH },
13884  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_18_CHECKER_TYPE,
13885  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_18_WIDTH },
13886  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_19_CHECKER_TYPE,
13887  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_19_WIDTH },
13888  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_20_CHECKER_TYPE,
13889  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_20_WIDTH },
13890  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_21_CHECKER_TYPE,
13891  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_21_WIDTH },
13892  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_22_CHECKER_TYPE,
13893  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_22_WIDTH },
13894  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_23_CHECKER_TYPE,
13895  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_23_WIDTH },
13896  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_24_CHECKER_TYPE,
13897  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_24_WIDTH },
13898  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_25_CHECKER_TYPE,
13899  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_25_WIDTH },
13900  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_26_CHECKER_TYPE,
13901  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_26_WIDTH },
13902  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_27_CHECKER_TYPE,
13903  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_27_WIDTH },
13904  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_28_CHECKER_TYPE,
13905  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_28_WIDTH },
13906  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_29_CHECKER_TYPE,
13907  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_29_WIDTH },
13908  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_30_CHECKER_TYPE,
13909  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_30_WIDTH },
13910  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_31_CHECKER_TYPE,
13911  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_31_WIDTH },
13912  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_32_CHECKER_TYPE,
13913  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_32_WIDTH },
13914  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_33_CHECKER_TYPE,
13915  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_33_WIDTH },
13916  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_34_CHECKER_TYPE,
13917  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_34_WIDTH },
13918  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_35_CHECKER_TYPE,
13919  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_35_WIDTH },
13920  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_36_CHECKER_TYPE,
13921  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_36_WIDTH },
13922  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_37_CHECKER_TYPE,
13923  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_37_WIDTH },
13924  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_38_CHECKER_TYPE,
13925  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_38_WIDTH },
13926  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_39_CHECKER_TYPE,
13927  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_39_WIDTH },
13928  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_40_CHECKER_TYPE,
13929  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_40_WIDTH },
13930  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_41_CHECKER_TYPE,
13931  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_41_WIDTH },
13932  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_42_CHECKER_TYPE,
13933  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_42_WIDTH },
13934  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_43_CHECKER_TYPE,
13935  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_43_WIDTH },
13936  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_44_CHECKER_TYPE,
13937  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_44_WIDTH },
13938  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_45_CHECKER_TYPE,
13939  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_45_WIDTH },
13940  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_46_CHECKER_TYPE,
13941  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_46_WIDTH },
13942  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_47_CHECKER_TYPE,
13943  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_47_WIDTH },
13944  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_48_CHECKER_TYPE,
13945  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_48_WIDTH },
13946  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_49_CHECKER_TYPE,
13947  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_49_WIDTH },
13948  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_50_CHECKER_TYPE,
13949  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_50_WIDTH },
13950  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_51_CHECKER_TYPE,
13951  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_51_WIDTH },
13952  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_52_CHECKER_TYPE,
13953  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_52_WIDTH },
13954  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_53_CHECKER_TYPE,
13955  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_53_WIDTH },
13956  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_54_CHECKER_TYPE,
13957  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_54_WIDTH },
13958  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_55_CHECKER_TYPE,
13959  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_55_WIDTH },
13960  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_56_CHECKER_TYPE,
13961  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_56_WIDTH },
13962  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_57_CHECKER_TYPE,
13963  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_57_WIDTH },
13964  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_58_CHECKER_TYPE,
13965  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_58_WIDTH },
13966  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_59_CHECKER_TYPE,
13967  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_59_WIDTH },
13968  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_60_CHECKER_TYPE,
13969  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_60_WIDTH },
13970  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_61_CHECKER_TYPE,
13971  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_61_WIDTH },
13972  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_62_CHECKER_TYPE,
13973  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_62_WIDTH },
13974  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_63_CHECKER_TYPE,
13975  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_63_WIDTH },
13976  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_64_CHECKER_TYPE,
13977  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_64_WIDTH },
13978  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_65_CHECKER_TYPE,
13979  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_65_WIDTH },
13980  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_66_CHECKER_TYPE,
13981  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_66_WIDTH },
13982  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_67_CHECKER_TYPE,
13983  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_67_WIDTH },
13984  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_68_CHECKER_TYPE,
13985  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_68_WIDTH },
13986 };
13987 
13993 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS] =
13994 {
13995  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
13996  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_0_WIDTH },
13997  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
13998  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_1_WIDTH },
13999  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
14000  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_2_WIDTH },
14001  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
14002  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_3_WIDTH },
14003  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_4_CHECKER_TYPE,
14004  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_4_WIDTH },
14005  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_5_CHECKER_TYPE,
14006  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_5_WIDTH },
14007  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_6_CHECKER_TYPE,
14008  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_6_WIDTH },
14009  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_7_CHECKER_TYPE,
14010  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_7_WIDTH },
14011  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_8_CHECKER_TYPE,
14012  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_8_WIDTH },
14013  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_9_CHECKER_TYPE,
14014  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_9_WIDTH },
14015  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_10_CHECKER_TYPE,
14016  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_10_WIDTH },
14017  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_11_CHECKER_TYPE,
14018  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_11_WIDTH },
14019  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_12_CHECKER_TYPE,
14020  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_12_WIDTH },
14021  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_13_CHECKER_TYPE,
14022  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_13_WIDTH },
14023  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_14_CHECKER_TYPE,
14024  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_14_WIDTH },
14025  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_15_CHECKER_TYPE,
14026  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_15_WIDTH },
14027  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_16_CHECKER_TYPE,
14028  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_16_WIDTH },
14029  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_17_CHECKER_TYPE,
14030  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_17_WIDTH },
14031  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_18_CHECKER_TYPE,
14032  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_18_WIDTH },
14033  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_19_CHECKER_TYPE,
14034  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_19_WIDTH },
14035  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_20_CHECKER_TYPE,
14036  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_20_WIDTH },
14037  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_21_CHECKER_TYPE,
14038  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_21_WIDTH },
14039  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_22_CHECKER_TYPE,
14040  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_22_WIDTH },
14041  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_23_CHECKER_TYPE,
14042  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_23_WIDTH },
14043  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_24_CHECKER_TYPE,
14044  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_24_WIDTH },
14045  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_25_CHECKER_TYPE,
14046  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_25_WIDTH },
14047  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_26_CHECKER_TYPE,
14048  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_26_WIDTH },
14049  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_27_CHECKER_TYPE,
14050  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_27_WIDTH },
14051  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_28_CHECKER_TYPE,
14052  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_28_WIDTH },
14053  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_29_CHECKER_TYPE,
14054  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_29_WIDTH },
14055  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_30_CHECKER_TYPE,
14056  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_30_WIDTH },
14057  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_31_CHECKER_TYPE,
14058  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_31_WIDTH },
14059  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_32_CHECKER_TYPE,
14060  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_32_WIDTH },
14061  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_33_CHECKER_TYPE,
14062  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_33_WIDTH },
14063  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_34_CHECKER_TYPE,
14064  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_34_WIDTH },
14065  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_35_CHECKER_TYPE,
14066  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_35_WIDTH },
14067  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_36_CHECKER_TYPE,
14068  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_36_WIDTH },
14069  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_37_CHECKER_TYPE,
14070  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_37_WIDTH },
14071  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_38_CHECKER_TYPE,
14072  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_38_WIDTH },
14073  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_39_CHECKER_TYPE,
14074  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_39_WIDTH },
14075  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_40_CHECKER_TYPE,
14076  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_40_WIDTH },
14077  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_41_CHECKER_TYPE,
14078  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_41_WIDTH },
14079  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_42_CHECKER_TYPE,
14080  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_42_WIDTH },
14081  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_43_CHECKER_TYPE,
14082  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_43_WIDTH },
14083  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_44_CHECKER_TYPE,
14084  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_44_WIDTH },
14085  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_45_CHECKER_TYPE,
14086  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_45_WIDTH },
14087  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_46_CHECKER_TYPE,
14088  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_46_WIDTH },
14089  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_47_CHECKER_TYPE,
14090  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_47_WIDTH },
14091  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_48_CHECKER_TYPE,
14092  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_48_WIDTH },
14093  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_49_CHECKER_TYPE,
14094  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_49_WIDTH },
14095  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_50_CHECKER_TYPE,
14096  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_50_WIDTH },
14097  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_51_CHECKER_TYPE,
14098  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_51_WIDTH },
14099  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_52_CHECKER_TYPE,
14100  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_52_WIDTH },
14101  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_53_CHECKER_TYPE,
14102  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_53_WIDTH },
14103  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_54_CHECKER_TYPE,
14104  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_54_WIDTH },
14105  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_55_CHECKER_TYPE,
14106  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_55_WIDTH },
14107  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_56_CHECKER_TYPE,
14108  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_56_WIDTH },
14109  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_57_CHECKER_TYPE,
14110  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_57_WIDTH },
14111  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_58_CHECKER_TYPE,
14112  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_58_WIDTH },
14113  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_59_CHECKER_TYPE,
14114  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_59_WIDTH },
14115  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_60_CHECKER_TYPE,
14116  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_60_WIDTH },
14117  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_61_CHECKER_TYPE,
14118  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_61_WIDTH },
14119  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_62_CHECKER_TYPE,
14120  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_62_WIDTH },
14121  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_63_CHECKER_TYPE,
14122  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_63_WIDTH },
14123  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_64_CHECKER_TYPE,
14124  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_64_WIDTH },
14125  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_65_CHECKER_TYPE,
14126  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_65_WIDTH },
14127  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_66_CHECKER_TYPE,
14128  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_66_WIDTH },
14129  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_67_CHECKER_TYPE,
14130  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_67_WIDTH },
14131  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_68_CHECKER_TYPE,
14132  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_68_WIDTH },
14133 };
14134 
14140 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS] =
14141 {
14142  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
14143  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_0_WIDTH },
14144  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
14145  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_1_WIDTH },
14146  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
14147  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_2_WIDTH },
14148  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
14149  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_3_WIDTH },
14150  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
14151  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_4_WIDTH },
14152  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
14153  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_5_WIDTH },
14154  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
14155  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_6_WIDTH },
14156  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
14157  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_7_WIDTH },
14158  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
14159  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_8_WIDTH },
14160  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
14161  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_9_WIDTH },
14162  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
14163  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_10_WIDTH },
14164  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
14165  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_11_WIDTH },
14166  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
14167  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_12_WIDTH },
14168  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
14169  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_13_WIDTH },
14170  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
14171  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_14_WIDTH },
14172 };
14173 
14179 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
14180 {
14181  { SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
14182  SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
14183 };
14184 
14190 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS] =
14191 {
14192  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
14193  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_0_WIDTH },
14194  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
14195  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_1_WIDTH },
14196  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
14197  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_2_WIDTH },
14198  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
14199  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_3_WIDTH },
14200  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
14201  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_4_WIDTH },
14202  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
14203  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_5_WIDTH },
14204  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
14205  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_6_WIDTH },
14206  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
14207  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_7_WIDTH },
14208  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
14209  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_8_WIDTH },
14210  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
14211  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_9_WIDTH },
14212  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
14213  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_10_WIDTH },
14214  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
14215  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_11_WIDTH },
14216  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
14217  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_12_WIDTH },
14218  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_13_CHECKER_TYPE,
14219  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_13_WIDTH },
14220  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_14_CHECKER_TYPE,
14221  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_14_WIDTH },
14222  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_15_CHECKER_TYPE,
14223  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_15_WIDTH },
14224  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_16_CHECKER_TYPE,
14225  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_16_WIDTH },
14226  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_17_CHECKER_TYPE,
14227  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_17_WIDTH },
14228  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_18_CHECKER_TYPE,
14229  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_18_WIDTH },
14230  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_19_CHECKER_TYPE,
14231  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_19_WIDTH },
14232  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_20_CHECKER_TYPE,
14233  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_20_WIDTH },
14234  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_21_CHECKER_TYPE,
14235  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_21_WIDTH },
14236  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_22_CHECKER_TYPE,
14237  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_22_WIDTH },
14238  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_23_CHECKER_TYPE,
14239  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_23_WIDTH },
14240  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_24_CHECKER_TYPE,
14241  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_24_WIDTH },
14242  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_25_CHECKER_TYPE,
14243  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_25_WIDTH },
14244  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_26_CHECKER_TYPE,
14245  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_26_WIDTH },
14246  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_27_CHECKER_TYPE,
14247  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_27_WIDTH },
14248  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_28_CHECKER_TYPE,
14249  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_28_WIDTH },
14250  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_29_CHECKER_TYPE,
14251  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_29_WIDTH },
14252  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_30_CHECKER_TYPE,
14253  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_30_WIDTH },
14254  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_31_CHECKER_TYPE,
14255  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_31_WIDTH },
14256  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_32_CHECKER_TYPE,
14257  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_32_WIDTH },
14258  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_33_CHECKER_TYPE,
14259  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_33_WIDTH },
14260  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_34_CHECKER_TYPE,
14261  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_34_WIDTH },
14262  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_35_CHECKER_TYPE,
14263  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_35_WIDTH },
14264  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_36_CHECKER_TYPE,
14265  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_36_WIDTH },
14266  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_37_CHECKER_TYPE,
14267  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_37_WIDTH },
14268  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_38_CHECKER_TYPE,
14269  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_38_WIDTH },
14270  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_39_CHECKER_TYPE,
14271  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_39_WIDTH },
14272  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_40_CHECKER_TYPE,
14273  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_40_WIDTH },
14274  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_41_CHECKER_TYPE,
14275  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_41_WIDTH },
14276  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_42_CHECKER_TYPE,
14277  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_42_WIDTH },
14278  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_43_CHECKER_TYPE,
14279  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_43_WIDTH },
14280  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_44_CHECKER_TYPE,
14281  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_44_WIDTH },
14282  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_45_CHECKER_TYPE,
14283  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_45_WIDTH },
14284  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_46_CHECKER_TYPE,
14285  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_46_WIDTH },
14286  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_47_CHECKER_TYPE,
14287  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_47_WIDTH },
14288  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_48_CHECKER_TYPE,
14289  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_48_WIDTH },
14290  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_49_CHECKER_TYPE,
14291  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_49_WIDTH },
14292  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_50_CHECKER_TYPE,
14293  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_50_WIDTH },
14294  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_51_CHECKER_TYPE,
14295  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_51_WIDTH },
14296  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_52_CHECKER_TYPE,
14297  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_52_WIDTH },
14298  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_53_CHECKER_TYPE,
14299  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_53_WIDTH },
14300  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_54_CHECKER_TYPE,
14301  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_54_WIDTH },
14302  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_55_CHECKER_TYPE,
14303  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_55_WIDTH },
14304  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_56_CHECKER_TYPE,
14305  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_56_WIDTH },
14306  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_57_CHECKER_TYPE,
14307  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_57_WIDTH },
14308  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_58_CHECKER_TYPE,
14309  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_58_WIDTH },
14310  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_59_CHECKER_TYPE,
14311  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_59_WIDTH },
14312  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_60_CHECKER_TYPE,
14313  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_60_WIDTH },
14314  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_61_CHECKER_TYPE,
14315  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_61_WIDTH },
14316  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_62_CHECKER_TYPE,
14317  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_62_WIDTH },
14318  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_63_CHECKER_TYPE,
14319  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_63_WIDTH },
14320  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_64_CHECKER_TYPE,
14321  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_64_WIDTH },
14322  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_65_CHECKER_TYPE,
14323  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_65_WIDTH },
14324  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_66_CHECKER_TYPE,
14325  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_66_WIDTH },
14326  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_67_CHECKER_TYPE,
14327  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_67_WIDTH },
14328  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_68_CHECKER_TYPE,
14329  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_68_WIDTH },
14330  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_69_CHECKER_TYPE,
14331  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_69_WIDTH },
14332  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_70_CHECKER_TYPE,
14333  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_70_WIDTH },
14334  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_71_CHECKER_TYPE,
14335  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_71_WIDTH },
14336  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_72_CHECKER_TYPE,
14337  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_72_WIDTH },
14338  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_73_CHECKER_TYPE,
14339  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_73_WIDTH },
14340  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_74_CHECKER_TYPE,
14341  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_74_WIDTH },
14342  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_75_CHECKER_TYPE,
14343  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_75_WIDTH },
14344  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_76_CHECKER_TYPE,
14345  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_76_WIDTH },
14346  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_77_CHECKER_TYPE,
14347  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_77_WIDTH },
14348  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_78_CHECKER_TYPE,
14349  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_78_WIDTH },
14350  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_79_CHECKER_TYPE,
14351  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_79_WIDTH },
14352  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_80_CHECKER_TYPE,
14353  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_80_WIDTH },
14354 };
14355 
14361 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
14362 {
14363  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
14364  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
14365  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
14366  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
14367  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
14368  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
14369  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
14370  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
14371  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
14372  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
14373  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
14374  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
14375  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
14376  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
14377  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
14378  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
14379  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
14380  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
14381  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
14382  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
14383  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
14384  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
14385  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
14386  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
14387  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
14388  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
14389  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
14390  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
14391  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
14392  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
14393  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
14394  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
14395  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
14396  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
14397 };
14398 
14404 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
14405 {
14406  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
14407  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
14408  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
14409  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
14410  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
14411  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
14412  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
14413  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
14414  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
14415  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
14416 };
14417 
14423 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
14424 {
14425  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
14426  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
14427  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
14428  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
14429  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
14430  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
14431  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
14432  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
14433  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
14434  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
14435  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
14436  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
14437  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
14438  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
14439  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
14440  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
14441  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
14442  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
14443  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
14444  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
14445  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
14446  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
14447  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
14448  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
14449  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
14450  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
14451  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
14452  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
14453  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
14454  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
14455  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
14456  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
14457  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
14458  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
14459 };
14460 
14466 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
14467 {
14468  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
14469  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
14470  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
14471  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
14472  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
14473  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
14474  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
14475  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
14476  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
14477  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
14478  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
14479  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
14480  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
14481  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
14482  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
14483  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
14484  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
14485  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
14486  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
14487  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
14488  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
14489  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
14490 };
14491 
14497 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
14498 {
14499  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
14500  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
14501  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
14502  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
14503  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
14504  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
14505  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
14506  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
14507  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
14508  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
14509  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
14510  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
14511  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
14512  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
14513  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
14514  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
14515  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
14516  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
14517  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
14518  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
14519  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
14520  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
14521  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
14522  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
14523  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
14524  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
14525  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
14526  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
14527  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
14528  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
14529  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
14530  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
14531  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
14532  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
14533 };
14534 
14540 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
14541 {
14542  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
14543  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
14544  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
14545  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
14546  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
14547  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
14548  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
14549  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
14550  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
14551  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
14552  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
14553  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
14554  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
14555  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
14556  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
14557  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
14558  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
14559  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
14560  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
14561  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
14562  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
14563  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
14564  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
14565  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
14566  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
14567  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
14568  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
14569  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
14570 };
14571 
14577 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
14578 {
14579  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
14580  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
14581  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
14582  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
14583  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
14584  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
14585  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
14586  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
14587  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
14588  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
14589  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
14590  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
14591  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
14592  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
14593  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
14594  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
14595  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
14596  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
14597  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
14598  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
14599  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
14600  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
14601  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
14602  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
14603  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
14604  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
14605 };
14606 
14612 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
14613 {
14614  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
14615  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
14616  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
14617  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
14618  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
14619  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
14620  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
14621  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
14622  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
14623  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
14624  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
14625  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
14626  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
14627  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
14628  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
14629  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
14630  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
14631  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
14632  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
14633  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
14634  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
14635  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
14636  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
14637  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
14638  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
14639  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
14640 };
14641 
14647 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
14648 {
14649  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
14650  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
14651  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
14652  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
14653  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
14654  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
14655  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
14656  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
14657  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
14658  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
14659  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
14660  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
14661  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
14662  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
14663  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
14664  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
14665  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
14666  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
14667  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
14668  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
14669  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
14670  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
14671  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
14672  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
14673  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
14674  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
14675 };
14676 
14682 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
14683 {
14684  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
14685  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
14686  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
14687  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
14688  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
14689  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
14690  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
14691  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
14692  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
14693  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
14694  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
14695  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
14696  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
14697  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
14698  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
14699  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
14700  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
14701  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
14702  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
14703  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
14704  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
14705  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
14706  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
14707  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
14708  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
14709  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
14710 };
14711 
14717 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
14718 {
14719  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
14720  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
14721  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
14722  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
14723  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
14724  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
14725  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
14726  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
14727  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
14728  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
14729  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
14730  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
14731  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
14732  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
14733  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
14734  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
14735  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
14736  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
14737  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
14738  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
14739  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
14740  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
14741  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
14742  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
14743  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
14744  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
14745  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
14746  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
14747  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
14748  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
14749  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
14750  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
14751  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
14752  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
14753 };
14754 
14760 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
14761 {
14762  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
14763  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
14764  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
14765  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
14766  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
14767  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
14768  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
14769  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
14770  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
14771  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
14772  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
14773  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
14774  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
14775  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
14776  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
14777  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
14778  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
14779  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
14780  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
14781  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
14782  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
14783  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
14784  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
14785  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
14786  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
14787  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
14788  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
14789  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
14790 };
14791 
14797 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
14798 {
14799  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
14800  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
14801  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
14802  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
14803  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
14804  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
14805  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
14806  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
14807  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
14808  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
14809  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
14810  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
14811  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
14812  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
14813  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
14814  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
14815  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
14816  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
14817  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
14818  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
14819  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
14820  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
14821  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
14822  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
14823  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
14824  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
14825 };
14826 
14832 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
14833 {
14834  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
14835  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
14836  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
14837  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
14838  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
14839  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
14840  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
14841  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
14842  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
14843  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
14844  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
14845  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
14846  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
14847  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
14848  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
14849  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
14850  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
14851  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
14852  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
14853  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
14854  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
14855  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
14856  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
14857  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
14858  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
14859  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
14860  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
14861  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
14862  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
14863  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
14864  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
14865  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
14866  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
14867  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
14868 };
14869 
14875 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
14876 {
14877  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
14878  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
14879  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
14880  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
14881  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
14882  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
14883  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
14884  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
14885  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
14886  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
14887  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
14888  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
14889  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
14890  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
14891 };
14892 
14898 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
14899 {
14900  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
14901  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
14902  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
14903  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
14904  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
14905  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
14906  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
14907  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
14908  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
14909  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
14910  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
14911  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
14912  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
14913  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
14914  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
14915  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
14916  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
14917  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
14918  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
14919  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
14920  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
14921  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
14922  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
14923  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
14924  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
14925  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
14926  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
14927  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
14928  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
14929  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
14930  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
14931  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
14932  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
14933  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
14934 };
14935 
14941 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
14942 {
14943  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
14944  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
14945  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
14946  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
14947  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
14948  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
14949  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
14950  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
14951  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
14952  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
14953  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
14954  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
14955  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
14956  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
14957 };
14958 
14964 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
14965 {
14966  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
14967  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
14968  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
14969  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
14970  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
14971  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
14972  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
14973  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
14974  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
14975  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
14976  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
14977  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
14978  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
14979  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
14980  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
14981  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
14982  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
14983  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
14984  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
14985  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
14986  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
14987  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
14988  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
14989  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
14990  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
14991  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
14992  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
14993  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
14994  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
14995  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
14996  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
14997  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
14998  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
14999  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
15000  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
15001  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
15002  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
15003  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
15004  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
15005  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
15006  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
15007  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
15008  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
15009  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
15010  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
15011  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
15012  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
15013  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
15014  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
15015  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
15016  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
15017  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
15018  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
15019  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
15020  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
15021  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
15022  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
15023  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
15024  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
15025  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
15026  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
15027  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
15028  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
15029  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
15030  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
15031  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
15032  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
15033  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
15034  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
15035  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
15036  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
15037  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
15038  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
15039  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
15040  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
15041  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
15042  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
15043  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
15044  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
15045  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
15046  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
15047  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
15048  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
15049  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
15050  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
15051  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
15052  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
15053  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
15054  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
15055  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
15056  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
15057  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
15058  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
15059  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
15060  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
15061  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
15062  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
15063  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
15064  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
15065  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
15066  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
15067  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
15068  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
15069  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
15070  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
15071  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
15072  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
15073  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
15074  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
15075  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
15076  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
15077  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
15078  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
15079  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
15080  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
15081  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
15082  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
15083  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
15084  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
15085  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
15086  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
15087  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
15088  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
15089  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
15090  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
15091  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
15092  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
15093  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
15094  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
15095  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
15096  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
15097  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
15098  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
15099  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
15100  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
15101  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
15102  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
15103  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
15104  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
15105  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
15106  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
15107  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
15108  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
15109  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
15110  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
15111  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
15112  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
15113  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
15114  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
15115  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
15116  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
15117  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
15118  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
15119  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
15120  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
15121  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
15122  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
15123  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
15124  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
15125  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
15126  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
15127  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
15128  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
15129  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
15130  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
15131  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
15132  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
15133  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
15134  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
15135  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
15136  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
15137  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
15138  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
15139  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
15140  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
15141  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
15142  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
15143  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
15144  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
15145  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
15146  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
15147  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
15148  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
15149  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
15150  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
15151  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
15152  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
15153  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
15154  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
15155  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
15156  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
15157  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
15158  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
15159  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
15160  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
15161  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
15162  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
15163  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
15164  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
15165  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
15166  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
15167  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
15168  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
15169  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
15170  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
15171  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
15172  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
15173  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
15174  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
15175  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
15176  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
15177  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
15178  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
15179  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
15180  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
15181  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
15182  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
15183  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
15184  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
15185  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
15186  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
15187  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
15188  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
15189  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
15190  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
15191  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
15192  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
15193  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
15194  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
15195  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
15196  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
15197  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
15198  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
15199  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
15200  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
15201  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
15202  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
15203  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
15204  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
15205  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
15206  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
15207  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
15208  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
15209  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
15210  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
15211  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
15212  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
15213  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
15214  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
15215  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
15216  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
15217  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
15218  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
15219  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
15220  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
15221  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
15222  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
15223  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
15224  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
15225  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
15226  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
15227  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
15228  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
15229  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
15230  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
15231  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
15232  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
15233  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
15234  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
15235  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
15236  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
15237  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
15238  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
15239  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
15240  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
15241  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
15242  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
15243  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
15244  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
15245  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
15246  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
15247  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
15248  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
15249  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
15250  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
15251  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
15252  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
15253  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
15254  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
15255  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
15256  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
15257  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
15258  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
15259  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
15260  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
15261  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
15262  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
15263  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
15264  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
15265  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
15266  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
15267  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
15268  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
15269  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
15270  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
15271  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
15272  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
15273  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
15274  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
15275  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
15276  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
15277  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
15278  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
15279  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
15280  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
15281  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
15282  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
15283  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
15284  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
15285  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
15286  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
15287  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
15288  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
15289  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
15290  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
15291  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
15292  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
15293  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
15294  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
15295  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
15296  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
15297  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
15298  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
15299  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
15300  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
15301  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
15302  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
15303  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
15304  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
15305  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
15306  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
15307  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
15308  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
15309  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
15310  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
15311  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
15312  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
15313  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
15314  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
15315  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
15316  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
15317  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
15318  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
15319  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
15320  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
15321  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
15322  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
15323  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
15324  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
15325  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
15326  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
15327  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
15328  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
15329  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
15330  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
15331  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
15332  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
15333  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
15334  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
15335  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
15336  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
15337  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
15338  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
15339  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
15340  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
15341  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
15342  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
15343  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
15344  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
15345  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
15346  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
15347  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
15348  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
15349  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
15350  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
15351  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
15352  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
15353  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
15354  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
15355  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
15356  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
15357  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
15358  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
15359  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
15360  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
15361  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
15362  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
15363  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
15364  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
15365  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
15366  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
15367  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
15368  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
15369  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
15370  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
15371  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
15372  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
15373  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
15374  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
15375  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
15376  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
15377  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
15378  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
15379  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
15380  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
15381  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
15382  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
15383  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
15384  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
15385  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
15386  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
15387  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
15388  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
15389  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
15390  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
15391  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
15392  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
15393  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
15394  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
15395  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
15396  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
15397  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
15398  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
15399  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
15400  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
15401  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
15402  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
15403  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
15404  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
15405  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
15406  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
15407  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
15408  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
15409  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
15410  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
15411  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
15412  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
15413  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
15414  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
15415  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
15416  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
15417  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
15418  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
15419  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
15420  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
15421  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
15422  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
15423  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
15424  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
15425  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
15426  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
15427  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
15428  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
15429  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
15430  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
15431  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
15432  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
15433  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
15434  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
15435  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
15436  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
15437  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
15438  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
15439  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
15440  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
15441  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
15442  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
15443  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
15444  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
15445  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
15446  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
15447  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
15448  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
15449  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
15450  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
15451  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
15452  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
15453  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
15454  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
15455  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
15456  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
15457  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
15458  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
15459  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
15460  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
15461  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
15462  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
15463  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
15464  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
15465  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
15466  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
15467  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
15468  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
15469  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
15470  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
15471  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
15472  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
15473  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
15474  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
15475  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
15476  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
15477  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
15478 };
15479 
15485 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
15486 {
15487  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
15488  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
15489  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
15490  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
15491  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
15492  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
15493  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
15494  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
15495  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
15496  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
15497  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
15498  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
15499  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
15500  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
15501  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
15502  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
15503  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
15504  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
15505  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
15506  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
15507  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
15508  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
15509  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
15510  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
15511  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
15512  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
15513  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
15514  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
15515  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
15516  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
15517  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
15518  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
15519  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
15520  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
15521  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
15522  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
15523  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
15524  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
15525  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
15526  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
15527  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
15528  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
15529  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
15530  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
15531  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
15532  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
15533  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
15534  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
15535  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
15536  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
15537  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
15538  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
15539  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
15540  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
15541  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
15542  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
15543  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
15544  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
15545  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
15546  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
15547  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
15548  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
15549  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
15550  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
15551  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
15552  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
15553  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
15554  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
15555  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
15556  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
15557  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
15558  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
15559  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
15560  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
15561  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
15562  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
15563  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
15564  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
15565  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
15566  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
15567  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
15568  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
15569  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
15570  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
15571  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
15572  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
15573  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
15574  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
15575  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
15576  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
15577  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
15578  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
15579  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
15580  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
15581  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
15582  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
15583  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
15584  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
15585  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
15586  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
15587  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
15588  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
15589  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
15590  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
15591  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
15592  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
15593  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
15594  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
15595  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
15596  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
15597  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
15598  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
15599  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
15600  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
15601  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
15602  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
15603  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
15604  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
15605  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
15606  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
15607  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
15608  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
15609  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
15610  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
15611  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
15612  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
15613  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
15614  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
15615  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
15616  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
15617  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
15618  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
15619  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
15620  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
15621  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
15622  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
15623  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
15624  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
15625  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
15626  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
15627  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
15628  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
15629  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
15630  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
15631  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
15632  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
15633  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
15634  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
15635  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
15636  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
15637  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
15638  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
15639  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
15640  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
15641  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
15642  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
15643  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
15644  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
15645  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
15646  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
15647  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
15648  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
15649  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
15650  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
15651  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
15652  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
15653  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
15654  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
15655  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
15656  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
15657  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
15658  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
15659  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
15660  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
15661  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
15662  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
15663  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
15664  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
15665  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
15666  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
15667  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
15668  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
15669  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
15670  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
15671  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
15672  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
15673  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
15674  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
15675  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
15676  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
15677  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
15678  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
15679  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
15680  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
15681  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
15682  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
15683  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
15684  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
15685  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
15686  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
15687  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
15688  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
15689  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
15690  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
15691  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
15692  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
15693  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
15694  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
15695  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
15696  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
15697  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
15698  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
15699  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
15700  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
15701  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
15702  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
15703  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
15704  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
15705  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
15706  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
15707  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
15708  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
15709  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
15710  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
15711  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
15712  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
15713  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
15714  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
15715  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
15716  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
15717  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
15718  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
15719  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
15720  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
15721  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
15722  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
15723  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
15724  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
15725  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
15726  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
15727  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
15728  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
15729  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
15730  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
15731  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
15732  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
15733  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
15734  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
15735  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
15736  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
15737  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
15738  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
15739  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
15740  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
15741  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
15742  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
15743  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
15744  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
15745  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
15746  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
15747  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
15748  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
15749  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
15750  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
15751  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
15752  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
15753  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
15754  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
15755  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
15756  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
15757  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
15758  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
15759  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
15760  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
15761  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
15762  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
15763  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
15764  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
15765  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
15766  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
15767  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
15768  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
15769  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
15770  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
15771  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
15772  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
15773  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
15774  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
15775  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
15776  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
15777  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
15778  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
15779  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
15780  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
15781  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
15782  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
15783  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
15784  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
15785  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
15786  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
15787  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
15788  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
15789  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
15790  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
15791  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
15792  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
15793  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
15794  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
15795  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
15796  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
15797  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
15798  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
15799  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
15800  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
15801  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
15802  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
15803  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
15804  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
15805  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
15806  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
15807  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
15808  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
15809  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
15810  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
15811  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
15812  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
15813  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
15814  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
15815  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
15816  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
15817  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
15818  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
15819  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
15820  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
15821  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
15822  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
15823  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
15824  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
15825  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
15826  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
15827  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
15828  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
15829  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
15830  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
15831  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
15832  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
15833  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
15834  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
15835  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
15836  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
15837  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
15838  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
15839  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
15840  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
15841  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
15842  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
15843  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
15844  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
15845  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
15846  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
15847  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
15848  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
15849  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
15850  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
15851  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
15852  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
15853  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
15854  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
15855  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
15856  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
15857  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
15858  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
15859  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
15860  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
15861  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
15862  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
15863  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
15864  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
15865  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
15866  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
15867  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
15868  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
15869  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
15870  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
15871  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
15872  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
15873  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
15874  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
15875  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
15876  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
15877  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
15878  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
15879  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
15880  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
15881  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
15882  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
15883  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
15884  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
15885  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
15886  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
15887  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
15888  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
15889  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
15890  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
15891  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
15892  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
15893  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
15894  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
15895  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
15896  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
15897  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
15898  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
15899  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
15900  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
15901  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
15902  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
15903  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
15904  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
15905  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
15906  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
15907  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
15908  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
15909  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
15910  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
15911  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
15912  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
15913  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
15914  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
15915  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
15916  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
15917  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
15918  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
15919 };
15920 
15926 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
15927 {
15928  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
15929  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
15930  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
15931  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
15932  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
15933  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
15934  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
15935  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
15936  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
15937  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
15938  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
15939  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
15940  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
15941  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
15942  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
15943  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
15944  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
15945  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
15946  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
15947  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
15948  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
15949  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
15950  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
15951  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
15952  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
15953  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
15954  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
15955  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
15956  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
15957  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
15958  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
15959  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
15960  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
15961  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
15962  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
15963  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
15964  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
15965  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
15966  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
15967  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
15968  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
15969  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
15970  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
15971  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
15972  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
15973  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
15974  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
15975  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
15976  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
15977  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
15978  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
15979  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
15980  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
15981  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
15982  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
15983  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
15984  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
15985  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
15986  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
15987  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
15988  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
15989  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
15990  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
15991  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
15992  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
15993  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
15994  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
15995  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
15996  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
15997  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
15998  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
15999  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
16000  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
16001  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
16002  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
16003  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
16004  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
16005  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
16006  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
16007  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
16008  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
16009  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
16010  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
16011  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
16012  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
16013  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
16014  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
16015  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
16016  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
16017  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
16018  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
16019  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
16020  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
16021  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
16022  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
16023  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
16024  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
16025  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
16026  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
16027  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
16028  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
16029  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
16030  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
16031  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
16032  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
16033  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
16034  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
16035  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
16036  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
16037  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
16038  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
16039  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
16040  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
16041  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
16042  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
16043  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
16044  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
16045  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
16046  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
16047  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
16048  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
16049  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
16050  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
16051  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
16052  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
16053  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
16054  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
16055  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
16056  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
16057  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
16058  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
16059  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
16060  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
16061  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
16062  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
16063  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
16064  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
16065  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
16066  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
16067  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
16068  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
16069  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
16070  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
16071  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
16072  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
16073  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
16074  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
16075  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
16076  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
16077  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
16078  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
16079  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
16080  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
16081  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
16082  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
16083  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
16084  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
16085  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
16086  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
16087  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
16088  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
16089  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
16090  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
16091  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
16092  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
16093  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
16094  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
16095  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
16096  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
16097  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
16098  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
16099  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
16100  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
16101  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
16102  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
16103  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
16104  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
16105  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
16106  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
16107  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
16108  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
16109  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
16110  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
16111  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
16112  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
16113  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
16114  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
16115  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
16116  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
16117  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
16118  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
16119  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
16120  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
16121  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
16122  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
16123  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
16124  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
16125  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
16126  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
16127  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
16128  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
16129  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
16130  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
16131  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
16132  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
16133  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
16134  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
16135  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
16136  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
16137  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
16138  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
16139  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
16140  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
16141  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
16142  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
16143  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
16144  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
16145  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
16146  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
16147  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
16148  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
16149  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
16150  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
16151  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
16152  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
16153  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
16154  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
16155  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
16156  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
16157  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
16158  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
16159  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
16160  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
16161  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
16162  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
16163  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
16164  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
16165  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
16166  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
16167  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
16168  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
16169  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
16170  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
16171  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
16172  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
16173  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
16174  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
16175  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
16176  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
16177  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
16178  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
16179  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
16180  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
16181  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
16182  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
16183  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
16184  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
16185  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
16186  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
16187  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
16188  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
16189  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
16190  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
16191  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
16192  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
16193  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
16194  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
16195  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
16196  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
16197  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
16198  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
16199  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
16200  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
16201  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
16202  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
16203  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
16204  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
16205  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
16206  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
16207  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
16208  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
16209  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
16210  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
16211  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
16212  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
16213  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
16214  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
16215  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
16216  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
16217  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
16218  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
16219  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
16220  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
16221  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
16222  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
16223  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
16224  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
16225  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
16226  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
16227  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
16228  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
16229  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
16230  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
16231  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
16232  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
16233  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
16234  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
16235  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
16236  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
16237  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
16238  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
16239  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
16240  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
16241  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
16242  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
16243  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
16244  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
16245  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
16246  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
16247  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
16248  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
16249  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
16250  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
16251  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
16252  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
16253  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
16254  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
16255  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
16256  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
16257  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
16258  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
16259  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
16260  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
16261  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
16262  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
16263  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
16264  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
16265  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
16266  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
16267  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
16268  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
16269  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
16270  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
16271  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
16272  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
16273  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
16274  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
16275  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
16276  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
16277  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
16278  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
16279  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
16280  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
16281  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
16282  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
16283  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
16284  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
16285  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
16286  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
16287  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
16288  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
16289  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
16290  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
16291  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
16292  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
16293  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
16294  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
16295  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
16296  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
16297  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
16298  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
16299  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
16300  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
16301  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
16302  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
16303  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
16304  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
16305  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
16306  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
16307  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
16308  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
16309  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
16310  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
16311  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
16312  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
16313  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
16314  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
16315  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
16316  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
16317  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
16318  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
16319  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
16320  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
16321  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
16322  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
16323  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
16324  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
16325  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
16326  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
16327  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
16328  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
16329  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
16330  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
16331  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
16332  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
16333  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
16334  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
16335  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
16336  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
16337  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
16338  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
16339  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
16340  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
16341  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
16342  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
16343  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
16344  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
16345  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
16346  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
16347  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
16348  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
16349  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
16350  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
16351  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
16352  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
16353  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
16354  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
16355  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
16356  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
16357  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
16358  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
16359  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
16360  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
16361  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
16362  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
16363  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
16364  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
16365  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
16366  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
16367  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
16368  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
16369  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
16370  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
16371  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
16372  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
16373  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
16374  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
16375  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
16376  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
16377  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
16378  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
16379  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
16380  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
16381  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
16382  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
16383  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
16384  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
16385  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
16386  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
16387  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
16388  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
16389  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
16390  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
16391  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
16392  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
16393  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
16394  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
16395  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
16396  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
16397  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
16398  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
16399  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
16400  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
16401  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
16402  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
16403  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
16404  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
16405  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
16406  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
16407  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
16408  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
16409  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
16410  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
16411  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
16412  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
16413  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
16414  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
16415  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
16416  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
16417  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
16418  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
16419  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
16420  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
16421  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
16422  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
16423  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
16424  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
16425  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
16426  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
16427  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
16428  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
16429  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
16430  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
16431  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
16432  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
16433  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
16434  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
16435  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
16436  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
16437  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
16438  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
16439  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
16440 };
16441 
16447 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
16448 {
16449  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
16450  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
16451  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
16452  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
16453  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
16454  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
16455  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
16456  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
16457  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
16458  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
16459  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
16460  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
16461  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
16462  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
16463  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
16464  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
16465  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
16466  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
16467  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
16468  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
16469  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
16470  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
16471  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
16472  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
16473  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
16474  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
16475  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
16476  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
16477  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
16478  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
16479  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
16480  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
16481  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
16482  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
16483  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
16484  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
16485  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
16486  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
16487  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
16488  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
16489  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
16490  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
16491  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
16492  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
16493  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
16494  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
16495  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
16496  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
16497  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
16498  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
16499  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
16500  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
16501  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
16502  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
16503  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
16504  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
16505  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
16506  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
16507  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
16508  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
16509  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
16510  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
16511  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
16512  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
16513  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
16514  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
16515  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
16516  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
16517  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
16518  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
16519  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
16520  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
16521  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
16522  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
16523  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
16524  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
16525  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
16526  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
16527  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
16528  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
16529  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
16530  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
16531  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
16532  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
16533  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
16534  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
16535  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
16536  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
16537  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
16538  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
16539  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
16540  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
16541  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
16542  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
16543  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
16544  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
16545  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
16546  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
16547  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
16548  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
16549  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
16550  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
16551  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
16552  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
16553  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
16554  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
16555  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
16556  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
16557  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
16558  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
16559  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
16560  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
16561  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
16562  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
16563  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
16564  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
16565  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
16566  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
16567  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
16568  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
16569  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
16570  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
16571  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
16572  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
16573  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
16574  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
16575  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
16576  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
16577  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
16578  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
16579  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
16580  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
16581  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
16582  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
16583  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
16584  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
16585  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
16586  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
16587  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
16588  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
16589  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
16590  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
16591  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
16592  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
16593  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
16594  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
16595  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
16596  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
16597  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
16598  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
16599  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
16600  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
16601  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
16602  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
16603  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
16604  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
16605  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
16606  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
16607  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
16608  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
16609  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
16610  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
16611  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
16612  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
16613  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
16614  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
16615  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
16616  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
16617  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
16618  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
16619  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
16620  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
16621  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
16622  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
16623  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
16624  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
16625  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
16626  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
16627  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
16628  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
16629  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
16630  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
16631  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
16632  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
16633  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
16634  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
16635  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
16636  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
16637  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
16638  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
16639  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
16640  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
16641  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
16642  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
16643  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
16644  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
16645  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
16646  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
16647  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
16648  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
16649  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
16650  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
16651  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
16652  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
16653  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
16654  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
16655  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
16656  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
16657  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
16658  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
16659  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
16660  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
16661  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
16662  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
16663  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
16664  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
16665  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
16666  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
16667  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
16668  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
16669  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
16670  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
16671  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
16672  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
16673  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
16674  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
16675  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
16676  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
16677  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
16678  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
16679  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
16680  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
16681  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
16682  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
16683  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
16684  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
16685  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
16686  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
16687  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
16688  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
16689  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
16690  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
16691  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
16692  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
16693  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
16694  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
16695  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
16696  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
16697  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
16698  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
16699  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
16700  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
16701  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
16702  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
16703  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
16704  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
16705  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
16706  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
16707  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
16708  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
16709  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
16710  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
16711  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
16712  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
16713  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
16714  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
16715  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
16716  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
16717 };
16718 
16724 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
16725 {
16726  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
16727  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
16728  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
16729  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
16730  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
16731  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
16732  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
16733  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
16734  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
16735  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
16736  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
16737  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
16738  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
16739  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
16740  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
16741  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
16742  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
16743  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
16744  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
16745  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
16746  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
16747  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
16748  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
16749  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
16750  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
16751  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
16752  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
16753  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
16754  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
16755  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
16756  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
16757  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
16758  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
16759  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
16760  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
16761  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
16762  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
16763  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
16764  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
16765  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
16766  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
16767  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
16768  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
16769  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
16770  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
16771  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
16772  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
16773  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
16774  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
16775  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
16776  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
16777  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
16778  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
16779  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
16780  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
16781  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
16782  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
16783  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
16784  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
16785  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
16786  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
16787  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
16788  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
16789  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
16790  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
16791  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
16792  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
16793  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
16794  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
16795  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
16796  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
16797  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
16798  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
16799  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
16800  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
16801  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
16802  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
16803  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
16804  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
16805  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
16806  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
16807  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
16808  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
16809  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
16810  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
16811  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
16812  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
16813  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
16814  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
16815  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
16816  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
16817  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
16818  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
16819  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
16820  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
16821  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
16822  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
16823  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
16824  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
16825  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
16826  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
16827  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
16828  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
16829  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
16830  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
16831  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
16832  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
16833  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
16834  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
16835  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
16836  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
16837  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
16838  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
16839  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
16840  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
16841  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
16842  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
16843  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
16844  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
16845  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
16846  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
16847  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
16848  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
16849  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
16850  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
16851  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
16852  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
16853  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
16854  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
16855  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
16856  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
16857  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
16858  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
16859  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
16860  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
16861  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
16862  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
16863  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
16864  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
16865  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
16866  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
16867  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
16868  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
16869  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
16870  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
16871  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
16872  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
16873  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
16874  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
16875  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
16876  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
16877  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
16878  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
16879  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
16880  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
16881  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
16882  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
16883  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
16884  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
16885  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
16886  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
16887  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
16888  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
16889  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
16890  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
16891  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
16892  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
16893  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
16894  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
16895  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
16896  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
16897  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
16898  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
16899  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
16900  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
16901  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
16902  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
16903  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
16904  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
16905  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
16906  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
16907  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
16908  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
16909  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
16910  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
16911  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
16912  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
16913  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
16914  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
16915  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
16916  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
16917  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
16918  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
16919  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
16920  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
16921  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
16922  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
16923  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
16924  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
16925  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
16926  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
16927  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
16928  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
16929  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
16930  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
16931  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
16932  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
16933  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
16934  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
16935  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
16936  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
16937  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
16938  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
16939  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
16940  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
16941  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
16942  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
16943  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
16944  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
16945  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
16946  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
16947  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
16948  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
16949  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
16950  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
16951  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
16952  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
16953  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
16954  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
16955  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
16956  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
16957  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
16958  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
16959  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
16960  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
16961  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
16962  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
16963  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
16964  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
16965  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
16966  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
16967  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
16968  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
16969  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
16970  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
16971  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
16972  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
16973  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
16974  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
16975  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
16976  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
16977  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
16978  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
16979  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
16980  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
16981  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
16982  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
16983  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
16984  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
16985  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
16986  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
16987  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
16988  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
16989  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
16990  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
16991  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
16992  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
16993  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
16994  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
16995  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
16996  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
16997  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
16998  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
16999  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
17000  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
17001  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
17002  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
17003  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
17004  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
17005  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
17006  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
17007  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
17008  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
17009  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
17010  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
17011  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
17012  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
17013  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
17014  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
17015  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
17016  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
17017  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
17018  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
17019  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
17020  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
17021  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
17022  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
17023  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
17024  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
17025  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
17026  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
17027  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
17028  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
17029  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
17030  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
17031  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
17032  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
17033  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
17034  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
17035  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
17036  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
17037  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
17038  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
17039  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
17040  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
17041  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
17042  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
17043  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
17044  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
17045  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
17046  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
17047  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
17048  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
17049  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
17050  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
17051  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
17052  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
17053  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
17054  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
17055  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
17056  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
17057  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
17058  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
17059  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
17060  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
17061  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
17062  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
17063  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
17064  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
17065  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
17066  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
17067  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
17068  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
17069  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
17070  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
17071  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
17072  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
17073  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
17074  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
17075  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
17076  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
17077  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
17078  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
17079  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
17080  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
17081  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
17082  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
17083  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
17084  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
17085  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
17086  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
17087  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
17088  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
17089  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
17090  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
17091  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
17092  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
17093  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
17094  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
17095  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
17096  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
17097  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
17098  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
17099  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
17100  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
17101  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
17102  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
17103  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
17104  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
17105  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
17106  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
17107  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
17108  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
17109  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
17110  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
17111  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
17112  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
17113  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
17114  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
17115  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
17116  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
17117  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
17118  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
17119  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
17120  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
17121  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
17122  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
17123  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
17124  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
17125  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
17126  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
17127  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
17128  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
17129  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
17130  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
17131  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
17132  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
17133  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
17134  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
17135  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
17136  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
17137  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
17138  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
17139  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
17140  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
17141  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
17142  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
17143  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
17144  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
17145  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
17146  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
17147  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
17148  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
17149  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
17150  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
17151  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
17152  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
17153  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
17154  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
17155  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
17156  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
17157  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
17158  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
17159  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
17160  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
17161  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
17162  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
17163  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
17164  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
17165  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
17166  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
17167  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
17168  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
17169  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
17170  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
17171  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
17172  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
17173  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
17174  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
17175  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
17176  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
17177  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
17178  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
17179  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
17180  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
17181  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
17182  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
17183  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
17184  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
17185  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
17186  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
17187  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
17188  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
17189  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
17190  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
17191  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
17192  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
17193  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
17194  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
17195  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
17196  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
17197  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
17198  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
17199  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
17200  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
17201  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
17202  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
17203  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
17204  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
17205  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
17206  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
17207  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
17208  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
17209  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
17210  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
17211  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
17212  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
17213  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
17214  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
17215  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
17216  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
17217  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
17218  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
17219  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
17220  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
17221  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
17222  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
17223  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
17224  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
17225  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
17226  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
17227  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
17228  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
17229  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
17230  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
17231  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
17232  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
17233  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
17234  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
17235  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
17236  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
17237  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
17238 };
17239 
17245 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
17246 {
17247  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
17248  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
17249  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
17250  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
17251  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
17252  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
17253  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
17254  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
17255  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
17256  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
17257  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
17258  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
17259  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
17260  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
17261  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
17262  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
17263  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
17264  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
17265  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
17266  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
17267  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
17268  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
17269  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
17270  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
17271  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
17272  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
17273  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
17274  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
17275  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
17276  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
17277  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
17278  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
17279  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
17280  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
17281  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
17282  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
17283  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
17284  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
17285  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
17286  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
17287  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
17288  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
17289  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
17290  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
17291  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
17292  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
17293  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
17294  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
17295  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
17296  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
17297  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
17298  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
17299  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
17300  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
17301  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
17302  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
17303  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
17304  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
17305  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
17306  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
17307  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
17308  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
17309  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
17310  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
17311  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
17312  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
17313  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
17314  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
17315  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
17316  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
17317  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
17318  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
17319  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
17320  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
17321  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
17322  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
17323  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
17324  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
17325  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
17326  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
17327  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
17328  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
17329  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
17330  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
17331  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
17332  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
17333  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
17334  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
17335  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
17336  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
17337  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
17338  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
17339  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
17340  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
17341  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
17342  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
17343  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
17344  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
17345  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
17346  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
17347  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
17348  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
17349  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
17350  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
17351  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
17352  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
17353  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
17354  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
17355  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
17356  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
17357  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
17358  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
17359  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
17360  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
17361  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
17362  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
17363  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
17364  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
17365  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
17366  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
17367  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
17368  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
17369  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
17370  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
17371  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
17372  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
17373  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
17374  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
17375  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
17376  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
17377  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
17378  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
17379  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
17380  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
17381  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
17382  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
17383  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
17384  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
17385  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
17386  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
17387  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
17388  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
17389  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
17390  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
17391  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
17392  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
17393  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
17394  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
17395  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
17396  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
17397  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
17398  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
17399  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
17400  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
17401  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
17402  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
17403  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
17404  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
17405  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
17406  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
17407  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
17408  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
17409  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
17410  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
17411  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
17412  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
17413  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
17414  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
17415  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
17416  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
17417  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
17418  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
17419  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
17420  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
17421  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
17422  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
17423  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
17424  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
17425  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
17426  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
17427  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
17428  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
17429  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
17430  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
17431  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
17432  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
17433  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
17434  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
17435  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
17436  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
17437  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
17438  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
17439  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
17440  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
17441  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
17442  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
17443  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
17444  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
17445  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
17446  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
17447  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
17448  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
17449  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
17450  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
17451  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
17452  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
17453  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
17454  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
17455  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
17456  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
17457  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
17458  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
17459  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
17460  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
17461  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
17462  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
17463  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
17464  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
17465  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
17466  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
17467  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
17468  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
17469  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
17470  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
17471  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
17472  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
17473  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
17474  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
17475  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
17476  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
17477  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
17478  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
17479  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
17480  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
17481  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
17482  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
17483  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
17484  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
17485  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
17486  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
17487  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
17488  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
17489  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
17490  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
17491  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
17492  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
17493  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
17494  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
17495  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
17496  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
17497  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
17498  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
17499  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
17500  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
17501  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
17502  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
17503  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
17504  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
17505  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
17506  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
17507  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
17508  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
17509  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
17510  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
17511  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
17512  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
17513  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
17514  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
17515  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
17516  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
17517  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
17518  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
17519  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
17520  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
17521  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
17522  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
17523  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
17524  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
17525  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
17526  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
17527  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
17528  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
17529  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
17530  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
17531  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
17532  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
17533  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
17534  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
17535  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
17536  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
17537  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
17538  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
17539  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
17540  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
17541  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
17542  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
17543  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
17544  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
17545  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
17546  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
17547  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
17548  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
17549 };
17550 
17556 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
17557 {
17558  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17559  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17560  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17561  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17562  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17563  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17564  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17565  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17566  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17567  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17568  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17569  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17570  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17571  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17572  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17573  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17574 };
17575 
17581 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
17582 {
17583  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
17584  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
17585  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
17586  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
17587  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
17588  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
17589  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
17590  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
17591  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
17592  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
17593  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
17594  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
17595  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
17596  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
17597  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
17598  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
17599  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
17600  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
17601  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
17602  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
17603  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
17604  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
17605  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
17606  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
17607  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
17608  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
17609  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
17610  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
17611  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
17612  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
17613  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
17614  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
17615  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
17616  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
17617  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
17618  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
17619  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
17620  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
17621 };
17622 
17628 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
17629 {
17630  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17631  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17632  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17633  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17634  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17635  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17636  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17637  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17638  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17639  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17640  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17641  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17642  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17643  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17644  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17645  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17646  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
17647  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
17648  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
17649  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
17650  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
17651  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
17652  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
17653  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
17654  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
17655  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
17656  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
17657  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
17658  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
17659  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
17660  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
17661  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
17662  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
17663  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
17664  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
17665  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
17666  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
17667  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
17668  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
17669  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
17670  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
17671  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
17672  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
17673  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
17674  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
17675  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
17676  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
17677  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
17678  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
17679  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
17680  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
17681  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
17682  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
17683  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
17684  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
17685  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
17686  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
17687  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
17688  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
17689  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
17690  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
17691  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
17692  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
17693  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
17694  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
17695  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
17696  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
17697  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
17698  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
17699  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
17700  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
17701  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
17702  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
17703  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
17704  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
17705  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
17706  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
17707  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
17708  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
17709  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
17710  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
17711  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
17712  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
17713  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
17714 };
17715 
17721 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
17722 {
17723  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17724  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17725  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17726  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17727  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17728  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17729  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17730  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17731  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17732  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17733 };
17734 
17740 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
17741 {
17742  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
17743  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
17744  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
17745  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
17746  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
17747  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
17748  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
17749  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
17750  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
17751  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
17752  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
17753  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
17754  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
17755  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
17756  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
17757  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
17758  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
17759  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
17760  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
17761  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
17762  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
17763  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
17764  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
17765  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
17766  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
17767  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
17768  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
17769  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
17770  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
17771  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
17772  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
17773  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
17774  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
17775  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
17776  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
17777  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
17778  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
17779  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
17780 };
17781 
17787 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
17788 {
17789  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17790  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17791  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17792  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17793  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17794  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17795  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17796  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17797  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17798  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17799  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17800  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17801  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17802  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17803  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17804  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17805  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
17806  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
17807  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
17808  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
17809  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
17810  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
17811  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
17812  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
17813  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
17814  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
17815  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
17816  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
17817  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
17818  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
17819  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
17820  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
17821  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
17822  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
17823  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
17824  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
17825  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
17826  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
17827  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
17828  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
17829  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
17830  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
17831  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
17832  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
17833  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
17834  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
17835  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
17836  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
17837  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
17838  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
17839  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
17840  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
17841  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
17842  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
17843  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
17844  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
17845  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
17846  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
17847  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
17848  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
17849  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
17850  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
17851  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
17852  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
17853  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
17854  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
17855  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
17856  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
17857  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
17858  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
17859  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
17860  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
17861  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
17862  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
17863  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
17864  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
17865  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
17866  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
17867  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
17868  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
17869  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
17870  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
17871  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
17872  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
17873 };
17874 
17880 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS] =
17881 {
17882  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_0_CHECKER_TYPE,
17883  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_0_WIDTH },
17884  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_1_CHECKER_TYPE,
17885  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_1_WIDTH },
17886  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_2_CHECKER_TYPE,
17887  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_2_WIDTH },
17888  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_3_CHECKER_TYPE,
17889  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_3_WIDTH },
17890  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_4_CHECKER_TYPE,
17891  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_4_WIDTH },
17892  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_5_CHECKER_TYPE,
17893  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_5_WIDTH },
17894  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_6_CHECKER_TYPE,
17895  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_6_WIDTH },
17896  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_7_CHECKER_TYPE,
17897  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_7_WIDTH },
17898  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_8_CHECKER_TYPE,
17899  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_8_WIDTH },
17900  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_9_CHECKER_TYPE,
17901  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_9_WIDTH },
17902  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_10_CHECKER_TYPE,
17903  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_10_WIDTH },
17904  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_11_CHECKER_TYPE,
17905  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_11_WIDTH },
17906  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_12_CHECKER_TYPE,
17907  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_12_WIDTH },
17908  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_13_CHECKER_TYPE,
17909  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_13_WIDTH },
17910  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_14_CHECKER_TYPE,
17911  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_14_WIDTH },
17912  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_15_CHECKER_TYPE,
17913  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_15_WIDTH },
17914  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_16_CHECKER_TYPE,
17915  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_16_WIDTH },
17916  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_17_CHECKER_TYPE,
17917  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_17_WIDTH },
17918  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_18_CHECKER_TYPE,
17919  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_18_WIDTH },
17920  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_19_CHECKER_TYPE,
17921  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_19_WIDTH },
17922  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_20_CHECKER_TYPE,
17923  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_20_WIDTH },
17924  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_21_CHECKER_TYPE,
17925  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_21_WIDTH },
17926  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_22_CHECKER_TYPE,
17927  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_22_WIDTH },
17928  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_23_CHECKER_TYPE,
17929  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_23_WIDTH },
17930  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_24_CHECKER_TYPE,
17931  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_24_WIDTH },
17932  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_25_CHECKER_TYPE,
17933  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_25_WIDTH },
17934  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_26_CHECKER_TYPE,
17935  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_26_WIDTH },
17936  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_27_CHECKER_TYPE,
17937  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_27_WIDTH },
17938  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_28_CHECKER_TYPE,
17939  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_28_WIDTH },
17940  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_29_CHECKER_TYPE,
17941  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_29_WIDTH },
17942  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_30_CHECKER_TYPE,
17943  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_30_WIDTH },
17944  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_31_CHECKER_TYPE,
17945  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_31_WIDTH },
17946  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_32_CHECKER_TYPE,
17947  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_32_WIDTH },
17948  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_33_CHECKER_TYPE,
17949  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_33_WIDTH },
17950  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_34_CHECKER_TYPE,
17951  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_34_WIDTH },
17952  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_35_CHECKER_TYPE,
17953  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_35_WIDTH },
17954  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_36_CHECKER_TYPE,
17955  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_36_WIDTH },
17956  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_37_CHECKER_TYPE,
17957  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_37_WIDTH },
17958  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_38_CHECKER_TYPE,
17959  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_38_WIDTH },
17960  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_39_CHECKER_TYPE,
17961  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_39_WIDTH },
17962  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_40_CHECKER_TYPE,
17963  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_40_WIDTH },
17964  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_41_CHECKER_TYPE,
17965  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_41_WIDTH },
17966  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_42_CHECKER_TYPE,
17967  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_42_WIDTH },
17968  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_43_CHECKER_TYPE,
17969  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_43_WIDTH },
17970  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_44_CHECKER_TYPE,
17971  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_44_WIDTH },
17972  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_45_CHECKER_TYPE,
17973  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_45_WIDTH },
17974  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_46_CHECKER_TYPE,
17975  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_46_WIDTH },
17976  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_47_CHECKER_TYPE,
17977  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_47_WIDTH },
17978  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_48_CHECKER_TYPE,
17979  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_48_WIDTH },
17980  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_49_CHECKER_TYPE,
17981  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_49_WIDTH },
17982  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_50_CHECKER_TYPE,
17983  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_50_WIDTH },
17984  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_51_CHECKER_TYPE,
17985  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_51_WIDTH },
17986  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_52_CHECKER_TYPE,
17987  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_52_WIDTH },
17988  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_53_CHECKER_TYPE,
17989  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_53_WIDTH },
17990  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_54_CHECKER_TYPE,
17991  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_54_WIDTH },
17992  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_55_CHECKER_TYPE,
17993  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_55_WIDTH },
17994  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_56_CHECKER_TYPE,
17995  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_56_WIDTH },
17996  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_57_CHECKER_TYPE,
17997  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_57_WIDTH },
17998  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_58_CHECKER_TYPE,
17999  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_58_WIDTH },
18000  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_59_CHECKER_TYPE,
18001  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_59_WIDTH },
18002  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_60_CHECKER_TYPE,
18003  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_60_WIDTH },
18004  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_61_CHECKER_TYPE,
18005  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_61_WIDTH },
18006  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_62_CHECKER_TYPE,
18007  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_62_WIDTH },
18008  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_63_CHECKER_TYPE,
18009  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_63_WIDTH },
18010  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_64_CHECKER_TYPE,
18011  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_64_WIDTH },
18012  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_65_CHECKER_TYPE,
18013  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_65_WIDTH },
18014  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_66_CHECKER_TYPE,
18015  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_66_WIDTH },
18016  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_67_CHECKER_TYPE,
18017  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_67_WIDTH },
18018  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_68_CHECKER_TYPE,
18019  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_68_WIDTH },
18020  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_69_CHECKER_TYPE,
18021  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_69_WIDTH },
18022  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_70_CHECKER_TYPE,
18023  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_70_WIDTH },
18024  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_71_CHECKER_TYPE,
18025  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_71_WIDTH },
18026  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_72_CHECKER_TYPE,
18027  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_72_WIDTH },
18028  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_73_CHECKER_TYPE,
18029  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_73_WIDTH },
18030  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_74_CHECKER_TYPE,
18031  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_74_WIDTH },
18032  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_75_CHECKER_TYPE,
18033  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_75_WIDTH },
18034  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_76_CHECKER_TYPE,
18035  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_76_WIDTH },
18036  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_77_CHECKER_TYPE,
18037  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_77_WIDTH },
18038  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_78_CHECKER_TYPE,
18039  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_78_WIDTH },
18040  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_79_CHECKER_TYPE,
18041  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_79_WIDTH },
18042  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_80_CHECKER_TYPE,
18043  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_80_WIDTH },
18044 };
18045 
18051 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
18052 {
18053  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
18054  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
18055  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
18056  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
18057  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
18058  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
18059  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
18060  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
18061  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
18062  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
18063  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
18064  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
18065  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
18066  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
18067  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
18068  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
18069  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
18070  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
18071  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
18072  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
18073  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
18074  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
18075  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
18076  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
18077  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
18078  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
18079  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
18080  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
18081  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
18082  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
18083  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
18084  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
18085  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
18086  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
18087  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
18088  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
18089  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
18090  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
18091  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
18092  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
18093  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
18094  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
18095  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
18096  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
18097  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
18098  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
18099  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
18100  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
18101  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
18102  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
18103  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
18104  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
18105  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
18106  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
18107  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
18108  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
18109  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
18110  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
18111  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
18112  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
18113  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
18114  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
18115  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
18116  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
18117  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
18118  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
18119  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
18120  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
18121  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
18122  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
18123  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
18124  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
18125  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
18126  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
18127  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
18128  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
18129  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
18130  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
18131  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
18132  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
18133  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
18134  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
18135  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
18136  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
18137  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
18138  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
18139  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
18140  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
18141  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
18142  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
18143  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
18144  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
18145  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
18146  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
18147  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
18148  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
18149  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
18150  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
18151  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
18152  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
18153  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
18154  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
18155  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
18156  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
18157  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
18158  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
18159  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
18160  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
18161  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
18162  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
18163  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
18164  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
18165  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
18166  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
18167  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
18168  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
18169  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
18170  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
18171  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
18172  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
18173  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
18174  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
18175  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
18176  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
18177  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
18178  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
18179  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
18180  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
18181  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
18182  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
18183  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
18184  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
18185  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
18186  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
18187  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
18188  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
18189  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
18190  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
18191  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
18192  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
18193  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
18194  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
18195  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
18196  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
18197  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
18198  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
18199  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
18200  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
18201  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
18202  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
18203  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
18204  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
18205  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
18206  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
18207  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
18208  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
18209  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
18210  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
18211  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
18212  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
18213  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
18214  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
18215  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
18216  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
18217  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
18218  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
18219  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
18220  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
18221  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
18222  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
18223  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
18224  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
18225  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
18226  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
18227  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
18228  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
18229  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
18230  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
18231  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
18232  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
18233  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
18234  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
18235  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
18236  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
18237  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
18238  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
18239  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
18240  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
18241  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
18242  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
18243  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
18244  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
18245  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
18246  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
18247  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
18248  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
18249  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
18250  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
18251  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
18252  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
18253  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_CHECKER_TYPE,
18254  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
18255  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_CHECKER_TYPE,
18256  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
18257  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_CHECKER_TYPE,
18258  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
18259  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_CHECKER_TYPE,
18260  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
18261  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_CHECKER_TYPE,
18262  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
18263  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_CHECKER_TYPE,
18264  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
18265  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_CHECKER_TYPE,
18266  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
18267  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_CHECKER_TYPE,
18268  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
18269  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_CHECKER_TYPE,
18270  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
18271  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_CHECKER_TYPE,
18272  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
18273  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_CHECKER_TYPE,
18274  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
18275  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_CHECKER_TYPE,
18276  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
18277  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_CHECKER_TYPE,
18278  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
18279  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_CHECKER_TYPE,
18280  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
18281  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_CHECKER_TYPE,
18282  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
18283  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_CHECKER_TYPE,
18284  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
18285  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_CHECKER_TYPE,
18286  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
18287  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_CHECKER_TYPE,
18288  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
18289  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_CHECKER_TYPE,
18290  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
18291  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_CHECKER_TYPE,
18292  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
18293  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_CHECKER_TYPE,
18294  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
18295  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_121_CHECKER_TYPE,
18296  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_121_WIDTH },
18297  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_122_CHECKER_TYPE,
18298  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_122_WIDTH },
18299  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_123_CHECKER_TYPE,
18300  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_123_WIDTH },
18301  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_124_CHECKER_TYPE,
18302  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_124_WIDTH },
18303  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_125_CHECKER_TYPE,
18304  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_125_WIDTH },
18305  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_126_CHECKER_TYPE,
18306  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_126_WIDTH },
18307  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_127_CHECKER_TYPE,
18308  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_127_WIDTH },
18309  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_128_CHECKER_TYPE,
18310  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_128_WIDTH },
18311  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_129_CHECKER_TYPE,
18312  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_129_WIDTH },
18313  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_130_CHECKER_TYPE,
18314  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_130_WIDTH },
18315  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_131_CHECKER_TYPE,
18316  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_131_WIDTH },
18317  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_132_CHECKER_TYPE,
18318  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_132_WIDTH },
18319  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_133_CHECKER_TYPE,
18320  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_133_WIDTH },
18321  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_134_CHECKER_TYPE,
18322  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_134_WIDTH },
18323 };
18324 
18330 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS] =
18331 {
18332  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_0_CHECKER_TYPE,
18333  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_0_WIDTH },
18334  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_1_CHECKER_TYPE,
18335  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_1_WIDTH },
18336  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_2_CHECKER_TYPE,
18337  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_2_WIDTH },
18338  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_3_CHECKER_TYPE,
18339  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_3_WIDTH },
18340  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_4_CHECKER_TYPE,
18341  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_4_WIDTH },
18342  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_5_CHECKER_TYPE,
18343  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_5_WIDTH },
18344  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_6_CHECKER_TYPE,
18345  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_6_WIDTH },
18346  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_7_CHECKER_TYPE,
18347  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_7_WIDTH },
18348  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_8_CHECKER_TYPE,
18349  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_8_WIDTH },
18350  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_9_CHECKER_TYPE,
18351  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_9_WIDTH },
18352  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_10_CHECKER_TYPE,
18353  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_10_WIDTH },
18354  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_11_CHECKER_TYPE,
18355  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_11_WIDTH },
18356  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_12_CHECKER_TYPE,
18357  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_12_WIDTH },
18358  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_13_CHECKER_TYPE,
18359  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_13_WIDTH },
18360  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_14_CHECKER_TYPE,
18361  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_14_WIDTH },
18362  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_15_CHECKER_TYPE,
18363  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_15_WIDTH },
18364  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_16_CHECKER_TYPE,
18365  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_16_WIDTH },
18366  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_17_CHECKER_TYPE,
18367  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_17_WIDTH },
18368  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_18_CHECKER_TYPE,
18369  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_18_WIDTH },
18370  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_19_CHECKER_TYPE,
18371  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_19_WIDTH },
18372  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_20_CHECKER_TYPE,
18373  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_20_WIDTH },
18374  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_21_CHECKER_TYPE,
18375  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_21_WIDTH },
18376  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_22_CHECKER_TYPE,
18377  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_22_WIDTH },
18378  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_23_CHECKER_TYPE,
18379  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_23_WIDTH },
18380  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_24_CHECKER_TYPE,
18381  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_24_WIDTH },
18382  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_25_CHECKER_TYPE,
18383  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_25_WIDTH },
18384  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_26_CHECKER_TYPE,
18385  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_26_WIDTH },
18386  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_27_CHECKER_TYPE,
18387  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_27_WIDTH },
18388  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_28_CHECKER_TYPE,
18389  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_28_WIDTH },
18390  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_29_CHECKER_TYPE,
18391  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_29_WIDTH },
18392  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_30_CHECKER_TYPE,
18393  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_30_WIDTH },
18394  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_31_CHECKER_TYPE,
18395  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_31_WIDTH },
18396  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_32_CHECKER_TYPE,
18397  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_32_WIDTH },
18398  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_33_CHECKER_TYPE,
18399  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_33_WIDTH },
18400  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_34_CHECKER_TYPE,
18401  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_34_WIDTH },
18402  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_35_CHECKER_TYPE,
18403  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_35_WIDTH },
18404  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_36_CHECKER_TYPE,
18405  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_36_WIDTH },
18406  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_37_CHECKER_TYPE,
18407  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_37_WIDTH },
18408  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_38_CHECKER_TYPE,
18409  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_38_WIDTH },
18410  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_39_CHECKER_TYPE,
18411  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_39_WIDTH },
18412  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_40_CHECKER_TYPE,
18413  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_40_WIDTH },
18414  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_41_CHECKER_TYPE,
18415  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_41_WIDTH },
18416  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_42_CHECKER_TYPE,
18417  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_42_WIDTH },
18418  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_43_CHECKER_TYPE,
18419  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_43_WIDTH },
18420  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_44_CHECKER_TYPE,
18421  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_44_WIDTH },
18422  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_45_CHECKER_TYPE,
18423  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_45_WIDTH },
18424  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_46_CHECKER_TYPE,
18425  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_46_WIDTH },
18426  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_47_CHECKER_TYPE,
18427  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_47_WIDTH },
18428  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_48_CHECKER_TYPE,
18429  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_48_WIDTH },
18430  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_49_CHECKER_TYPE,
18431  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_49_WIDTH },
18432  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_50_CHECKER_TYPE,
18433  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_50_WIDTH },
18434  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_51_CHECKER_TYPE,
18435  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_51_WIDTH },
18436  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_52_CHECKER_TYPE,
18437  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_52_WIDTH },
18438  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_53_CHECKER_TYPE,
18439  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_53_WIDTH },
18440  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_54_CHECKER_TYPE,
18441  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_54_WIDTH },
18442  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_55_CHECKER_TYPE,
18443  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_55_WIDTH },
18444  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_56_CHECKER_TYPE,
18445  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_56_WIDTH },
18446  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_57_CHECKER_TYPE,
18447  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_57_WIDTH },
18448  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_58_CHECKER_TYPE,
18449  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_58_WIDTH },
18450  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_59_CHECKER_TYPE,
18451  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_59_WIDTH },
18452  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_60_CHECKER_TYPE,
18453  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_60_WIDTH },
18454  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_61_CHECKER_TYPE,
18455  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_61_WIDTH },
18456  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_62_CHECKER_TYPE,
18457  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_62_WIDTH },
18458  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_63_CHECKER_TYPE,
18459  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_63_WIDTH },
18460  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_64_CHECKER_TYPE,
18461  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_64_WIDTH },
18462  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_65_CHECKER_TYPE,
18463  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_65_WIDTH },
18464  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_66_CHECKER_TYPE,
18465  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_66_WIDTH },
18466  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_67_CHECKER_TYPE,
18467  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_67_WIDTH },
18468  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_68_CHECKER_TYPE,
18469  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_68_WIDTH },
18470  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_69_CHECKER_TYPE,
18471  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_69_WIDTH },
18472  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_70_CHECKER_TYPE,
18473  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_70_WIDTH },
18474  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_71_CHECKER_TYPE,
18475  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_71_WIDTH },
18476  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_72_CHECKER_TYPE,
18477  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_72_WIDTH },
18478  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_73_CHECKER_TYPE,
18479  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_73_WIDTH },
18480  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_74_CHECKER_TYPE,
18481  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_74_WIDTH },
18482  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_75_CHECKER_TYPE,
18483  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_75_WIDTH },
18484  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_76_CHECKER_TYPE,
18485  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_76_WIDTH },
18486  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_77_CHECKER_TYPE,
18487  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_77_WIDTH },
18488  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_78_CHECKER_TYPE,
18489  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_78_WIDTH },
18490  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_79_CHECKER_TYPE,
18491  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_79_WIDTH },
18492  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_80_CHECKER_TYPE,
18493  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_80_WIDTH },
18494  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_81_CHECKER_TYPE,
18495  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_81_WIDTH },
18496  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_82_CHECKER_TYPE,
18497  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_82_WIDTH },
18498  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_83_CHECKER_TYPE,
18499  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_83_WIDTH },
18500  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_84_CHECKER_TYPE,
18501  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_84_WIDTH },
18502  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_85_CHECKER_TYPE,
18503  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_85_WIDTH },
18504  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_86_CHECKER_TYPE,
18505  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_86_WIDTH },
18506  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_87_CHECKER_TYPE,
18507  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_87_WIDTH },
18508  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_88_CHECKER_TYPE,
18509  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_88_WIDTH },
18510  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_89_CHECKER_TYPE,
18511  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_89_WIDTH },
18512  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_90_CHECKER_TYPE,
18513  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_90_WIDTH },
18514  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_91_CHECKER_TYPE,
18515  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_91_WIDTH },
18516  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_92_CHECKER_TYPE,
18517  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_92_WIDTH },
18518  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_93_CHECKER_TYPE,
18519  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_93_WIDTH },
18520  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_94_CHECKER_TYPE,
18521  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_94_WIDTH },
18522  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_95_CHECKER_TYPE,
18523  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_95_WIDTH },
18524  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_96_CHECKER_TYPE,
18525  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_96_WIDTH },
18526  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_97_CHECKER_TYPE,
18527  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_97_WIDTH },
18528  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_98_CHECKER_TYPE,
18529  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_98_WIDTH },
18530  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_99_CHECKER_TYPE,
18531  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_99_WIDTH },
18532  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_100_CHECKER_TYPE,
18533  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_100_WIDTH },
18534 };
18535 
18541 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
18542 {
18543  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
18544  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
18545  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
18546  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
18547  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
18548  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
18549  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
18550  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
18551  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
18552  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
18553  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
18554  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
18555 };
18556 
18562 {
18563  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
18564  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
18565  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
18566  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
18567  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
18568  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
18569  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
18570  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
18571  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
18572  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
18573  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
18574  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
18575  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
18576  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
18577  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
18578  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
18579  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
18580  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
18581  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
18582  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
18583  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
18584 };
18585 
18591 static const SDL_GrpChkConfig_t SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] =
18592 {
18593  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
18594  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
18595  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
18596  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
18597 };
18598 
18604 {
18605  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20718000u,
18606  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
18607  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
18608 };
18609 
18615 static const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
18616 {
18617  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
18618  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
18619 };
18620 
18626 {
18627  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0020708000u,
18628  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
18629  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
18630 };
18631 
18637 static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
18638 {
18639  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
18640  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
18641 };
18642 
18648 {
18649  { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID, 0u,
18650  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
18651  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
18652 };
18653 
18659 {
18660  { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID, 0u,
18661  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
18662  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
18663 };
18664 
18670 {
18671  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_CONFIG_RAM_ID, 0u,
18672  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_CONFIG_RAM_SIZE, 4u,
18673  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
18674  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_STATE_RAM_ID, 0u,
18675  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_STATE_RAM_SIZE, 4u,
18676  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
18677  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F0_RAM_ID, 0u,
18678  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F0_RAM_SIZE, 4u,
18679  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
18680  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F1_RAM_ID, 0u,
18681  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F1_RAM_SIZE, 4u,
18682  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
18683  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
18684  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F0_RAM_SIZE, 4u,
18685  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
18686  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
18687  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F1_RAM_SIZE, 4u,
18688  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
18689  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
18690  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
18691  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
18692  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STST0_RAM_ID, 0u,
18693  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STST0_RAM_SIZE, 4u,
18694  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
18695  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STSR0_RAM_ID, 0u,
18696  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STSR0_RAM_SIZE, 4u,
18697  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
18698  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
18699  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
18700  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
18701  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_STATREG_SR_SPRAM_40X128_SWW_SR_RAM_ID, 0u,
18702  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_STATREG_SR_SPRAM_40X128_SWW_SR_RAM_SIZE, 4u,
18703  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_STATREG_SR_SPRAM_40X128_SWW_SR_ROW_WIDTH, ((bool)false) },
18704  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_COMMON_IM_TPRAM_248X34_SWW_SR_RAM_ID, 0u,
18705  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_COMMON_IM_TPRAM_248X34_SWW_SR_RAM_SIZE, 4u,
18706  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_COMMON_IM_TPRAM_248X34_SWW_SR_ROW_WIDTH, ((bool)false) },
18707 };
18708 
18714 {
18715  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
18716  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
18717  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18718  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
18719  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
18720  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18721  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
18722  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
18723  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18724  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
18725  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
18726  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18727  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
18728  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
18729  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18730  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
18731  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
18732  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18733  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
18734  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
18735  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18736  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
18737  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
18738  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18739  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
18740  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
18741  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18742  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
18743  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
18744  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18745  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
18746  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
18747  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18748  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
18749  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
18750  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18751  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
18752  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
18753  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18754  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
18755  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
18756  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18757  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
18758  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
18759  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18760  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
18761  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
18762  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18763  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
18764  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
18765  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18766  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
18767  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
18768  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18769  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
18770  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
18771  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18772  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
18773  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
18774  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18775  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
18776  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
18777  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18778  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
18779  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
18780  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18781  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
18782  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
18783  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18784  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
18785  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
18786  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18787  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
18788  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
18789  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18790  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
18791  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
18792  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18793  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
18794  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
18795  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18796 };
18797 
18803 {
18804  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
18805  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
18806  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18807  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
18808  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
18809  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18810  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
18811  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
18812  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18813  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
18814  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
18815  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18816  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
18817  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
18818  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18819  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
18820  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
18821  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18822  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
18823  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
18824  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18825  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
18826  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
18827  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18828  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
18829  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
18830  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18831  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
18832  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
18833  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18834  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
18835  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
18836  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18837  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
18838  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
18839  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18840  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
18841  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
18842  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18843  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
18844  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
18845  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18846  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
18847  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
18848  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18849  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
18850  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
18851  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18852  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
18853  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
18854  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18855  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
18856  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
18857  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18858  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
18859  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
18860  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18861  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
18862  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
18863  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18864  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
18865  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
18866  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18867  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
18868  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
18869  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18870  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
18871  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
18872  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18873  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
18874  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
18875  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18876  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
18877  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
18878  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18879  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
18880  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
18881  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18882  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
18883  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
18884  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18885 };
18886 
18892 {
18893  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
18894  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
18895  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18896  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
18897  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
18898  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18899  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
18900  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
18901  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18902  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
18903  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
18904  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18905  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
18906  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
18907  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18908  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
18909  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
18910  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18911  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
18912  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
18913  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18914  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
18915  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
18916  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18917  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
18918  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
18919  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18920  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
18921  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
18922  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18923  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
18924  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
18925  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18926  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
18927  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
18928  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18929  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
18930  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
18931  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18932  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
18933  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
18934  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18935  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
18936  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
18937  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18938  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
18939  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
18940  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18941  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
18942  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
18943  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18944  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
18945  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
18946  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18947  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
18948  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
18949  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18950  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
18951  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
18952  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18953  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
18954  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
18955  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18956  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
18957  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
18958  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18959  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
18960  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
18961  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18962  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
18963  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
18964  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18965  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
18966  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
18967  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18968  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
18969  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
18970  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18971  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
18972  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
18973  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18974 };
18975 
18981 {
18982  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
18983  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
18984  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18985  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
18986  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
18987  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18988  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
18989  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
18990  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18991  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
18992  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
18993  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18994  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
18995  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
18996  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
18997  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
18998  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
18999  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19000  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
19001  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
19002  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19003  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
19004  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
19005  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19006  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
19007  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
19008  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19009  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
19010  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
19011  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19012  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
19013  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
19014  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19015  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
19016  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
19017  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19018  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
19019  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
19020  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19021  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
19022  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
19023  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19024  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
19025  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
19026  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19027  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
19028  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
19029  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19030  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
19031  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
19032  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19033  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
19034  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
19035  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19036  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
19037  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
19038  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19039  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
19040  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
19041  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19042  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
19043  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
19044  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19045  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
19046  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
19047  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19048  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
19049  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
19050  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19051  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
19052  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
19053  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19054  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
19055  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
19056  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19057  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
19058  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
19059  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19060  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
19061  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
19062  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19063 };
19064 
19070 {
19071  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
19072  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
19073  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19074  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
19075  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
19076  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19077  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
19078  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
19079  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19080  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
19081  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
19082  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19083  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID, 0u,
19084  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_SIZE, 4u,
19085  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19086  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID, 0u,
19087  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_SIZE, 4u,
19088  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19089  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID, 0u,
19090  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_SIZE, 4u,
19091  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19092  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID, 0u,
19093  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_SIZE, 4u,
19094  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19095  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID, 0u,
19096  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_SIZE, 4u,
19097  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19098  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID, 0u,
19099  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_SIZE, 4u,
19100  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19101  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID, 0u,
19102  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_SIZE, 4u,
19103  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19104  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID, 0u,
19105  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_SIZE, 4u,
19106  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19107  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID, 0u,
19108  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_SIZE, 4u,
19109  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19110  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID, 0u,
19111  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_SIZE, 4u,
19112  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19113  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID, 0u,
19114  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_SIZE, 4u,
19115  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19116  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID, 0u,
19117  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_SIZE, 4u,
19118  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19119  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID, 0u,
19120  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_SIZE, 4u,
19121  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19122  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID, 0u,
19123  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_SIZE, 4u,
19124  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19125  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID, 0u,
19126  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_SIZE, 4u,
19127  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19128  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID, 0u,
19129  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_SIZE, 4u,
19130  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19131  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID, 0u,
19132  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_SIZE, 4u,
19133  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19134  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID, 0u,
19135  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_SIZE, 4u,
19136  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19137  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID, 0u,
19138  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_SIZE, 4u,
19139  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19140  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID, 0u,
19141  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_SIZE, 4u,
19142  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
19143 };
19144 
19150 {
19151  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0004E00000u,
19152  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
19153  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
19154 };
19155 
19161 static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
19162 {
19163  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
19164  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
19165 };
19166 
19172 {
19173  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0004E10000u,
19174  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
19175  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
19176 };
19177 
19183 static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
19184 {
19185  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
19186  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
19187 };
19188 
19194 {
19195  { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
19196  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
19197  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
19198  { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
19199  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
19200  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
19201  { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
19202  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
19203  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
19204  { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
19205  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
19206  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
19207 };
19208 
19214 {
19215  { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
19216  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
19217  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
19218  { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
19219  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
19220  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
19221  { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
19222  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
19223  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
19224  { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
19225  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
19226  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
19227 };
19228 
19233 static const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS] =
19234 {
19235  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
19236  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
19237  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
19238  0u,
19239  NULL },
19240  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
19241  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
19242  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
19243  0u,
19244  NULL },
19245  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
19246  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
19247  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
19248  0u,
19249  NULL },
19250  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
19251  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
19252  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
19253  0u,
19254  NULL },
19255  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
19256  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
19257  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
19258  0u,
19259  NULL },
19260  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
19261  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
19262  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
19263  0u,
19264  NULL },
19265  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
19266  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
19267  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
19268  0u,
19269  NULL },
19270  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
19271  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
19272  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
19273  0u,
19274  NULL },
19275  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
19276  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
19277  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
19278  0u,
19279  NULL },
19280  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
19281  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
19282  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
19283  0u,
19284  NULL },
19285  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
19286  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
19287  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
19288  0u,
19289  NULL },
19290  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
19291  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
19292  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
19293  0u,
19294  NULL },
19295  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
19296  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
19297  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
19298  0u,
19299  NULL },
19300  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
19301  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
19302  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
19303  0u,
19304  NULL },
19305  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
19306  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
19307  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
19308  0u,
19309  NULL },
19310  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
19311  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
19312  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
19313  0u,
19314  NULL },
19315  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
19316  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
19317  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
19318  0u,
19319  NULL },
19320  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
19321  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
19322  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
19323  0u,
19324  NULL },
19325  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
19326  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
19327  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
19328  0u,
19329  NULL },
19330  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
19331  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
19332  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
19333  0u,
19334  NULL },
19335  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
19336  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
19337  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
19338  0u,
19339  NULL },
19340  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID,
19341  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_INJECT_TYPE,
19342  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ECC_TYPE,
19343  0u,
19344  NULL },
19345  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID,
19346  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_INJECT_TYPE,
19347  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ECC_TYPE,
19348  0u,
19349  NULL },
19350  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID,
19351  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_INJECT_TYPE,
19352  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ECC_TYPE,
19353  0u,
19354  NULL },
19355  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID,
19356  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_INJECT_TYPE,
19357  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ECC_TYPE,
19358  0u,
19359  NULL },
19360  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID,
19361  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_INJECT_TYPE,
19362  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ECC_TYPE,
19363  0u,
19364  NULL },
19365  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID,
19366  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_INJECT_TYPE,
19367  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ECC_TYPE,
19368  0u,
19369  NULL },
19370  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID,
19371  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_INJECT_TYPE,
19372  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ECC_TYPE,
19373  0u,
19374  NULL },
19375  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
19376  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
19377  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
19378  0u,
19379  NULL },
19380 };
19381 
19386 static const SDL_RAMIdEntry_t SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS] =
19387 {
19388  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
19389  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
19390  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
19391  0u,
19392  NULL },
19393  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
19394  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
19395  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
19396  0u,
19397  NULL },
19398  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
19399  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
19400  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
19401  0u,
19402  NULL },
19403  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
19404  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
19405  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
19406  0u,
19407  NULL },
19408  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
19409  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
19410  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
19411  0u,
19412  NULL },
19413  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
19414  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
19415  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
19416  0u,
19417  NULL },
19418  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
19419  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
19420  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
19421  0u,
19422  NULL },
19423  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
19424  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
19425  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
19426  0u,
19427  NULL },
19428  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
19429  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
19430  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
19431  0u,
19432  NULL },
19433  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
19434  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
19435  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
19436  0u,
19437  NULL },
19438  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
19439  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
19440  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
19441  0u,
19442  NULL },
19443  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
19444  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
19445  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
19446  0u,
19447  NULL },
19448  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
19449  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
19450  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
19451  0u,
19452  NULL },
19453  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
19454  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
19455  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
19456  0u,
19457  NULL },
19458  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
19459  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
19460  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
19461  0u,
19462  NULL },
19463  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
19464  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
19465  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
19466  0u,
19467  NULL },
19468  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
19469  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
19470  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
19471  0u,
19472  NULL },
19473  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
19474  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
19475  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
19476  0u,
19477  NULL },
19478  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
19479  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
19480  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
19481  0u,
19482  NULL },
19483  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
19484  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
19485  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
19486  0u,
19487  NULL },
19488  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
19489  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
19490  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
19491  0u,
19492  NULL },
19493  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID,
19494  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_INJECT_TYPE,
19495  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ECC_TYPE,
19496  0u,
19497  NULL },
19498  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID,
19499  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_INJECT_TYPE,
19500  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ECC_TYPE,
19501  0u,
19502  NULL },
19503  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID,
19504  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_INJECT_TYPE,
19505  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ECC_TYPE,
19506  0u,
19507  NULL },
19508  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID,
19509  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_INJECT_TYPE,
19510  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ECC_TYPE,
19511  0u,
19512  NULL },
19513  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID,
19514  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_INJECT_TYPE,
19515  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ECC_TYPE,
19516  0u,
19517  NULL },
19518  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID,
19519  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_INJECT_TYPE,
19520  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ECC_TYPE,
19521  0u,
19522  NULL },
19523  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID,
19524  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_INJECT_TYPE,
19525  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ECC_TYPE,
19526  0u,
19527  NULL },
19528  { SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
19529  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
19530  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
19531  0u,
19532  NULL },
19533 };
19534 
19539 static const SDL_RAMIdEntry_t SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RamIdTable[SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS] =
19540 {
19541  { SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_RAM_ID,
19542  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_INJECT_TYPE,
19543  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_ECC_TYPE,
19544  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS,
19546 };
19547 
19552 static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS] =
19553 {
19554  { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
19555  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
19556  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
19557  0u,
19558  NULL },
19559 };
19560 
19565 static const SDL_RAMIdEntry_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS] =
19566 {
19567  { SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
19568  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
19569  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
19570  0u,
19571  NULL },
19572 };
19573 
19578 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR2_RamIdTable[SDL_WKUP_ECC_AGGR2_NUM_RAMS] =
19579 {
19580  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
19581  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
19582  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
19583  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
19585  { SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
19586  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
19587  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
19588  SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
19590  { SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_RAM_ID,
19591  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_INJECT_TYPE,
19592  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_ECC_TYPE,
19593  SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
19595  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
19596  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
19597  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
19598  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
19600  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
19601  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
19602  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
19603  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
19605  { SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_RAM_ID,
19606  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
19607  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_ECC_TYPE,
19608  SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
19610  { SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
19611  SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
19612  SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
19613  SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
19615  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_RAM_ID,
19616  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_INJECT_TYPE,
19617  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_ECC_TYPE,
19618  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19620  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_RAM_ID,
19621  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
19622  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
19623  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19625  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
19626  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
19627  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
19628  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19630  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
19631  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
19632  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
19633  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
19635  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
19636  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
19637  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
19638  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
19640  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
19641  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
19642  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
19643  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
19645  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
19646  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
19647  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
19648  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19650  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
19651  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
19652  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
19653  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
19655  { SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
19656  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
19657  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
19658  SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
19660  { SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_RAM_ID,
19661  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
19662  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_ECC_TYPE,
19663  SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
19665 };
19666 
19671 static const SDL_RAMIdEntry_t SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_RamIdTable[SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_NUM_RAMS] =
19672 {
19673  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID,
19674  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_INJECT_TYPE,
19675  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_ECC_TYPE,
19676  0u,
19677  NULL },
19678  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID,
19679  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_INJECT_TYPE,
19680  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_ECC_TYPE,
19681  0u,
19682  NULL },
19683  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID,
19684  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_INJECT_TYPE,
19685  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_ECC_TYPE,
19686  0u,
19687  NULL },
19688  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID,
19689  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_INJECT_TYPE,
19690  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_ECC_TYPE,
19691  0u,
19692  NULL },
19693  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_STATE_BUFFER0_RAM_ID,
19694  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_STATE_BUFFER0_INJECT_TYPE,
19695  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_STATE_BUFFER0_ECC_TYPE,
19696  0u,
19697  NULL },
19698  { SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RING_MEMORY_RAM_ID,
19699  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RING_MEMORY_INJECT_TYPE,
19700  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_32CH_WRAP_TPRAM_DRU_RING_MEMORY_ECC_TYPE,
19701  0u,
19702  NULL },
19703 };
19704 
19709 static const SDL_RAMIdEntry_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_NUM_RAMS] =
19710 {
19711  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_ID,
19712  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_INJECT_TYPE,
19713  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_ECC_TYPE,
19714  0u,
19715  NULL },
19716  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
19717  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
19718  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
19719  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19721  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
19722  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
19723  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
19724  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
19726  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_RAM_ID,
19727  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_INJECT_TYPE,
19728  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_ECC_TYPE,
19729  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
19731  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
19732  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
19733  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
19734  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
19736  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
19737  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
19738  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
19739  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
19741  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_RAM_ID,
19742  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
19743  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
19744  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
19746  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
19747  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
19748  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
19749  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
19751  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_RAM_ID,
19752  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_INJECT_TYPE,
19753  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_ECC_TYPE,
19754  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS,
19756  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_RAM_ID,
19757  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_INJECT_TYPE,
19758  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_ECC_TYPE,
19759  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS,
19761  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_RAM_ID,
19762  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_INJECT_TYPE,
19763  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_ECC_TYPE,
19764  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS,
19766  { SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_RAM_ID,
19767  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_INJECT_TYPE,
19768  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_ECC_TYPE,
19769  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS,
19771 };
19772 
19777 static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS] =
19778 {
19779  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
19780  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
19781  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
19782  0u,
19783  NULL },
19784  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
19785  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
19786  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
19787  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
19789  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
19790  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
19791  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
19792  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
19794 };
19795 
19800 static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS] =
19801 {
19802  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
19803  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
19804  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
19805  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
19807  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
19808  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
19809  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
19810  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
19812  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
19813  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
19814  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
19815  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
19817  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
19818  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
19819  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
19820  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
19822 };
19823 
19828 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR1_RamIdTable[SDL_WKUP_ECC_AGGR1_NUM_RAMS] =
19829 {
19830  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_RAM_ID,
19831  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
19832  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
19833  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
19835  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
19836  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
19837  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
19838  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
19840  { SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
19841  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
19842  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
19843  SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
19845  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
19846  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
19847  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
19848  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
19850  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
19851  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
19852  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
19853  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
19855  { SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
19856  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
19857  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
19858  SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
19860  { SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
19861  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
19862  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
19863  SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
19865 };
19866 
19871 static const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS] =
19872 {
19873  { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
19874  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
19875  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
19876  0u,
19877  NULL },
19878 };
19879 
19884 static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS] =
19885 {
19886  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
19887  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
19888  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
19889  0u,
19890  NULL },
19891  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
19892  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
19893  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
19894  0u,
19895  NULL },
19896  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
19897  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
19898  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
19899  0u,
19900  NULL },
19901  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
19902  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
19903  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
19904  0u,
19905  NULL },
19906  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
19907  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
19908  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
19909  0u,
19910  NULL },
19911  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
19912  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
19913  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
19914  0u,
19915  NULL },
19916  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
19917  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
19918  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
19919  0u,
19920  NULL },
19921  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
19922  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
19923  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
19924  0u,
19925  NULL },
19926  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
19927  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
19928  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
19929  0u,
19930  NULL },
19931  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
19932  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
19933  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
19934  0u,
19935  NULL },
19936  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
19937  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
19938  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
19939  0u,
19940  NULL },
19941  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
19942  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
19943  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
19944  0u,
19945  NULL },
19946  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
19947  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
19948  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
19949  0u,
19950  NULL },
19951  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
19952  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
19953  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
19954  0u,
19955  NULL },
19956  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
19957  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
19958  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
19959  0u,
19960  NULL },
19961  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
19962  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
19963  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
19964  0u,
19965  NULL },
19966  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
19967  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
19968  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
19969  0u,
19970  NULL },
19971  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
19972  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
19973  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
19974  0u,
19975  NULL },
19976  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
19977  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
19978  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
19979  0u,
19980  NULL },
19981  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
19982  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
19983  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
19984  0u,
19985  NULL },
19986  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
19987  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
19988  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
19989  0u,
19990  NULL },
19991  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_ID,
19992  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_INJECT_TYPE,
19993  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_ECC_TYPE,
19994  0u,
19995  NULL },
19996  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_ID,
19997  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_INJECT_TYPE,
19998  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_ECC_TYPE,
19999  0u,
20000  NULL },
20001  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_ID,
20002  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_INJECT_TYPE,
20003  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_ECC_TYPE,
20004  0u,
20005  NULL },
20006  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_ID,
20007  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_INJECT_TYPE,
20008  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_ECC_TYPE,
20009  0u,
20010  NULL },
20011  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_ID,
20012  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_INJECT_TYPE,
20013  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_ECC_TYPE,
20014  0u,
20015  NULL },
20016  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_ID,
20017  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_INJECT_TYPE,
20018  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_ECC_TYPE,
20019  0u,
20020  NULL },
20021  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
20022  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
20023  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
20024  0u,
20025  NULL },
20026  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_RAM_ID,
20027  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_INJECT_TYPE,
20028  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_ECC_TYPE,
20029  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS,
20031  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
20032  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
20033  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
20034  0u,
20035  NULL },
20036  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_RAM_ID,
20037  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_INJECT_TYPE,
20038  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_ECC_TYPE,
20039  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS,
20041  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_RAM_ID,
20042  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_INJECT_TYPE,
20043  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_ECC_TYPE,
20044  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS,
20046  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_RAM_ID,
20047  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_INJECT_TYPE,
20048  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_ECC_TYPE,
20049  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS,
20051  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_RAM_ID,
20052  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
20053  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
20054  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
20056  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
20057  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
20058  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
20059  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
20061 };
20062 
20067 static const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS] =
20068 {
20069  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID,
20070  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_INJECT_TYPE,
20071  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ECC_TYPE,
20072  0u,
20073  NULL },
20074  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID,
20075  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_INJECT_TYPE,
20076  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ECC_TYPE,
20077  0u,
20078  NULL },
20079  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID,
20080  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_INJECT_TYPE,
20081  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ECC_TYPE,
20082  0u,
20083  NULL },
20084 };
20085 
20090 static const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS] =
20091 {
20092  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID,
20093  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_INJECT_TYPE,
20094  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ECC_TYPE,
20095  0u,
20096  NULL },
20097  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_RAM_ID,
20098  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_INJECT_TYPE,
20099  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL1_ECC_TYPE,
20100  0u,
20101  NULL },
20102  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_RAM_ID,
20103  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_INJECT_TYPE,
20104  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL2_ECC_TYPE,
20105  0u,
20106  NULL },
20107  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_RAM_ID,
20108  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_INJECT_TYPE,
20109  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL3_ECC_TYPE,
20110  0u,
20111  NULL },
20112  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_RAM_ID,
20113  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_INJECT_TYPE,
20114  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL4_ECC_TYPE,
20115  0u,
20116  NULL },
20117  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_RAM_ID,
20118  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_INJECT_TYPE,
20119  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL5_ECC_TYPE,
20120  0u,
20121  NULL },
20122  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_RAM_ID,
20123  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_INJECT_TYPE,
20124  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM67_CORE_ECC_ECC_CTRL6_ECC_TYPE,
20125  0u,
20126  NULL },
20127  { SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID,
20128  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_INJECT_TYPE,
20129  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ECC_TYPE,
20130  0u,
20131  NULL },
20132 };
20133 
20138 static const SDL_RAMIdEntry_t SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_NUM_RAMS] =
20139 {
20140  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_RAM_ID,
20141  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_INJECT_TYPE,
20142  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_ECC_TYPE,
20143  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
20145  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID,
20146  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
20147  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
20148  0u,
20149  NULL },
20150  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
20151  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
20152  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
20153  0u,
20154  NULL },
20155  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
20156  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
20157  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
20158  0u,
20159  NULL },
20160  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
20161  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
20162  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
20163  0u,
20164  NULL },
20165  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
20166  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
20167  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
20168  0u,
20169  NULL },
20170  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID,
20171  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_INJECT_TYPE,
20172  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ECC_TYPE,
20173  0u,
20174  NULL },
20175  { SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID,
20176  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_INJECT_TYPE,
20177  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ECC_TYPE,
20178  0u,
20179  NULL },
20180 };
20181 
20186 static const SDL_RAMIdEntry_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_NUM_RAMS] =
20187 {
20188  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_RAM_ID,
20189  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_INJECT_TYPE,
20190  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_ECC_TYPE,
20191  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
20193  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID,
20194  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
20195  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
20196  0u,
20197  NULL },
20198  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
20199  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
20200  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
20201  0u,
20202  NULL },
20203  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
20204  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
20205  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
20206  0u,
20207  NULL },
20208  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
20209  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
20210  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
20211  0u,
20212  NULL },
20213  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
20214  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
20215  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
20216  0u,
20217  NULL },
20218  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID,
20219  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_INJECT_TYPE,
20220  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ECC_TYPE,
20221  0u,
20222  NULL },
20223  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID,
20224  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_INJECT_TYPE,
20225  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ECC_TYPE,
20226  0u,
20227  NULL },
20228 };
20229 
20234 static const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS] =
20235 {
20236  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_RAM_ID,
20237  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_INJECT_TYPE,
20238  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_ECC_TYPE,
20239  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
20241  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID,
20242  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
20243  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
20244  0u,
20245  NULL },
20246  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
20247  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
20248  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
20249  0u,
20250  NULL },
20251  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
20252  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
20253  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
20254  0u,
20255  NULL },
20256  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
20257  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
20258  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
20259  0u,
20260  NULL },
20261  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
20262  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
20263  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
20264  0u,
20265  NULL },
20266  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID,
20267  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_INJECT_TYPE,
20268  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ECC_TYPE,
20269  0u,
20270  NULL },
20271  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID,
20272  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_INJECT_TYPE,
20273  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ECC_TYPE,
20274  0u,
20275  NULL },
20276 };
20277 
20282 static const SDL_RAMIdEntry_t SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable[SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS] =
20283 {
20284  { SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_ID,
20285  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_INJECT_TYPE,
20286  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_ECC_TYPE,
20287  0u,
20288  NULL },
20289 };
20290 
20295 static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
20296 {
20297  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
20298  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
20299  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
20300  0u,
20301  NULL },
20302 };
20303 
20308 static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
20309 {
20310  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
20311  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
20312  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
20313  0u,
20314  NULL },
20315 };
20316 
20321 static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS] =
20322 {
20323  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_RAM_ID,
20324  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_INJECT_TYPE,
20325  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_ECC_TYPE,
20326  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
20328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID,
20329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_INJECT_TYPE,
20330  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ECC_TYPE,
20331  0u,
20332  NULL },
20333  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID,
20334  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_INJECT_TYPE,
20335  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ECC_TYPE,
20336  0u,
20337  NULL },
20338  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID,
20339  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
20340  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ECC_TYPE,
20341  0u,
20342  NULL },
20343  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID,
20344  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
20345  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ECC_TYPE,
20346  0u,
20347  NULL },
20348  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID,
20349  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
20350  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ECC_TYPE,
20351  0u,
20352  NULL },
20353  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID,
20354  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
20355  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ECC_TYPE,
20356  0u,
20357  NULL },
20358  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID,
20359  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
20360  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ECC_TYPE,
20361  0u,
20362  NULL },
20363  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID,
20364  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_INJECT_TYPE,
20365  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ECC_TYPE,
20366  0u,
20367  NULL },
20368  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID,
20369  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_INJECT_TYPE,
20370  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ECC_TYPE,
20371  0u,
20372  NULL },
20373  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID,
20374  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
20375  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
20376  0u,
20377  NULL },
20378  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_RAM_ID,
20379  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_INJECT_TYPE,
20380  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_ECC_TYPE,
20381  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS,
20383  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_RAM_ID,
20384  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_INJECT_TYPE,
20385  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_ECC_TYPE,
20386  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS,
20388  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID,
20389  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_INJECT_TYPE,
20390  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ECC_TYPE,
20391  0u,
20392  NULL },
20393  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID,
20394  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_INJECT_TYPE,
20395  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ECC_TYPE,
20396  0u,
20397  NULL },
20398  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_RAM_ID,
20399  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_INJECT_TYPE,
20400  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_ECC_TYPE,
20401  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS,
20403  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_RAM_ID,
20404  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_INJECT_TYPE,
20405  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_ECC_TYPE,
20406  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS,
20408  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID,
20409  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_INJECT_TYPE,
20410  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ECC_TYPE,
20411  0u,
20412  NULL },
20413  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
20414  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
20415  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
20416  0u,
20417  NULL },
20418  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
20419  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
20420  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
20421  0u,
20422  NULL },
20423  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_RAM_ID,
20424  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_INJECT_TYPE,
20425  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_ECC_TYPE,
20426  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS,
20428  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
20429  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
20430  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
20431  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
20433  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
20434  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
20435  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
20436  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
20438  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
20439  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
20440  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
20441  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
20443  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID,
20444  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_INJECT_TYPE,
20445  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ECC_TYPE,
20446  0u,
20447  NULL },
20448  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_RAM_ID,
20449  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_INJECT_TYPE,
20450  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_ECC_TYPE,
20451  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS,
20453  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
20454  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
20455  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
20456  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
20458  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_RAM_ID,
20459  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
20460  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
20461  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
20463  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
20464  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
20465  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
20466  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
20468  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
20469  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
20470  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
20471  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
20473  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
20474  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
20475  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
20476  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
20478  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
20479  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
20480  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
20481  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
20483  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_RAM_ID,
20484  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_INJECT_TYPE,
20485  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_ECC_TYPE,
20486  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
20488  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_RAM_ID,
20489  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_INJECT_TYPE,
20490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_ECC_TYPE,
20491  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
20493  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_RAM_ID,
20494  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
20495  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
20496  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
20498  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_RAM_ID,
20499  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_INJECT_TYPE,
20500  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_ECC_TYPE,
20501  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
20503  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_RAM_ID,
20504  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_INJECT_TYPE,
20505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_ECC_TYPE,
20506  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
20508  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_RAM_ID,
20509  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_INJECT_TYPE,
20510  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_ECC_TYPE,
20511  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS,
20513  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_RAM_ID,
20514  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
20515  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
20516  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
20518  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_RAM_ID,
20519  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_INJECT_TYPE,
20520  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_ECC_TYPE,
20521  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS,
20523  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_RAM_ID,
20524  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_INJECT_TYPE,
20525  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_ECC_TYPE,
20526  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
20528  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_RAM_ID,
20529  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_INJECT_TYPE,
20530  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_ECC_TYPE,
20531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
20533  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_RAM_ID,
20534  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_INJECT_TYPE,
20535  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_ECC_TYPE,
20536  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
20538  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_RAM_ID,
20539  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
20540  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
20541  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
20543  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
20544  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
20545  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
20546  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
20548  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
20549  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
20550  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
20551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
20553  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
20554  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
20555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
20556  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
20558 };
20559 
20564 static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS] =
20565 {
20566  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_ID,
20567  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_INJECT_TYPE,
20568  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_ECC_TYPE,
20569  0u,
20570  NULL },
20571  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_ID,
20572  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_INJECT_TYPE,
20573  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_ECC_TYPE,
20574  0u,
20575  NULL },
20576  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_ID,
20577  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_INJECT_TYPE,
20578  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_ECC_TYPE,
20579  0u,
20580  NULL },
20581  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_ID,
20582  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_INJECT_TYPE,
20583  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_ECC_TYPE,
20584  0u,
20585  NULL },
20586  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_ID,
20587  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_INJECT_TYPE,
20588  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_ECC_TYPE,
20589  0u,
20590  NULL },
20591  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_ID,
20592  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_INJECT_TYPE,
20593  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_ECC_TYPE,
20594  0u,
20595  NULL },
20596  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_ID,
20597  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_INJECT_TYPE,
20598  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_ECC_TYPE,
20599  0u,
20600  NULL },
20601  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_ID,
20602  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_INJECT_TYPE,
20603  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_ECC_TYPE,
20604  0u,
20605  NULL },
20606  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_ID,
20607  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_INJECT_TYPE,
20608  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_ECC_TYPE,
20609  0u,
20610  NULL },
20611  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_ID,
20612  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_INJECT_TYPE,
20613  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_ECC_TYPE,
20614  0u,
20615  NULL },
20616  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_ID,
20617  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_INJECT_TYPE,
20618  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_ECC_TYPE,
20619  0u,
20620  NULL },
20621  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_ID,
20622  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_INJECT_TYPE,
20623  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_ECC_TYPE,
20624  0u,
20625  NULL },
20626 };
20627 
20632 static const SDL_RAMIdEntry_t SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_NUM_RAMS] =
20633 {
20634  { SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_MSRAM8KX256E_MSRAM0_ECC0_RAM_ID,
20635  SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_MSRAM8KX256E_MSRAM0_ECC0_INJECT_TYPE,
20636  SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_MSRAM8KX256E_MSRAM0_ECC0_ECC_TYPE,
20637  0u,
20638  NULL },
20639 };
20640 
20645 static const SDL_RAMIdEntry_t SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_RamIdTable[SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_NUM_RAMS] =
20646 {
20647  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_RAM_ID,
20648  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_INJECT_TYPE,
20649  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_ECC_TYPE,
20650  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_MAX_NUM_CHECKERS,
20652  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_DMA_PSIL_FIFO_RAM_ID,
20653  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
20654  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
20655  0u,
20656  NULL },
20657  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_RAM_ID,
20658  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_INJECT_TYPE,
20659  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_ECC_TYPE,
20660  0u,
20661  NULL },
20662 };
20663 
20668 static const SDL_RAMIdEntry_t SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_RamIdTable[SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_NUM_RAMS] =
20669 {
20670  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER0_FIFO_RAM_ID,
20671  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER0_FIFO_INJECT_TYPE,
20672  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER0_FIFO_ECC_TYPE,
20673  0u,
20674  NULL },
20675  { SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER1_FIFO_RAM_ID,
20676  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER1_FIFO_INJECT_TYPE,
20677  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_CSI_TX_IF_V2_RAM_WRAPPER1_FIFO_ECC_TYPE,
20678  0u,
20679  NULL },
20680 };
20681 
20686 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_RamIdTable[SDL_WKUP_ECC_AGGR0_NUM_RAMS] =
20687 {
20688  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
20689  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
20690  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
20691  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
20693  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
20694  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
20695  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
20696  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
20698  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
20699  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
20700  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
20701  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
20703  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_RAM_ID,
20704  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_INJECT_TYPE,
20705  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_ECC_TYPE,
20706  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
20708  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
20709  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
20710  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
20711  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
20713  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
20714  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
20715  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
20716  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
20718  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
20719  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
20720  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
20721  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
20723  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
20724  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
20725  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
20726  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
20728  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_RAM_ID,
20729  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_INJECT_TYPE,
20730  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_ECC_TYPE,
20731  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
20733  { SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_RAM_ID,
20734  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_INJECT_TYPE,
20735  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_ECC_TYPE,
20736  SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS,
20738  { SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_RAM_ID,
20739  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
20740  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_ECC_TYPE,
20741  SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
20743 };
20744 
20749 static const SDL_RAMIdEntry_t SDL_DMASS0_ECC_AGGR_0_RamIdTable[SDL_DMASS0_ECC_AGGR_0_NUM_RAMS] =
20750 {
20751  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_RAM_ID,
20752  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_INJECT_TYPE,
20753  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_CONFIG_ECC_TYPE,
20754  0u,
20755  NULL },
20756  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_RAM_ID,
20757  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_INJECT_TYPE,
20758  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_CFG_STATE_ECC_TYPE,
20759  0u,
20760  NULL },
20761  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_RAM_ID,
20762  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
20763  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F0_ECC_TYPE,
20764  0u,
20765  NULL },
20766  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_RAM_ID,
20767  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
20768  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_TPCFIFO_F1_ECC_TYPE,
20769  0u,
20770  NULL },
20771  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_RAM_ID,
20772  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
20773  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F0_ECC_TYPE,
20774  0u,
20775  NULL },
20776  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_RAM_ID,
20777  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
20778  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_F1_ECC_TYPE,
20779  0u,
20780  NULL },
20781  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_RAM_ID,
20782  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
20783  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RPCFIFO_WC_ECC_TYPE,
20784  0u,
20785  NULL },
20786  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_RAM_ID,
20787  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_INJECT_TYPE,
20788  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STST0_ECC_TYPE,
20789  0u,
20790  NULL },
20791  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_RAM_ID,
20792  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_INJECT_TYPE,
20793  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_STATS_STSR0_ECC_TYPE,
20794  0u,
20795  NULL },
20796  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_RAM_ID,
20797  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
20798  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
20799  0u,
20800  NULL },
20801  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_RAM_ID,
20802  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_INJECT_TYPE,
20803  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_CONFIG_ECC_TYPE,
20804  0u,
20805  NULL },
20806  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_RAM_ID,
20807  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_INJECT_TYPE,
20808  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_CFG_STATE_ECC_TYPE,
20809  0u,
20810  NULL },
20811  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_RAM_ID,
20812  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_INJECT_TYPE,
20813  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F0_ECC_TYPE,
20814  0u,
20815  NULL },
20816  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_RAM_ID,
20817  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_INJECT_TYPE,
20818  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_PCFIFO_DFIFO_F1_ECC_TYPE,
20819  0u,
20820  NULL },
20821  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_RAM_ID,
20822  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_INJECT_TYPE,
20823  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F0_ECC_TYPE,
20824  0u,
20825  NULL },
20826  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_RAM_ID,
20827  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_INJECT_TYPE,
20828  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_TPCFIFO_F1_ECC_TYPE,
20829  0u,
20830  NULL },
20831  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_RAM_ID,
20832  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_INJECT_TYPE,
20833  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F0_ECC_TYPE,
20834  0u,
20835  NULL },
20836  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_RAM_ID,
20837  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_INJECT_TYPE,
20838  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_F1_ECC_TYPE,
20839  0u,
20840  NULL },
20841  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_RAM_ID,
20842  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_INJECT_TYPE,
20843  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RPCFIFO_WC_ECC_TYPE,
20844  0u,
20845  NULL },
20846  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_RAM_ID,
20847  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_INJECT_TYPE,
20848  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STST0_ECC_TYPE,
20849  0u,
20850  NULL },
20851  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_RAM_ID,
20852  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_INJECT_TYPE,
20853  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_STATS_STSR0_ECC_TYPE,
20854  0u,
20855  NULL },
20856  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_RAM_ID,
20857  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
20858  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_BCDMA_RINGOCC_CNTR_ECC_TYPE,
20859  0u,
20860  NULL },
20861  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID,
20862  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_INJECT_TYPE,
20863  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ECC_TYPE,
20864  0u,
20865  NULL },
20866  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_ID,
20867  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_INJECT_TYPE,
20868  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_ECC_TYPE,
20869  0u,
20870  NULL },
20871  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_RAM_ID,
20872  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_INJECT_TYPE,
20873  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_RINGACC_STRAM_ECC_TYPE,
20874  0u,
20875  NULL },
20876  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
20877  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
20878  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
20879  0u,
20880  NULL },
20881  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
20882  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
20883  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
20884  0u,
20885  NULL },
20886  { SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_RAM_ID,
20887  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_INJECT_TYPE,
20888  SDL_DMASS0_ECC_AGGR_0_DMSS_AM67_IPCSS_MSRAM_ECC0_ECC_TYPE,
20889  0u,
20890  NULL },
20891 };
20892 
20897 static const SDL_RAMIdEntry_t SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_NUM_RAMS] =
20898 {
20899  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID,
20900  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_INJECT_TYPE,
20901  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ECC_TYPE,
20902  0u,
20903  NULL },
20904  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID,
20905  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_INJECT_TYPE,
20906  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ECC_TYPE,
20907  0u,
20908  NULL },
20909  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID,
20910  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_INJECT_TYPE,
20911  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ECC_TYPE,
20912  0u,
20913  NULL },
20914  { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID,
20915  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_INJECT_TYPE,
20916  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ECC_TYPE,
20917  0u,
20918  NULL },
20919 };
20920 
20925 static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS] =
20926 {
20927  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_RAM_ID,
20928  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_INJECT_TYPE,
20929  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_ECC_TYPE,
20930  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS,
20932  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_RAM_ID,
20933  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_INJECT_TYPE,
20934  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_ECC_TYPE,
20935  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS,
20937  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_RAM_ID,
20938  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_INJECT_TYPE,
20939  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_ECC_TYPE,
20940  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS,
20942  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_RAM_ID,
20943  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_INJECT_TYPE,
20944  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_ECC_TYPE,
20945  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS,
20947  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_RAM_ID,
20948  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_INJECT_TYPE,
20949  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_ECC_TYPE,
20950  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS,
20952  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_RAM_ID,
20953  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_INJECT_TYPE,
20954  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_ECC_TYPE,
20955  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS,
20957  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_RAM_ID,
20958  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
20959  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_ECC_TYPE,
20960  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
20962 };
20963 
20968 static const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] =
20969 {
20970  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
20971  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
20972  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
20973  0u,
20974  NULL },
20975  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
20976  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
20977  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
20978  0u,
20979  NULL },
20980 };
20981 
20986 static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS] =
20987 {
20988  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
20989  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
20990  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
20991  0u,
20992  NULL },
20993  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
20994  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
20995  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
20996  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
20998  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
20999  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
21000  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
21001  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
21003 };
21004 
21009 static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
21010 {
21011  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
21012  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
21013  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
21014  0u,
21015  NULL },
21016 };
21017 
21022 static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
21023 {
21024  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
21025  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
21026  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
21027  0u,
21028  NULL },
21029 };
21030 
21035 static const SDL_RAMIdEntry_t SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RamIdTable[SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_NUM_RAMS] =
21036 {
21037  { SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
21038  SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
21039  SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
21040  0u,
21041  NULL },
21042 };
21043 
21048 static const SDL_RAMIdEntry_t SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_NUM_RAMS] =
21049 {
21050  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID,
21051  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_INJECT_TYPE,
21052  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_ECC_TYPE,
21053  0u,
21054  NULL },
21055  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID,
21056  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_INJECT_TYPE,
21057  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_ECC_TYPE,
21058  0u,
21059  NULL },
21060  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID,
21061  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_INJECT_TYPE,
21062  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_ECC_TYPE,
21063  0u,
21064  NULL },
21065  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID,
21066  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_INJECT_TYPE,
21067  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_ECC_TYPE,
21068  0u,
21069  NULL },
21070  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_RAM_ID,
21071  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_INJECT_TYPE,
21072  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_ECC_TYPE,
21073  0u,
21074  NULL },
21075  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_RAM_ID,
21076  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_INJECT_TYPE,
21077  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_ECC_TYPE,
21078  0u,
21079  NULL },
21080 };
21081 
21086 static const SDL_RAMIdEntry_t SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_NUM_RAMS] =
21087 {
21088  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_RAM_ID,
21089  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_INJECT_TYPE,
21090  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_ECC_TYPE,
21091  0u,
21092  NULL },
21093  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_RAM_ID,
21094  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_INJECT_TYPE,
21095  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_ECC_TYPE,
21096  0u,
21097  NULL },
21098  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_RAM_ID,
21099  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_INJECT_TYPE,
21100  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_ECC_TYPE,
21101  0u,
21102  NULL },
21103  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_RAM_ID,
21104  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_INJECT_TYPE,
21105  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_ECC_TYPE,
21106  0u,
21107  NULL },
21108  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_RAM_ID,
21109  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_INJECT_TYPE,
21110  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_ECC_TYPE,
21111  0u,
21112  NULL },
21113  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_RAM_ID,
21114  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_INJECT_TYPE,
21115  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_ECC_TYPE,
21116  0u,
21117  NULL },
21118  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_RAM_ID,
21119  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_INJECT_TYPE,
21120  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_ECC_TYPE,
21121  0u,
21122  NULL },
21123  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_RAM_ID,
21124  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_INJECT_TYPE,
21125  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_ECC_TYPE,
21126  0u,
21127  NULL },
21128  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_RAM_ID,
21129  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_INJECT_TYPE,
21130  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_ECC_TYPE,
21131  0u,
21132  NULL },
21133  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_RAM_ID,
21134  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_INJECT_TYPE,
21135  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_ECC_TYPE,
21136  0u,
21137  NULL },
21138  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_RAM_ID,
21139  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_INJECT_TYPE,
21140  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_ECC_TYPE,
21141  0u,
21142  NULL },
21143  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_RAM_ID,
21144  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_INJECT_TYPE,
21145  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_ECC_TYPE,
21146  0u,
21147  NULL },
21148 };
21149 
21154 static const SDL_RAMIdEntry_t SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_NUM_RAMS] =
21155 {
21156  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_RAM_ID,
21157  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_INJECT_TYPE,
21158  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_ECC_TYPE,
21159  0u,
21160  NULL },
21161  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_RAM_ID,
21162  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_INJECT_TYPE,
21163  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_ECC_TYPE,
21164  0u,
21165  NULL },
21166  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_RAM_ID,
21167  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_INJECT_TYPE,
21168  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_ECC_TYPE,
21169  0u,
21170  NULL },
21171  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_RAM_ID,
21172  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_INJECT_TYPE,
21173  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_ECC_TYPE,
21174  0u,
21175  NULL },
21176  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_RAM_ID,
21177  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_INJECT_TYPE,
21178  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_ECC_TYPE,
21179  0u,
21180  NULL },
21181  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_RAM_ID,
21182  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_INJECT_TYPE,
21183  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_ECC_TYPE,
21184  0u,
21185  NULL },
21186  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_RAM_ID,
21187  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_INJECT_TYPE,
21188  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_ECC_TYPE,
21189  0u,
21190  NULL },
21191  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_RAM_ID,
21192  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_INJECT_TYPE,
21193  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_ECC_TYPE,
21194  0u,
21195  NULL },
21196  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_RAM_ID,
21197  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_INJECT_TYPE,
21198  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_ECC_TYPE,
21199  0u,
21200  NULL },
21201  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_RAM_ID,
21202  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_INJECT_TYPE,
21203  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_ECC_TYPE,
21204  0u,
21205  NULL },
21206  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_RAM_ID,
21207  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_INJECT_TYPE,
21208  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_ECC_TYPE,
21209  0u,
21210  NULL },
21211  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_RAM_ID,
21212  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_INJECT_TYPE,
21213  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_ECC_TYPE,
21214  0u,
21215  NULL },
21216  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_RAM_ID,
21217  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_INJECT_TYPE,
21218  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_ECC_TYPE,
21219  0u,
21220  NULL },
21221  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_RAM_ID,
21222  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_INJECT_TYPE,
21223  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_ECC_TYPE,
21224  0u,
21225  NULL },
21226  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_RAM_ID,
21227  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_INJECT_TYPE,
21228  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_ECC_TYPE,
21229  0u,
21230  NULL },
21231  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_RAM_ID,
21232  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_INJECT_TYPE,
21233  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_ECC_TYPE,
21234  0u,
21235  NULL },
21236  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_RAM_ID,
21237  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_INJECT_TYPE,
21238  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_ECC_TYPE,
21239  0u,
21240  NULL },
21241  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_RAM_ID,
21242  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_INJECT_TYPE,
21243  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_ECC_TYPE,
21244  0u,
21245  NULL },
21246  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_RAM_ID,
21247  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_INJECT_TYPE,
21248  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_ECC_TYPE,
21249  0u,
21250  NULL },
21251  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_RAM_ID,
21252  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_INJECT_TYPE,
21253  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_ECC_TYPE,
21254  0u,
21255  NULL },
21256  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_RAM_ID,
21257  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_INJECT_TYPE,
21258  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_ECC_TYPE,
21259  0u,
21260  NULL },
21261  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_RAM_ID,
21262  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_INJECT_TYPE,
21263  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_ECC_TYPE,
21264  0u,
21265  NULL },
21266  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_RAM_ID,
21267  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_INJECT_TYPE,
21268  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_ECC_TYPE,
21269  0u,
21270  NULL },
21271  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_RAM_ID,
21272  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_INJECT_TYPE,
21273  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_ECC_TYPE,
21274  0u,
21275  NULL },
21276  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_RAM_ID,
21277  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_INJECT_TYPE,
21278  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_ECC_TYPE,
21279  0u,
21280  NULL },
21281  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_RAM_ID,
21282  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_INJECT_TYPE,
21283  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_ECC_TYPE,
21284  0u,
21285  NULL },
21286  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_RAM_ID,
21287  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_INJECT_TYPE,
21288  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_ECC_TYPE,
21289  0u,
21290  NULL },
21291  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_RAM_ID,
21292  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_INJECT_TYPE,
21293  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_ECC_TYPE,
21294  0u,
21295  NULL },
21296  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_RAM_ID,
21297  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_INJECT_TYPE,
21298  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_ECC_TYPE,
21299  0u,
21300  NULL },
21301  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_RAM_ID,
21302  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_INJECT_TYPE,
21303  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_ECC_TYPE,
21304  0u,
21305  NULL },
21306  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_RAM_ID,
21307  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_INJECT_TYPE,
21308  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_ECC_TYPE,
21309  0u,
21310  NULL },
21311  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_RAM_ID,
21312  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_INJECT_TYPE,
21313  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_ECC_TYPE,
21314  0u,
21315  NULL },
21316  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_RAM_ID,
21317  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_INJECT_TYPE,
21318  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_ECC_TYPE,
21319  0u,
21320  NULL },
21321  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_RAM_ID,
21322  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_INJECT_TYPE,
21323  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_ECC_TYPE,
21324  0u,
21325  NULL },
21326  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_RAM_ID,
21327  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_INJECT_TYPE,
21328  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_ECC_TYPE,
21329  0u,
21330  NULL },
21331  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_RAM_ID,
21332  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_INJECT_TYPE,
21333  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_ECC_TYPE,
21334  0u,
21335  NULL },
21336  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_RAM_ID,
21337  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_INJECT_TYPE,
21338  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_ECC_TYPE,
21339  0u,
21340  NULL },
21341  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_RAM_ID,
21342  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_INJECT_TYPE,
21343  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_ECC_TYPE,
21344  0u,
21345  NULL },
21346  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_RAM_ID,
21347  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_INJECT_TYPE,
21348  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_ECC_TYPE,
21349  0u,
21350  NULL },
21351  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_RAM_ID,
21352  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_INJECT_TYPE,
21353  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_ECC_TYPE,
21354  0u,
21355  NULL },
21356  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_RAM_ID,
21357  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_INJECT_TYPE,
21358  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_ECC_TYPE,
21359  0u,
21360  NULL },
21361  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_RAM_ID,
21362  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_INJECT_TYPE,
21363  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_ECC_TYPE,
21364  0u,
21365  NULL },
21366  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_RAM_ID,
21367  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_INJECT_TYPE,
21368  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_ECC_TYPE,
21369  0u,
21370  NULL },
21371  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_RAM_ID,
21372  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_INJECT_TYPE,
21373  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_ECC_TYPE,
21374  0u,
21375  NULL },
21376  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_RAM_ID,
21377  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_INJECT_TYPE,
21378  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_ECC_TYPE,
21379  0u,
21380  NULL },
21381  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_RAM_ID,
21382  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_INJECT_TYPE,
21383  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_ECC_TYPE,
21384  0u,
21385  NULL },
21386  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_RAM_ID,
21387  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_INJECT_TYPE,
21388  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_ECC_TYPE,
21389  0u,
21390  NULL },
21391  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_RAM_ID,
21392  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_INJECT_TYPE,
21393  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_ECC_TYPE,
21394  0u,
21395  NULL },
21396  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_RAM_ID,
21397  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_INJECT_TYPE,
21398  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_ECC_TYPE,
21399  0u,
21400  NULL },
21401  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_RAM_ID,
21402  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_INJECT_TYPE,
21403  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_ECC_TYPE,
21404  0u,
21405  NULL },
21406  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_RAM_ID,
21407  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_INJECT_TYPE,
21408  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_ECC_TYPE,
21409  0u,
21410  NULL },
21411  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_RAM_ID,
21412  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_INJECT_TYPE,
21413  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_ECC_TYPE,
21414  0u,
21415  NULL },
21416  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_RAM_ID,
21417  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_INJECT_TYPE,
21418  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_ECC_TYPE,
21419  0u,
21420  NULL },
21421  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_RAM_ID,
21422  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_INJECT_TYPE,
21423  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_ECC_TYPE,
21424  0u,
21425  NULL },
21426  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_RAM_ID,
21427  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_INJECT_TYPE,
21428  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_ECC_TYPE,
21429  0u,
21430  NULL },
21431  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_RAM_ID,
21432  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_INJECT_TYPE,
21433  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_ECC_TYPE,
21434  0u,
21435  NULL },
21436  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_RAM_ID,
21437  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_INJECT_TYPE,
21438  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_ECC_TYPE,
21439  0u,
21440  NULL },
21441  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_RAM_ID,
21442  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_INJECT_TYPE,
21443  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_ECC_TYPE,
21444  0u,
21445  NULL },
21446  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_RAM_ID,
21447  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_INJECT_TYPE,
21448  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_ECC_TYPE,
21449  0u,
21450  NULL },
21451  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_RAM_ID,
21452  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_INJECT_TYPE,
21453  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_ECC_TYPE,
21454  0u,
21455  NULL },
21456  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_RAM_ID,
21457  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_INJECT_TYPE,
21458  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_ECC_TYPE,
21459  0u,
21460  NULL },
21461  { SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_RAM_ID,
21462  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_INJECT_TYPE,
21463  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_ECC_TYPE,
21464  0u,
21465  NULL },
21466 };
21467 
21472 static const SDL_RAMIdEntry_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS] =
21473 {
21474  { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID,
21475  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_INJECT_TYPE,
21476  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ECC_TYPE,
21477  0u,
21478  NULL },
21479 };
21480 
21485 static const SDL_RAMIdEntry_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_RamIdTable[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_NUM_RAMS] =
21486 {
21487  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_RAM_ID,
21488  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_INJECT_TYPE,
21489  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_ECC_TYPE,
21490  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS,
21492  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_RAM_ID,
21493  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_INJECT_TYPE,
21494  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_ECC_TYPE,
21495  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS,
21497  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_RAM_ID,
21498  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_INJECT_TYPE,
21499  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_ECC_TYPE,
21500  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS,
21502  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_RAM_ID,
21503  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_INJECT_TYPE,
21504  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_ECC_TYPE,
21505  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
21507  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_RAM_ID,
21508  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_INJECT_TYPE,
21509  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_ECC_TYPE,
21510  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
21512  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_RAM_ID,
21513  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_INJECT_TYPE,
21514  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_ECC_TYPE,
21515  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS,
21517  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_RAM_ID,
21518  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_INJECT_TYPE,
21519  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_ECC_TYPE,
21520  0u,
21521  NULL },
21522  { SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_RAM_ID,
21523  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_INJECT_TYPE,
21524  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_ECC_TYPE,
21525  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS,
21527 };
21528 
21533 static const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS] =
21534 {
21535  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID,
21536  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_INJECT_TYPE,
21537  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ECC_TYPE,
21538  0u,
21539  NULL },
21540  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID,
21541  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_INJECT_TYPE,
21542  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ECC_TYPE,
21543  0u,
21544  NULL },
21545  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID,
21546  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_INJECT_TYPE,
21547  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ECC_TYPE,
21548  0u,
21549  NULL },
21550  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID,
21551  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_INJECT_TYPE,
21552  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ECC_TYPE,
21553  0u,
21554  NULL },
21555 };
21556 
21561 static const SDL_RAMIdEntry_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_RamIdTable[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_NUM_RAMS] =
21562 {
21563  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_RAM_ID,
21564  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_INJECT_TYPE,
21565  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_ECC_TYPE,
21566  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS,
21568  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_RAM_ID,
21569  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_INJECT_TYPE,
21570  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_ECC_TYPE,
21571  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS,
21573  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_RAM_ID,
21574  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_INJECT_TYPE,
21575  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_ECC_TYPE,
21576  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS,
21578  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_RAM_ID,
21579  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_INJECT_TYPE,
21580  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_ECC_TYPE,
21581  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
21583  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_RAM_ID,
21584  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_INJECT_TYPE,
21585  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_ECC_TYPE,
21586  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
21588  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_RAM_ID,
21589  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_INJECT_TYPE,
21590  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_ECC_TYPE,
21591  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS,
21593  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_RAM_ID,
21594  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_INJECT_TYPE,
21595  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_SAM67_C7XV_CLEC_CLEC_SRAM_ECC_TYPE,
21596  0u,
21597  NULL },
21598  { SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_RAM_ID,
21599  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_INJECT_TYPE,
21600  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_ECC_TYPE,
21601  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS,
21603 };
21604 
21609 static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR0_RamIdTable[SDL_MCU_ECC_AGGR0_NUM_RAMS] =
21610 {
21611  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_RAM_ID,
21612  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_INJECT_TYPE,
21613  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_ECC_TYPE,
21614  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS,
21616  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_RAM_ID,
21617  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_INJECT_TYPE,
21618  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_ECC_TYPE,
21619  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS,
21621  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_RAM_ID,
21622  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_INJECT_TYPE,
21623  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_ECC_TYPE,
21624  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS,
21626  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_RAM_ID,
21627  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_INJECT_TYPE,
21628  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_ECC_TYPE,
21629  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS,
21631  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_RAM_ID,
21632  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_INJECT_TYPE,
21633  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_ECC_TYPE,
21634  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS,
21636  { SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_RAM_ID,
21637  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_INJECT_TYPE,
21638  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_ECC_TYPE,
21639  SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS,
21641  { SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
21642  SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
21643  SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
21644  SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
21646  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID,
21647  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_INJECT_TYPE,
21648  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ECC_TYPE,
21649  0u,
21650  NULL },
21651  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID,
21652  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_INJECT_TYPE,
21653  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ECC_TYPE,
21654  0u,
21655  NULL },
21656  { SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_RAM_ID,
21657  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_INJECT_TYPE,
21658  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_ECC_TYPE,
21659  SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS,
21661  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_RAM_ID,
21662  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
21663  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
21664  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
21666  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_RAM_ID,
21667  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
21668  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
21669  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
21671  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_RAM_ID,
21672  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
21673  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
21674  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
21676  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_RAM_ID,
21677  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
21678  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
21679  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
21681  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_RAM_ID,
21682  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
21683  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
21684  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
21686  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_RAM_ID,
21687  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
21688  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
21689  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
21691  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_RAM_ID,
21692  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_INJECT_TYPE,
21693  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_ECC_TYPE,
21694  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
21696  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_RAM_ID,
21697  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_INJECT_TYPE,
21698  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_ECC_TYPE,
21699  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
21701  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
21702  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
21703  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
21704  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
21706  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
21707  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
21708  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
21709  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
21711  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_RAM_ID,
21712  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
21713  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
21714  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
21716  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_RAM_ID,
21717  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
21718  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
21719  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
21721  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
21722  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
21723  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
21724  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
21726  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
21727  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
21728  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
21729  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
21731  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_RAM_ID,
21732  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
21733  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
21734  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
21736  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
21737  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
21738  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
21739  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
21741  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
21742  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
21743  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
21744  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
21746  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
21747  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
21748  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
21749  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
21751  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
21752  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
21753  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
21754  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
21756  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
21757  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
21758  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
21759  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
21761  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
21762  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
21763  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
21764  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
21766  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
21767  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
21768  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
21769  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
21771  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
21772  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
21773  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
21774  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
21776  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
21777  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
21778  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
21779  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21781  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
21782  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
21783  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
21784  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
21786  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
21787  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
21788  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
21789  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21791  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
21792  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
21793  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
21794  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21796  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
21797  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
21798  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
21799  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
21801  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
21802  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
21803  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
21804  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21806  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_RAM_ID,
21807  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_INJECT_TYPE,
21808  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_ECC_TYPE,
21809  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS,
21811  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
21812  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
21813  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
21814  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
21816  { SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_RAM_ID,
21817  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_INJECT_TYPE,
21818  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_ECC_TYPE,
21819  SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS,
21821  { SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
21822  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
21823  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
21824  SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
21826 };
21827 
21832 static const SDL_RAMIdEntry_t SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_NUM_RAMS] =
21833 {
21834  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_RAM_ID,
21835  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_INJECT_TYPE,
21836  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_ECC_TYPE,
21837  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
21839  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID,
21840  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
21841  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
21842  0u,
21843  NULL },
21844  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
21845  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
21846  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
21847  0u,
21848  NULL },
21849  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
21850  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
21851  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
21852  0u,
21853  NULL },
21854  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
21855  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
21856  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
21857  0u,
21858  NULL },
21859  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
21860  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
21861  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
21862  0u,
21863  NULL },
21864  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID,
21865  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_INJECT_TYPE,
21866  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ECC_TYPE,
21867  0u,
21868  NULL },
21869  { SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID,
21870  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_INJECT_TYPE,
21871  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ECC_TYPE,
21872  0u,
21873  NULL },
21874 };
21875 
21880 static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
21881 {
21882  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
21883  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
21884  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
21885  0u,
21886  NULL },
21887  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
21888  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
21889  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
21890  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
21892 };
21893 
21898 static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
21899 {
21900  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
21901  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
21902  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
21903  0u,
21904  NULL },
21905  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
21906  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
21907  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
21908  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
21910 };
21911 
21916 static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_NUM_RAMS] =
21917 {
21918  { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID,
21919  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_INJECT_TYPE,
21920  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ECC_TYPE,
21921  0u,
21922  NULL },
21923 };
21924 
21929 static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_NUM_RAMS] =
21930 {
21931  { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID,
21932  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_INJECT_TYPE,
21933  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ECC_TYPE,
21934  0u,
21935  NULL },
21936 };
21937 
21942 static const SDL_RAMIdEntry_t SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_RamIdTable[SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_NUM_RAMS] =
21943 {
21944  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_CONFIG_RAM_ID,
21945  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_CONFIG_INJECT_TYPE,
21946  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_CONFIG_ECC_TYPE,
21947  0u,
21948  NULL },
21949  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_STATE_RAM_ID,
21950  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_STATE_INJECT_TYPE,
21951  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_CFG_STATE_ECC_TYPE,
21952  0u,
21953  NULL },
21954  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F0_RAM_ID,
21955  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F0_INJECT_TYPE,
21956  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F0_ECC_TYPE,
21957  0u,
21958  NULL },
21959  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F1_RAM_ID,
21960  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F1_INJECT_TYPE,
21961  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_TPCFIFO_F1_ECC_TYPE,
21962  0u,
21963  NULL },
21964  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F0_RAM_ID,
21965  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F0_INJECT_TYPE,
21966  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F0_ECC_TYPE,
21967  0u,
21968  NULL },
21969  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F1_RAM_ID,
21970  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F1_INJECT_TYPE,
21971  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_F1_ECC_TYPE,
21972  0u,
21973  NULL },
21974  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_WC_RAM_ID,
21975  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_WC_INJECT_TYPE,
21976  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RPCFIFO_WC_ECC_TYPE,
21977  0u,
21978  NULL },
21979  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STST0_RAM_ID,
21980  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STST0_INJECT_TYPE,
21981  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STST0_ECC_TYPE,
21982  0u,
21983  NULL },
21984  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STSR0_RAM_ID,
21985  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STSR0_INJECT_TYPE,
21986  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_STATS_STSR0_ECC_TYPE,
21987  0u,
21988  NULL },
21989  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RINGOCC_CNTR_RAM_ID,
21990  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
21991  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_BCDMA_RINGOCC_CNTR_ECC_TYPE,
21992  0u,
21993  NULL },
21994  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_STATREG_SR_SPRAM_40X128_SWW_SR_RAM_ID,
21995  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_STATREG_SR_SPRAM_40X128_SWW_SR_INJECT_TYPE,
21996  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_STATREG_SR_SPRAM_40X128_SWW_SR_ECC_TYPE,
21997  0u,
21998  NULL },
21999  { SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_COMMON_IM_TPRAM_248X34_SWW_SR_RAM_ID,
22000  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_COMMON_IM_TPRAM_248X34_SWW_SR_INJECT_TYPE,
22001  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_DMSS_CSI_AM67_INTAGGR_COMMON_IM_TPRAM_248X34_SWW_SR_ECC_TYPE,
22002  0u,
22003  NULL },
22004 };
22005 
22010 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS] =
22011 {
22012  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
22013  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
22014  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
22015  0u,
22016  NULL },
22017  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
22018  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
22019  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
22020  0u,
22021  NULL },
22022  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
22023  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
22024  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
22025  0u,
22026  NULL },
22027  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
22028  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
22029  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
22030  0u,
22031  NULL },
22032  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
22033  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
22034  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
22035  0u,
22036  NULL },
22037  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
22038  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
22039  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
22040  0u,
22041  NULL },
22042  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22043  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22044  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22045  0u,
22046  NULL },
22047  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22048  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22049  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22050  0u,
22051  NULL },
22052  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22053  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22054  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22055  0u,
22056  NULL },
22057  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22058  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22059  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22060  0u,
22061  NULL },
22062  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
22063  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
22064  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
22065  0u,
22066  NULL },
22067  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
22068  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
22069  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
22070  0u,
22071  NULL },
22072  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
22073  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
22074  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
22075  0u,
22076  NULL },
22077  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
22078  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
22079  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
22080  0u,
22081  NULL },
22082  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22083  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22084  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22085  0u,
22086  NULL },
22087  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22088  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22089  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22090  0u,
22091  NULL },
22092  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22093  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22094  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22095  0u,
22096  NULL },
22097  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22098  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22099  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22100  0u,
22101  NULL },
22102  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
22103  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
22104  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
22105  0u,
22106  NULL },
22107  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22108  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22109  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22110  0u,
22111  NULL },
22112  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22113  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22114  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22115  0u,
22116  NULL },
22117  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22118  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22119  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22120  0u,
22121  NULL },
22122  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22123  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22124  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22125  0u,
22126  NULL },
22127  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
22128  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
22129  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
22130  0u,
22131  NULL },
22132  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
22133  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
22134  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
22135  0u,
22136  NULL },
22137  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
22138  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
22139  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
22140  0u,
22141  NULL },
22142  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
22143  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
22144  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
22145  0u,
22146  NULL },
22147 };
22148 
22153 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS] =
22154 {
22155  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
22156  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
22157  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
22158  0u,
22159  NULL },
22160  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
22161  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
22162  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
22163  0u,
22164  NULL },
22165  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
22166  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
22167  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
22168  0u,
22169  NULL },
22170  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
22171  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
22172  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
22173  0u,
22174  NULL },
22175  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
22176  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
22177  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
22178  0u,
22179  NULL },
22180  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
22181  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
22182  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
22183  0u,
22184  NULL },
22185  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22186  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22187  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22188  0u,
22189  NULL },
22190  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22191  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22192  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22193  0u,
22194  NULL },
22195  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22196  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22197  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22198  0u,
22199  NULL },
22200  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22201  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22202  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22203  0u,
22204  NULL },
22205  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
22206  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
22207  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
22208  0u,
22209  NULL },
22210  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
22211  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
22212  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
22213  0u,
22214  NULL },
22215  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
22216  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
22217  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
22218  0u,
22219  NULL },
22220  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
22221  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
22222  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
22223  0u,
22224  NULL },
22225  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22226  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22227  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22228  0u,
22229  NULL },
22230  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22231  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22232  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22233  0u,
22234  NULL },
22235  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22236  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22237  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22238  0u,
22239  NULL },
22240  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22241  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22242  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22243  0u,
22244  NULL },
22245  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
22246  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
22247  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
22248  0u,
22249  NULL },
22250  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22251  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22252  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22253  0u,
22254  NULL },
22255  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22256  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22257  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22258  0u,
22259  NULL },
22260  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22261  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22262  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22263  0u,
22264  NULL },
22265  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22266  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22267  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22268  0u,
22269  NULL },
22270  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
22271  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
22272  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
22273  0u,
22274  NULL },
22275  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
22276  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
22277  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
22278  0u,
22279  NULL },
22280  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
22281  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
22282  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
22283  0u,
22284  NULL },
22285  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
22286  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
22287  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
22288  0u,
22289  NULL },
22290 };
22291 
22296 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS] =
22297 {
22298  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
22299  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
22300  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
22301  0u,
22302  NULL },
22303  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
22304  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
22305  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
22306  0u,
22307  NULL },
22308  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
22309  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
22310  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
22311  0u,
22312  NULL },
22313  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
22314  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
22315  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
22316  0u,
22317  NULL },
22318  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
22319  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
22320  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
22321  0u,
22322  NULL },
22323  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
22324  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
22325  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
22326  0u,
22327  NULL },
22328  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22329  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22330  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22331  0u,
22332  NULL },
22333  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22334  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22335  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22336  0u,
22337  NULL },
22338  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22339  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22340  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22341  0u,
22342  NULL },
22343  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22344  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22345  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22346  0u,
22347  NULL },
22348  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
22349  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
22350  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
22351  0u,
22352  NULL },
22353  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
22354  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
22355  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
22356  0u,
22357  NULL },
22358  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
22359  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
22360  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
22361  0u,
22362  NULL },
22363  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
22364  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
22365  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
22366  0u,
22367  NULL },
22368  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22369  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22370  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22371  0u,
22372  NULL },
22373  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22374  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22375  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22376  0u,
22377  NULL },
22378  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22379  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22380  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22381  0u,
22382  NULL },
22383  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22384  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22385  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22386  0u,
22387  NULL },
22388  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
22389  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
22390  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
22391  0u,
22392  NULL },
22393  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22394  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22395  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22396  0u,
22397  NULL },
22398  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22399  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22400  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22401  0u,
22402  NULL },
22403  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22404  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22405  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22406  0u,
22407  NULL },
22408  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22409  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22410  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22411  0u,
22412  NULL },
22413  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
22414  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
22415  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
22416  0u,
22417  NULL },
22418  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
22419  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
22420  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
22421  0u,
22422  NULL },
22423  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
22424  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
22425  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
22426  0u,
22427  NULL },
22428  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
22429  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
22430  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
22431  0u,
22432  NULL },
22433 };
22434 
22439 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS] =
22440 {
22441  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
22442  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
22443  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
22444  0u,
22445  NULL },
22446  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
22447  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
22448  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
22449  0u,
22450  NULL },
22451  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
22452  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
22453  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
22454  0u,
22455  NULL },
22456  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
22457  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
22458  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
22459  0u,
22460  NULL },
22461  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
22462  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
22463  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
22464  0u,
22465  NULL },
22466  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
22467  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
22468  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
22469  0u,
22470  NULL },
22471  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22472  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22473  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22474  0u,
22475  NULL },
22476  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22477  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22478  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22479  0u,
22480  NULL },
22481  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22482  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22483  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22484  0u,
22485  NULL },
22486  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22487  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22488  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22489  0u,
22490  NULL },
22491  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
22492  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
22493  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
22494  0u,
22495  NULL },
22496  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
22497  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
22498  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
22499  0u,
22500  NULL },
22501  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
22502  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
22503  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
22504  0u,
22505  NULL },
22506  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
22507  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
22508  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
22509  0u,
22510  NULL },
22511  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22512  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22513  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22514  0u,
22515  NULL },
22516  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22517  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22518  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22519  0u,
22520  NULL },
22521  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22522  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22523  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22524  0u,
22525  NULL },
22526  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22527  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22528  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22529  0u,
22530  NULL },
22531  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
22532  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
22533  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
22534  0u,
22535  NULL },
22536  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
22537  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
22538  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
22539  0u,
22540  NULL },
22541  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
22542  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
22543  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
22544  0u,
22545  NULL },
22546  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
22547  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
22548  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
22549  0u,
22550  NULL },
22551  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
22552  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
22553  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
22554  0u,
22555  NULL },
22556  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
22557  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
22558  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
22559  0u,
22560  NULL },
22561  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
22562  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
22563  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
22564  0u,
22565  NULL },
22566  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
22567  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
22568  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
22569  0u,
22570  NULL },
22571  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
22572  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
22573  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
22574  0u,
22575  NULL },
22576 };
22577 
22582 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS] =
22583 {
22584  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
22585  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
22586  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
22587  0u,
22588  NULL },
22589  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
22590  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
22591  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
22592  0u,
22593  NULL },
22594  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
22595  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
22596  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
22597  0u,
22598  NULL },
22599  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
22600  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
22601  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
22602  0u,
22603  NULL },
22604  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID,
22605  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_INJECT_TYPE,
22606  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ECC_TYPE,
22607  0u,
22608  NULL },
22609  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID,
22610  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_INJECT_TYPE,
22611  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ECC_TYPE,
22612  0u,
22613  NULL },
22614  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID,
22615  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_INJECT_TYPE,
22616  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ECC_TYPE,
22617  0u,
22618  NULL },
22619  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID,
22620  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_INJECT_TYPE,
22621  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ECC_TYPE,
22622  0u,
22623  NULL },
22624  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID,
22625  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_INJECT_TYPE,
22626  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ECC_TYPE,
22627  0u,
22628  NULL },
22629  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID,
22630  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_INJECT_TYPE,
22631  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ECC_TYPE,
22632  0u,
22633  NULL },
22634  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID,
22635  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_INJECT_TYPE,
22636  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ECC_TYPE,
22637  0u,
22638  NULL },
22639  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID,
22640  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_INJECT_TYPE,
22641  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ECC_TYPE,
22642  0u,
22643  NULL },
22644  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID,
22645  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_INJECT_TYPE,
22646  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ECC_TYPE,
22647  0u,
22648  NULL },
22649  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID,
22650  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_INJECT_TYPE,
22651  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ECC_TYPE,
22652  0u,
22653  NULL },
22654  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID,
22655  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_INJECT_TYPE,
22656  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ECC_TYPE,
22657  0u,
22658  NULL },
22659  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID,
22660  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_INJECT_TYPE,
22661  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ECC_TYPE,
22662  0u,
22663  NULL },
22664  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID,
22665  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_INJECT_TYPE,
22666  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ECC_TYPE,
22667  0u,
22668  NULL },
22669  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID,
22670  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_INJECT_TYPE,
22671  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ECC_TYPE,
22672  0u,
22673  NULL },
22674  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID,
22675  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_INJECT_TYPE,
22676  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ECC_TYPE,
22677  0u,
22678  NULL },
22679  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID,
22680  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_INJECT_TYPE,
22681  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ECC_TYPE,
22682  0u,
22683  NULL },
22684  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID,
22685  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_INJECT_TYPE,
22686  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ECC_TYPE,
22687  0u,
22688  NULL },
22689  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID,
22690  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_INJECT_TYPE,
22691  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ECC_TYPE,
22692  0u,
22693  NULL },
22694  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID,
22695  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_INJECT_TYPE,
22696  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ECC_TYPE,
22697  0u,
22698  NULL },
22699  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID,
22700  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_INJECT_TYPE,
22701  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ECC_TYPE,
22702  0u,
22703  NULL },
22704 };
22705 
22710 static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
22711 {
22712  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
22713  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
22714  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
22715  0u,
22716  NULL },
22717  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
22718  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
22719  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
22720  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
22722 };
22723 
22728 static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
22729 {
22730  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
22731  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
22732  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
22733  0u,
22734  NULL },
22735  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
22736  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
22737  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
22738  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
22740 };
22741 
22746 static const SDL_RAMIdEntry_t SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RamIdTable[SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_NUM_RAMS] =
22747 {
22748  { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID,
22749  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_INJECT_TYPE,
22750  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_ECC_TYPE,
22751  0u,
22752  NULL },
22753  { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID,
22754  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_INJECT_TYPE,
22755  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_ECC_TYPE,
22756  0u,
22757  NULL },
22758  { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID,
22759  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_INJECT_TYPE,
22760  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_ECC_TYPE,
22761  0u,
22762  NULL },
22763  { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
22764  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
22765  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
22766  0u,
22767  NULL },
22768 };
22769 
22774 static const SDL_RAMIdEntry_t SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RamIdTable[SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_NUM_RAMS] =
22775 {
22776  { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID,
22777  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_INJECT_TYPE,
22778  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_ECC_TYPE,
22779  0u,
22780  NULL },
22781  { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID,
22782  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_INJECT_TYPE,
22783  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ECC_TYPE,
22784  0u,
22785  NULL },
22786  { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID,
22787  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_INJECT_TYPE,
22788  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_ECC_TYPE,
22789  0u,
22790  NULL },
22791  { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID,
22792  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_INJECT_TYPE,
22793  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_ECC_TYPE,
22794  0u,
22795  NULL },
22796 };
22797 
22799 {
22800  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_R5FSS0_CORE0_ECC_AGGR_BASE)), //0
22801  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_R5FSS0_CORE0_ECC_AGGR_BASE)), //1
22802  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DSS_DSI0_DSI_TOP_ECC_AGGR_SYS_CFG_BASE)), //2
22803  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC0_ECC_AGGR_BASE)), //3
22804  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC1_ECC_AGGR_BASE)), //4
22805  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR2_ECC_AGGR_BASE)), //5
22806  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMPAC0_DMPAC_TOP_CFG_SLV_KSDW_ECC_AGGR_CFG_BASE)), //6
22807  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGGR0_ECC_AGGR_BASE)), //7
22808  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_256K1_ECC_AGGR_REGS_BASE)), //8
22809  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_VTM0_ECCAGGR_CFG_BASE)), //9
22810  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR1_ECC_AGGR_BASE)), //10
22811  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_FSS0_OSPI0_ECC_AGGR_BASE)), //11
22812  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_R5FSS0_CORE0_ECC_AGGR_BASE)), //12
22813  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_GICSS0_REGS_BASE)), //13
22814  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_BASE)), //14
22815  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_RX_IF3_ECC_AGGR_CFG_BASE)), //15
22816  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_RX_IF1_ECC_AGGR_CFG_BASE)), //16
22817  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_RX_IF0_ECC_AGGR_CFG_BASE)), //17
22818  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSCSS0_REGS_BASE)), //18
22819  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_RXMEM_BASE)), //19
22820  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_TXMEM_BASE )), //20
22821  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SMS0_ECC_AGGR_BASE)), //21
22822  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SA3_SS0_ECCAGGR_CFG_BASE)), //22
22823  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSRAM8KX256E0_ECC_AGGR_REGS_BASE)), //23
22824  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_TX_IF0_ECC_AGGR_CFG_BASE)), //24
22825  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_TX_IF0_ECC_AGGR_BYTE_CFG_BASE)), //25
22826  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR0_ECC_AGGR_BASE)), //26
22827  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMASS0_ECCAGGR_BASE)), //27
22828  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA0_BASE)), //28
22829  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ECC_AGGR1_ECC_AGGR_BASE)), //29
22830  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB0_ECC_AGGR_BASE)), //30
22831  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_256K0_ECC_AGGR_REGS_BASE)), //31
22832  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_RXMEM_BASE)), //32
22833  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_TXMEM_BASE)), //33
22834  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB1_ECC_AGGR_BASE)), //34
22835  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_VPAC0_IVPAC_TOP_0_CFG_SLV_KSDW_ECC_AGGR_CFG_BASE )), //35
22836  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_VPAC0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_LDC0_S_VBUSP_KSDW_ECC_AGGR_CFG_BASE)), //36
22837  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_VPAC0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_KSDW_ECC_AGGR_CFG_BASE)), //37
22838  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_PSRAMECC_8K0_REGS_BASE)), //38
22839  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_C7X256V0_ECC_AGGR_BASE)), //39
22840  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA1_BASE)), //40
22841  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_C7X256V1_ECC_AGGR_BASE)), //41
22842  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ECC_AGGR0_ECC_AGGR_BASE)), //42
22843  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_RX_IF2_ECC_AGGR_CFG_BASE)), //43
22844  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN1_ECC_AGGR_BASE)), //44
22845  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_AGGR_BASE)), //45
22846  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_TXMEM_BASE)), //46
22847  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_RXMEM_BASE)), //47
22848  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMASS1_ECCAGGR_BASE)), //48
22849  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE0_ECC_AGGR_BASE)), //49
22850  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE1_ECC_AGGR_BASE )), //50
22851  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE2_ECC_AGGR_BASE )), //51
22852  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE3_ECC_AGGR_BASE)), //52
22853  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_SS_ECC_AGGR_BASE)), //53
22854  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN0_ECC_AGGR_BASE )), //54
22855  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN1_ECC_AGGR_BASE)), //55
22856  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PCIE0_CORE_ECC_AGGR0_BASE)), //56
22857  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PCIE0_CORE_ECC_AGGR1_BASE)), //57
22858 };
22859 
22865 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
22866 {
22867  {
22868  /* Index: SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR (0u) */
22869  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS,
22874  SDLR_ESM0_ESM_LVL_EVENT_WKUP_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
22875  SDLR_ESM0_ESM_LVL_EVENT_WKUP_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0,
22876  },
22877  {
22878  /* Index : SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR (1U) */
22879  SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS,
22884  SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
22885  SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0,
22886  },
22887  {
22888  /* Index : SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS (2U) */
22889  SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS,
22892  NULL,
22894  SDLR_ESM0_ESM_LVL_EVENT_DSS_DSI0_DSI_0_SAFETY_ERROR_FATAL_INTR_0,
22895  SDLR_ESM0_ESM_LVL_EVENT_DSS_DSI0_ECC_INTR_UNCORR_LEVEL_SYS_0,
22896  },
22897  { /* Index : SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR (3U) */
22898  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
22903  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_CORR_LEVEL_0,
22904  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_UNCORR_LEVEL_0,
22905  },
22906  {
22907  /* Index : SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR (4U) */
22908  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
22913  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC1_ECC_CORR_LEVEL_0,
22914  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC1_ECC_UNCORR_LEVEL_0,
22915  },
22916  {
22917  /* Index : SDL_WKUP_ECC_AGGR2 (5U) */
22918  SDL_WKUP_ECC_AGGR2_NUM_RAMS,
22921  NULL,
22923  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR2_CORR_LEVEL_0,
22924  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR2_UNCORR_LEVEL_0,
22925 
22926  },
22927  { /* Index : SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR (6U) */
22928  SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_NUM_RAMS,
22933  SDLR_ESM0_ESM_PLS_EVENT1_DMPAC0_ECC_CORRECTED_ERR_PULSE_0,
22934  SDLR_ESM0_ESM_PLS_EVENT1_DMPAC0_ECC_UNCORRECTED_ERR_PULSE_0,
22935  },
22936  { /* Index : SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR (7U) */
22937  SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_NUM_RAMS,
22942  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_CORR_LEVEL_0,
22943  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_UNCORR_LEVEL_0,
22944  },
22945  { /* Index : SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR (8U) */
22946  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
22951  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K1_ECC_CORR_LEVEL_0,
22952  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K1_ECC_UNCORR_LEVEL_0,
22953 
22954  },
22955  { /* Index : SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR (9U) */
22956  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS,
22959  NULL,
22961  SDLR_ESM0_ESM_LVL_EVENT_WKUP_VTM0_CORR_LEVEL_0,
22962  SDLR_ESM0_ESM_LVL_EVENT_WKUP_VTM0_UNCORR_LEVEL_0,
22963  },
22964  { /* Index : SDL_WKUP_ECC_AGGR1 (10U) */
22965  SDL_WKUP_ECC_AGGR1_NUM_RAMS,
22968  NULL,
22970  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR1_CORR_LEVEL_0,
22971  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR1_UNCORR_LEVEL_0,
22972  },
22973  { /* Index : SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR (11U) */
22974  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS,
22979  SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0,
22980  SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0
22981  },
22982  { /* Index : SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR (12U) */
22983  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS,
22988  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CPU0_ECC_AGGR_0_CPU0_ECC_CORRECTED_LEVEL_0,
22989  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CPU0_ECC_AGGR_0_CPU0_ECC_UNCORRECTED_LEVEL_0,
22990  },
22991  { /* Index : SDL_GICSS0_GIC500SS_1_4_ECC_AGGR (13U) */
22992  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS,
22997  SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_CORR_LEVEL_0,
22998  SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_UNCORR_LEVEL_0,
22999  },
23000  { /* Index : SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR (14U) */
23001  SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS,
23006  SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_SEC_PEND_0,
23007  SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_DED_PEND_0,
23008  },
23009  { /* Index : SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR (15U) */
23010  SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_NUM_RAMS,
23015  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF3_CORR_LEVEL_0,
23016  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF3_UNCORR_LEVEL_0,
23017  },
23018  { /* Index : SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR (16U) */
23019  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_NUM_RAMS,
23024  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF1_CORR_LEVEL_0,
23025  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF1_UNCORR_LEVEL_0,
23026  },
23027  { /* Index : SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR (17U) */
23028  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS,
23033  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF0_CORR_LEVEL_0,
23034  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF0_UNCORR_LEVEL_0,
23035  },
23036  { /* Index : SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR (18U) */
23037  SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS,
23042  SDLR_ESM0_ESM_LVL_EVENT_PSC0_ECC_AGGR_0_FW_CH_BR_ECC_AGGR_CORR_LEVEL_0,
23043  SDLR_ESM0_ESM_LVL_EVENT_PSC0_ECC_AGGR_0_FW_CH_BR_ECC_AGGR_UNCORR_LEVEL_0,
23044  },
23045  { /* Index : SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM (19U) */
23046  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
23051  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
23052  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0,
23053  },
23054  { /* Index : SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM (20U) */
23055  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
23060  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
23061  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
23062  },
23063  { /* Index : SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR (21U) */
23064  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS,
23069  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_SEC_PEND_0,
23070  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_DED_PEND_0,
23071  },
23072  { /* Index : SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR (22U) */
23073  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS,
23078  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_CORR_LEVEL_0,
23079  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_UNCORR_LEVEL_0,
23080  },
23081  { /* Index: SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR (23U) */
23082  SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_NUM_RAMS,
23087  SDLR_ESM0_ESM_LVL_EVENT_MSRAM8KX256E0_ECC_CORR_LEVEL_0,
23088  SDLR_ESM0_ESM_LVL_EVENT_MSRAM8KX256E0_ECC_UNCORR_LEVEL_0,
23089  },
23090  { /* Index : SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR (24U) */
23091  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_NUM_RAMS,
23096  SDLR_ESM0_ESM_LVL_EVENT_CSI_TX_IF0_CORR_LEVEL_0,
23097  SDLR_ESM0_ESM_LVL_EVENT_CSI_TX_IF0_UNCORR_LEVEL_0,
23098  },
23099  { /* Index : SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE (25U) */
23100  SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_NUM_RAMS,
23105  0u,
23106  0u,
23107  },
23108  {
23109  /* Index : SDL_WKUP_ECC_AGGR0 (26U) */
23110  SDL_WKUP_ECC_AGGR0_NUM_RAMS,
23113  NULL,
23115  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_CORR_LEVEL_0,
23116  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_UNCORR_LEVEL_0,
23117  },
23118  { /* Index : SDL_DMASS0_ECC_AGGR_0 (27U) */
23119  SDL_DMASS0_ECC_AGGR_0_NUM_RAMS,
23124  SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
23125  SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
23126  },
23127  { /* Index : SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR (28U) */
23128  SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_NUM_RAMS,
23133  SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_SEC_PEND_0,
23134  SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_DED_PEND_0,
23135  },
23136  { /* Index : SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR (29U) */
23137  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS,
23140  NULL,
23142  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR1_CORR_LEVEL_0,
23143  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR1_UNCORR_LEVEL_0,
23144  },
23145  { /* Index : SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR (30U) */
23146  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS,
23151  SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
23152  SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0,
23153  },
23154  { /* Index : SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR (31U) */
23155  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
23160  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K0_ECC_CORR_LEVEL_0,
23161  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K0_ECC_UNCORR_LEVEL_0,
23162  },
23163  { /* Index : SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (32U) */
23164  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
23169  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
23170  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0,
23171  },
23172  { /* Index : SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (33U) */
23173  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
23178  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
23179  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0,
23180  },
23181  { /* Index : SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR (34U) */
23182  SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_NUM_RAMS,
23187  SDLR_ESM0_ESM_LVL_EVENT_USB1_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
23188  SDLR_ESM0_ESM_LVL_EVENT_USB1_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0,
23189  },
23190  { /* Index : SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR (35U) */
23191  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_NUM_RAMS,
23196  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_ECC_INTR0_CORR_LEVEL_0,
23197  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_ECC_INTR0_UNCORR_LEVEL_0,
23198  },
23199  { /* Index : SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR (36U) */
23200  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_NUM_RAMS,
23205  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_ECC_INTR3_CORR_LEVEL_0,
23206  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_ECC_INTR3_UNCORR_LEVEL_0,
23207  },
23208  { /* Index : SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR (37U) */
23209  SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_NUM_RAMS,
23214  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_ECC_INTR1_CORR_LEVEL_0,
23215  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_ECC_INTR1_UNCORR_LEVEL_0,
23216  },
23217  { /* Index : SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR (38U) */
23218  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS,
23223  SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAMECC_8K0_ECC_CORR_LEVEL_0,
23224  SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAMECC_8K0_ECC_UNCORR_LEVEL_0,
23225  },
23226  { /* Index : SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR (39U) */
23227  SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_NUM_RAMS,
23232  SDLR_ESM0_ESM_LVL_EVENT_C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_1,
23233  SDLR_ESM0_ESM_LVL_EVENT_C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_0,
23234  },
23235  { /* Index : SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR (40U) */
23236  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS,
23241  SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_SEC_PEND_0,
23242  SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_DED_PEND_0,
23243  },
23244  { /* Index : SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR (41U) */
23245  SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_NUM_RAMS,
23250  SDLR_ESM0_ESM_LVL_EVENT_C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_1,
23251  SDLR_ESM0_ESM_LVL_EVENT_C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_0,
23252  },
23253  { /* Index : SDL_MCU_ECC_AGGR0 (42U) */
23254  SDL_MCU_ECC_AGGR0_NUM_RAMS,
23259  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0,
23260  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0,
23261  },
23262  { /* Index: SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR (43U) */
23263  SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_NUM_RAMS,
23268  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF2_CORR_LEVEL_0,
23269  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF2_UNCORR_LEVEL_0,
23270  },
23271  { /* Index : SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (44U) */
23272  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
23277  SDLR_ESM0_ESM_LVL_EVENT_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
23278  SDLR_ESM0_ESM_LVL_EVENT_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0,
23279  },
23280  { /* Index : SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (45U) */
23281  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
23286  SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
23287  SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0,
23288  },
23289  { /* Index : SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM (46U) */
23290  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_NUM_RAMS,
23295  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_TXMEM_CORR_ERR_LVL_0,
23296  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_TXMEM_UNCORR_ERR_LVL_0,
23297  },
23298  { /* Index : SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM (47U) */
23299  SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_NUM_RAMS,
23304  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_RXMEM_CORR_ERR_LVL_0,
23305  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_RXMEM_UNCORR_ERR_LVL_0,
23306  },
23307  { /* Index : SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR (48U) */
23308  SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_NUM_RAMS,
23313  SDLR_ESM0_ESM_LVL_EVENT_DMASS1_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
23314  SDLR_ESM0_ESM_LVL_EVENT_DMASS1_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0,
23315 
23316  },
23317  { /* Index : SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0 (49U) */
23318  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS,
23323  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_CORRECTED_ERR_LEVEL_0,
23324  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_UNCORRECTED_ERR_LEVEL_0,
23325  },
23326  { /* Index : SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 (50U) */
23327  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS,
23332  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_CORRECTED_ERR_LEVEL_0,
23333  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_UNCORRECTED_ERR_LEVEL_0,
23334  },
23335  { /* Index : SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2 (51U) */
23336  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS,
23341  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR2_CORRECTED_ERR_LEVEL_0,
23342  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR2_UNCORRECTED_ERR_LEVEL_0,
23343  },
23344  { /* Index : SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3 (52U) */
23345  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS,
23350  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR3_CORRECTED_ERR_LEVEL_0,
23351  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR3_UNCORRECTED_ERR_LEVEL_0,
23352  },
23353  { /* Index : SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC (53U) */
23354  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS,
23359  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_CORRECTED_ERR_LEVEL_0,
23360  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_UNCORRECTED_ERR_LEVEL_0,
23361  },
23362  { /* Index : SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (54U) */
23363  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
23368  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
23369  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0,
23370  },
23371  { /* Index : SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (55U) */
23372  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
23377  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
23378  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0,
23379  },
23380  { /* Index : SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR (56U) */
23381  /*Not sure for below interrupt*/
23382  SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_NUM_RAMS,
23387  SDLR_ESM0_ESM_LVL_EVENT_PCIE0_PCIE_ECC0_CORR_LEVEL_0,
23388  SDLR_ESM0_ESM_LVL_EVENT_PCIE0_PCIE_ECC0_UNCORR_LEVEL_0,
23389  },
23390  { /* Index : SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR (57U) */
23391  /*Not sure for below interrupt*/
23392  SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_NUM_RAMS,
23397  0u,
23398  0u,
23399  },
23400 };
23401 
23402 #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:58
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:21929
SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable[SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20282
SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13585
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14647
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14875
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:5906
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15926
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:96
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:87
SDL_ESM_INST_MAIN_ESM0
@ SDL_ESM_INST_MAIN_ESM0
Definition: sdl_esm_soc.h:59
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS]
Definition: sdl_ecc_soc.h:22439
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19233
SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13108
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10971
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:77
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11288
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13993
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:102
SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM67_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4264
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6690
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9198
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:22865
SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:86
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:21022
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14466
SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_MemEntries[SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:11640
SDL_WKUP_ECC_AGGR2_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR2_RamIdTable[SDL_WKUP_ECC_AGGR2_NUM_RAMS]
Definition: sdl_ecc_soc.h:19578
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11661
SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5839
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14361
SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6453
SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_MemEntries[SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:4284
SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:95
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19777
SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6525
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:75
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13651
SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6495
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:13148
SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13574
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4357
SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_ISAM67_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14179
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9767
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2875
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3016
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:69
sdl_esm_soc.h
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS]
Definition: sdl_ecc_soc.h:22582
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21533
SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:64
SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5626
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12352
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:21009
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:110
SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_ISAM67_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2864
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10850
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:103
SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_MemEntries[SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:10457
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:78
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18051
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:61
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8750
SDL_ecc_aggrRegs
Definition: V0/sdlr_ecc.h:53
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19552
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:325
NULL
#define NULL
Define NULL if not defined.
Definition: csl_types.h:100
SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION
#define SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION
Definition: sdl_ecc_soc.h:5905
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14497
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:98
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6888
SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_MemEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:13168
SDL_WKUP_ECC_AGGR1_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR1_RamIdTable[SDL_WKUP_ECC_AGGR1_NUM_RAMS]
Definition: sdl_ecc_soc.h:19828
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4525
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19709
SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:869
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9552
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7409
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20968
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14898
SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_RamIdTable[SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20645
SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:217
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:20295
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6843
SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:83
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18647
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10090
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7828
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14832
SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_MemEntries[SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6579
SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_RamIdTable[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21485
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17740
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:336
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19183
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19800
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_AM67_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17556
SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:73
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14964
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6239
SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20897
SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RamIdTable[SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22746
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11453
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18330
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18603
SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:106
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14717
SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12709
SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:114
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14941
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4586
SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21048
SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1990
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22710
SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12724
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9237
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ERR_SCR_AM67_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17787
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18625
SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18561
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6169
SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RamIdTable[SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21035
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6537
SDL_DMASS0_ECC_AGGR_0_MemEntries
static const SDL_MemConfig_t SDL_DMASS0_ECC_AGGR_0_MemEntries[SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:11548
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12669
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20067
SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_MemEntries[SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:10468
SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5477
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:22860
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:71
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS]
Definition: sdl_ecc_soc.h:22010
SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries[SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:313
SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5816
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4642
SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_RamIdTable[SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21942
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18658
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18713
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14577
SDL_WKUP_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:63
SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19386
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:107
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8116
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:70
SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13097
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12187
SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21154
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10928
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6208
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14682
SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:93
SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_MemEntries[SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12394
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20925
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:111
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:122
SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_SAM67_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11528
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4798
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9211
SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR1_SAM67_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5870
SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:72
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13790
SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:82
SDL_DMASS0_ECC_AGGR_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_DMASS0_ECC_AGGR_0_RamIdTable[SDL_DMASS0_ECC_AGGR_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:20749
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18802
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14540
SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:94
SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:81
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:108
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18615
SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6421
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:109
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7675
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10067
SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13197
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6404
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9119
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12167
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6669
SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_MemEntries[SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:19213
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:71
SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2511
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21472
SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_USB1_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:92
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6612
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18980
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:20308
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10893
SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13086
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:79
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_AM67_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15485
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3873
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14140
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_AM67_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16447
SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:348
SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_MemEntries[SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:19193
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ERR_SCR_AM67_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3920
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6601
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12372
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:89
SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSCSS0_SAM67_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:76
SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_ISAM67_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14190
SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_MemEntries[SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12475
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19871
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11947
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11143
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21880
SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6483
SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_RamIdTable[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21561
SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM8KX256E0_MSRAM8KX256E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20632
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4937
SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21832
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:113
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12094
SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:115
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM67_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2946
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19884
SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_groupEntries[SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_CSI_TX_IF_V2_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10483
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:91
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:4786
SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:99
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_AM67_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17628
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:19171
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12111
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6567
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8470
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:19069
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:104
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4675
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10679
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_MemEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:4310
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9040
SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_RamIdTable[SDL_DMPAC0_SAM67_DMPAC_WRAP_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_KSDW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19671
SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21086
SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13596
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12383
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20234
SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RamIdTable[SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22774
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8961
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4731
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17245
SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM67XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1469
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM67_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3854
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8401
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10281
SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_MemEntries[SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12431
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4625
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12201
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:22798
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4013
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18637
SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12692
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS]
Definition: sdl_ecc_soc.h:22296
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM67_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14797
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8326
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:65
SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1354
SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20186
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20986
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:10413
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM67_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2981
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12150
SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_AM67_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20090
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:90
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:46
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20321
SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13212
SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM67_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3537
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17581
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8101
SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_MemEntries[SDL_DMASS1_DMSS_CSI_AM67_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18669
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8251
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:67
SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_MCU_FW_CBASS_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM67_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5773
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4392
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20564
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4958
SDL_MCU_ECC_AGGR0_MemEntries
static const SDL_MemConfig_t SDL_MCU_ECC_AGGR0_MemEntries[SDL_MCU_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:13636
SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM67_WKUP_DM_CBASS_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM67_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5454
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:80
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM67_WKUP_DM_CBASS_EXPORT_AM67_WKUP_DM_CBASS_TO_AM67_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10994
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18891
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19161
SDL_ECC_Base_Address_TOTAL_ENTRIES
#define SDL_ECC_Base_Address_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:116
SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13180
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14404
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6086
SDL_MCU_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR0_RamIdTable[SDL_MCU_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:21609
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7532
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:19565
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17880
SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13069
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11808
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14612
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4979
SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_MemEntries[SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12680
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:62
SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:74
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:112
SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM67_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18541
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10038
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14423
SDL_MCU_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:100
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:21898
SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES
#define SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:60
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:87
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_AM67_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17721
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:5890
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13846
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:105
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6590
SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF3_CSI_RX_IF_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:20138
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12213
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6005
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9224
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4714
SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM67_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10514
SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18591
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6384
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS]
Definition: sdl_ecc_soc.h:22153
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5330
sdl_ecc_priv.h
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_AM67_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16724
SDL_ESM_INST_WKUP_ESM0
@ SDL_ESM_INST_WKUP_ESM0
Definition: sdl_esm_soc.h:57
SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:21916
SDL_WKUP_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:84
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:66
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4770
SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_MemEntries[SDL_VPAC0_SAM67_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:12405
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9331
SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM67_SEC_HSM_ECC_AGGR_AM67_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4322
SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_RX_IF2_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:101
SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RamIdTable
static const SDL_RAMIdEntry_t SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_RamIdTable[SDL_DSS_DSI0_K3_DSS_DSI_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS]
Definition: sdl_ecc_soc.h:19539
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5345
SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:85
SDL_WKUP_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:68
SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_MemEntries
static const SDL_MemConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_MemEntries[SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:10499
SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:59
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:88
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:19149
SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V1_SAM67_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13557
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22728
SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_RamIdTable[SDL_CSI_TX_IF0_CSI_TX_IF_V2_ECC_AGGR_BYTE_NUM_RAMS]
Definition: sdl_ecc_soc.h:20668
SDL_WKUP_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_RamIdTable[SDL_WKUP_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:20686
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8539
SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13829
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9316
SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_AM67_MCU_CBASS_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM67_MCU_CBASS_TO_AM67_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14760
SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_C7X256V0_SAM67_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:97