TI Autonomous Driving Algorithms (TIADALG) Library User Guide
cslr_UMC.h
Go to the documentation of this file.
1 /********************************************************************
2  * Copyright (C) 2013-2014 Texas Instruments Incorporated.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32 */
33 #ifndef _CSLR_UMC_H_
34 #define _CSLR_UMC_H_
35 
36 #ifdef __cplusplus
37 extern "C"
38 {
39 #endif
40  //#include <ti/csl/cslr.h>
41  //#include <ti/csl/tistdtypes.h>
42 
43 /**************************************************************************
44 * Field Definition Macros
45 **************************************************************************/
46 
47 /* L2CFG */
48 
49 #define CSL_UMC_L2CFG_RSVD0_MASK (0xFFFFFFFFFFFFFFF0U)
50 #define CSL_UMC_L2CFG_RSVD0_SHIFT (4U)
51 #define CSL_UMC_L2CFG_RSVD0_RESETVAL (0x00000000U)
52 
53 #define CSL_UMC_L2CFG_NOINIT_MASK (0x00000008U)
54 #define CSL_UMC_L2CFG_NOINIT_SHIFT (3U)
55 #define CSL_UMC_L2CFG_NOINIT_RESETVAL (0x00000000U)
56 #define CSL_UMC_L2CFG_NOINIT_MAX (0x00000001U)
57 
58 #define CSL_UMC_L2CFG_L2MODE_MASK (0x00000007U)
59 #define CSL_UMC_L2CFG_L2MODE_SHIFT (0U)
60 #define CSL_UMC_L2CFG_L2MODE_RESETVAL (0x00000000U)
61 #define CSL_UMC_L2CFG_L2MODE_MAX (0x00000007U)
62 
63 #define CSL_UMC_L2CFG_RESETVAL (0x00000000U)
64 
65 /* L2CC */
66 
67 #define CSL_UMC_L2CC_RSVD0_MASK (0xFFFFFFFFFFFFFFF8U)
68 #define CSL_UMC_L2CC_RSVD0_SHIFT (3U)
69 #define CSL_UMC_L2CC_RSVD0_RESETVAL (0x00000000U)
70 
71 #define CSL_UMC_L2CC_POPER_MASK (0x00000004U)
72 #define CSL_UMC_L2CC_POPER_SHIFT (2U)
73 #define CSL_UMC_L2CC_POPER_RESETVAL (0x00000000U)
74 #define CSL_UMC_L2CC_POPER_MAX (0x00000001U)
75 
76 #define CSL_UMC_L2CC_RSVD1_MASK (0x00000002U)
77 #define CSL_UMC_L2CC_RSVD1_SHIFT (1U)
78 #define CSL_UMC_L2CC_RSVD1_RESETVAL (0x00000000U)
79 #define CSL_UMC_L2CC_RSVD1_MAX (0x00000001U)
80 
81 #define CSL_UMC_L2CC_OPER_MASK (0x00000001U)
82 #define CSL_UMC_L2CC_OPER_SHIFT (0U)
83 #define CSL_UMC_L2CC_OPER_RESETVAL (0x00000000U)
84 #define CSL_UMC_L2CC_OPER_MAX (0x00000001U)
85 
86 #define CSL_UMC_L2CC_RESETVAL (0x00000000U)
87 
88 /* L2WB */
89 
90 #define CSL_UMC_L2WB_RSVD0_MASK (0xFFFFFFFFFFFFFFFEU)
91 #define CSL_UMC_L2WB_RSVD0_SHIFT (1U)
92 #define CSL_UMC_L2WB_RSVD0_RESETVAL (0x00000000U)
93 
94 #define CSL_UMC_L2WB_WB_MASK (0x00000001U)
95 #define CSL_UMC_L2WB_WB_SHIFT (0U)
96 #define CSL_UMC_L2WB_WB_RESETVAL (0x00000000U)
97 #define CSL_UMC_L2WB_WB_MAX (0x00000001U)
98 
99 #define CSL_UMC_L2WB_RESETVAL (0x00000000U)
100 
101 /* L2WBINV */
102 
103 #define CSL_UMC_L2WBINV_RSVD0_MASK (0xFFFFFFFFFFFFFFFEU)
104 #define CSL_UMC_L2WBINV_RSVD0_SHIFT (1U)
105 #define CSL_UMC_L2WBINV_RSVD0_RESETVAL (0x00000000U)
106 
107 #define CSL_UMC_L2WBINV_WBINV_MASK (0x00000001U)
108 #define CSL_UMC_L2WBINV_WBINV_SHIFT (0U)
109 #define CSL_UMC_L2WBINV_WBINV_RESETVAL (0x00000000U)
110 #define CSL_UMC_L2WBINV_WBINV_MAX (0x00000001U)
111 
112 #define CSL_UMC_L2WBINV_RESETVAL (0x00000000U)
113 
114 /* L2INV */
115 
116 #define CSL_UMC_L2INV_RSVD0_MASK (0xFFFFFFFFFFFFFFFEU)
117 #define CSL_UMC_L2INV_RSVD0_SHIFT (1U)
118 #define CSL_UMC_L2INV_RSVD0_RESETVAL (0x00000000U)
119 
120 #define CSL_UMC_L2INV_INV_MASK (0x00000001U)
121 #define CSL_UMC_L2INV_INV_SHIFT (0U)
122 #define CSL_UMC_L2INV_INV_RESETVAL (0x00000000U)
123 #define CSL_UMC_L2INV_INV_MAX (0x00000001U)
124 
125 #define CSL_UMC_L2INV_RESETVAL (0x00000000U)
126 
127 /* L2EMUCMD */
128 
129 #define CSL_UMC_L2EMUCMD_RSVD0_MASK (0xFFFFFFFFFFFFFFFCU)
130 #define CSL_UMC_L2EMUCMD_RSVD0_SHIFT (2U)
131 #define CSL_UMC_L2EMUCMD_RSVD0_RESETVAL (0x00000000U)
132 
133 #define CSL_UMC_L2EMUCMD_TAGMOD_MASK (0x00000002U)
134 #define CSL_UMC_L2EMUCMD_TAGMOD_SHIFT (1U)
135 #define CSL_UMC_L2EMUCMD_TAGMOD_RESETVAL (0x00000000U)
136 #define CSL_UMC_L2EMUCMD_TAGMOD_MAX (0x00000001U)
137 
138 #define CSL_UMC_L2EMUCMD_FRZ_MASK (0x00000001U)
139 #define CSL_UMC_L2EMUCMD_FRZ_SHIFT (0U)
140 #define CSL_UMC_L2EMUCMD_FRZ_RESETVAL (0x00000000U)
141 #define CSL_UMC_L2EMUCMD_FRZ_MAX (0x00000001U)
142 
143 #define CSL_UMC_L2EMUCMD_RESETVAL (0x00000000U)
144 
145 /* L2CTAG */
146 
147 #define CSL_UMC_L2CTAG_RSVD0_MASK (0xFFFFFFFC00000000U)
148 #define CSL_UMC_L2CTAG_RSVD0_SHIFT (34U)
149 #define CSL_UMC_L2CTAG_RSVD0_RESETVAL (0x00000000U)
150 #define CSL_UMC_L2CTAG_RSVD0_MAX (0x3fffffffU)
151 
152 #define CSL_UMC_L2CTAG_MESI_MASK (0x300000000U)
153 #define CSL_UMC_L2CTAG_MESI_SHIFT (32U)
154 #define CSL_UMC_L2CTAG_MESI_RESETVAL (0x00000000U)
155 #define CSL_UMC_L2CTAG_MESI_MAX (0x00000003U)
156 
157 #define CSL_UMC_L2CTAG_TAG_MASK (0xFFFFFFFFU)
158 #define CSL_UMC_L2CTAG_TAG_SHIFT (0U)
159 #define CSL_UMC_L2CTAG_TAG_RESETVAL (0x00000000U)
160 #define CSL_UMC_L2CTAG_TAG_MAX (0xFFFFFFFFU)
161 
162 #define CSL_UMC_L2CTAG_RESETVAL (0x00000000U)
163 
164 /* L2EDCFG */
165 
166 #define CSL_UMC_L2EDCFG_RSVD0_MASK (0xFFFFFFFFFFFFFFF8U)
167 #define CSL_UMC_L2EDCFG_RSVD0_SHIFT (3U)
168 #define CSL_UMC_L2EDCFG_RSVD0_RESETVAL (0x00000000U)
169 
170 #define CSL_UMC_L2EDCFG_ENABLE_MASK (0x00000004U)
171 #define CSL_UMC_L2EDCFG_ENABLE_SHIFT (2U)
172 #define CSL_UMC_L2EDCFG_ENABLE_RESETVAL (0x00000000U)
173 #define CSL_UMC_L2EDCFG_ENABLE_MAX (0x00000001U)
174 
175 #define CSL_UMC_L2EDCFG_SUSP_MASK (0x00000002U)
176 #define CSL_UMC_L2EDCFG_SUSP_SHIFT (1U)
177 #define CSL_UMC_L2EDCFG_SUSP_RESETVAL (0x00000000U)
178 #define CSL_UMC_L2EDCFG_SUSP_MAX (0x00000001U)
179 
180 #define CSL_UMC_L2EDCFG_SCEN_MASK (0x00000001U)
181 #define CSL_UMC_L2EDCFG_SCEN_SHIFT (0U)
182 #define CSL_UMC_L2EDCFG_SCEN_RESETVAL (0x00000000U)
183 #define CSL_UMC_L2EDCFG_SCEN_MAX (0x00000001U)
184 
185 #define CSL_UMC_L2EDCFG_RESETVAL (0x00000000U)
186 
187 /* L2EDSTAT */
188 
189 #define CSL_UMC_L2EDSTAT_RSVD0_MASK (0xFFFFFFFFFFFFFFF8U)
190 #define CSL_UMC_L2EDSTAT_RSVD0_SHIFT (3U)
191 #define CSL_UMC_L2EDSTAT_RSVD0_RESETVAL (0x00000000U)
192 
193 #define CSL_UMC_L2EDSTAT_ENABLE_MASK (0x00000004U)
194 #define CSL_UMC_L2EDSTAT_ENABLE_SHIFT (2U)
195 #define CSL_UMC_L2EDSTAT_ENABLE_RESETVAL (0x00000000U)
196 #define CSL_UMC_L2EDSTAT_ENABLE_MAX (0x00000001U)
197 
198 #define CSL_UMC_L2EDSTAT_SUSP_MASK (0x00000002U)
199 #define CSL_UMC_L2EDSTAT_SUSP_SHIFT (1U)
200 #define CSL_UMC_L2EDSTAT_SUSP_RESETVAL (0x00000000U)
201 #define CSL_UMC_L2EDSTAT_SUSP_MAX (0x00000001U)
202 
203 #define CSL_UMC_L2EDSTAT_SCEN_MASK (0x00000001U)
204 #define CSL_UMC_L2EDSTAT_SCEN_SHIFT (0U)
205 #define CSL_UMC_L2EDSTAT_SCEN_RESETVAL (0x00000000U)
206 #define CSL_UMC_L2EDSTAT_SCEN_MAX (0x00000001U)
207 
208 #define CSL_UMC_L2EDSTAT_RESETVAL (0x00000000U)
209 
210 /* L2COREDEA */
211 
212 #define CSL_UMC_L2COREDEA_RSVD0_MASK (0xFFFFF00000000000U)
213 #define CSL_UMC_L2COREDEA_RSVD0_SHIFT (44U)
214 #define CSL_UMC_L2COREDEA_RSVD0_RESETVAL (0x00000000U)
215 #define CSL_UMC_L2COREDEA_RSVD0_MAX (0x000fffffU)
216 
217 #define CSL_UMC_L2COREDEA_EADDR_MASK (0xFFFFFFFFFFFU)
218 #define CSL_UMC_L2COREDEA_EADDR_SHIFT (0U)
219 #define CSL_UMC_L2COREDEA_EADDR_RESETVAL (0x00000000U)
220 
221 #define CSL_UMC_L2COREDEA_RESETVAL (0x00000000U)
222 
223 /* L2COREDES */
224 
225 #define CSL_UMC_L2COREDES_RSVD0_MASK (0xFFFFFFFFFFFF8000U)
226 #define CSL_UMC_L2COREDES_RSVD0_SHIFT (15U)
227 #define CSL_UMC_L2COREDES_RSVD0_RESETVAL (0x00000000U)
228 
229 #define CSL_UMC_L2COREDES_BITPOS_MASK (0x00007F80U)
230 #define CSL_UMC_L2COREDES_BITPOS_SHIFT (7U)
231 #define CSL_UMC_L2COREDES_BITPOS_RESETVAL (0x00000000U)
232 #define CSL_UMC_L2COREDES_BITPOS_MAX (0x000000ffU)
233 
234 #define CSL_UMC_L2COREDES_RQSTR_MASK (0x00000060U)
235 #define CSL_UMC_L2COREDES_RQSTR_SHIFT (5U)
236 #define CSL_UMC_L2COREDES_RQSTR_RESETVAL (0x00000000U)
237 #define CSL_UMC_L2COREDES_RQSTR_MAX (0x00000003U)
238 
239 #define CSL_UMC_L2COREDES_MEME_MASK (0x00000018U)
240 #define CSL_UMC_L2COREDES_MEME_SHIFT (3U)
241 #define CSL_UMC_L2COREDES_MEME_RESETVAL (0x00000000U)
242 #define CSL_UMC_L2COREDES_MEME_MAX (0x00000003U)
243 
244 #define CSL_UMC_L2COREDES_BANK_MASK (0x00000006U)
245 #define CSL_UMC_L2COREDES_BANK_SHIFT (1U)
246 #define CSL_UMC_L2COREDES_BANK_RESETVAL (0x00000000U)
247 #define CSL_UMC_L2COREDES_BANK_MAX (0x00000003U)
248 
249 #define CSL_UMC_L2COREDES_ERROR_FLAG_MASK (0x00000001U)
250 #define CSL_UMC_L2COREDES_ERROR_FLAG_SHIFT (0U)
251 #define CSL_UMC_L2COREDES_ERROR_FLAG_RESETVAL (0x00000000U)
252 #define CSL_UMC_L2COREDES_ERROR_FLAG_MAX (0x00000001U)
253 
254 #define CSL_UMC_L2COREDES_RESETVAL (0x00000000U)
255 
256 /* L2COREDER */
257 
258 #define CSL_UMC_L2COREDER_RSVD0_MASK (0xFFFFFFFFFFFFFFFEU)
259 #define CSL_UMC_L2COREDER_RSVD0_SHIFT (1U)
260 #define CSL_UMC_L2COREDER_RSVD0_RESETVAL (0x00000000U)
261 
262 #define CSL_UMC_L2COREDER_ERROR_RESET_MASK (0x00000001U)
263 #define CSL_UMC_L2COREDER_ERROR_RESET_SHIFT (0U)
264 #define CSL_UMC_L2COREDER_ERROR_RESET_RESETVAL (0x00000000U)
265 #define CSL_UMC_L2COREDER_ERROR_RESET_MAX (0x00000001U)
266 
267 #define CSL_UMC_L2COREDER_RESETVAL (0x00000000U)
268 
269 /* L2COREDEC */
270 
271 #define CSL_UMC_L2COREDEC_RSVD0_MASK (0xFFFFFFFF00000000U)
272 #define CSL_UMC_L2COREDEC_RSVD0_SHIFT (32U)
273 #define CSL_UMC_L2COREDEC_RSVD0_RESETVAL (0x00000000U)
274 #define CSL_UMC_L2COREDEC_RSVD0_MAX (0xFFFFFFFFU)
275 
276 #define CSL_UMC_L2COREDEC_ERROR_COUNT_MASK (0xFFFFFFFFU)
277 #define CSL_UMC_L2COREDEC_ERROR_COUNT_SHIFT (0U)
278 #define CSL_UMC_L2COREDEC_ERROR_COUNT_RESETVAL (0x00000000U)
279 #define CSL_UMC_L2COREDEC_ERROR_COUNT_MAX (0xFFFFFFFFU)
280 
281 #define CSL_UMC_L2COREDEC_RESETVAL (0x00000000U)
282 
283 /* L2NCOREDEA */
284 
285 #define CSL_UMC_L2NCOREDEA_RSVD0_MASK (0xFFFFF00000000000U)
286 #define CSL_UMC_L2NCOREDEA_RSVD0_SHIFT (44U)
287 #define CSL_UMC_L2NCOREDEA_RSVD0_RESETVAL (0x00000000U)
288 #define CSL_UMC_L2NCOREDEA_RSVD0_MAX (0x000fffffU)
289 
290 #define CSL_UMC_L2NCOREDEA_EADDR_MASK (0xFFFFFFFFFFFU)
291 #define CSL_UMC_L2NCOREDEA_EADDR_SHIFT (0U)
292 #define CSL_UMC_L2NCOREDEA_EADDR_RESETVAL (0x00000000U)
293 
294 #define CSL_UMC_L2NCOREDEA_RESETVAL (0x00000000U)
295 
296 /* L2NCOREDES */
297 
298 #define CSL_UMC_L2NCOREDES_RSVD0_MASK (0xFFFFFFFFFFFFFF80U)
299 #define CSL_UMC_L2NCOREDES_RSVD0_SHIFT (7U)
300 #define CSL_UMC_L2NCOREDES_RSVD0_RESETVAL (0x00000000U)
301 
302 #define CSL_UMC_L2NCOREDES_RQSTR_MASK (0x00000060U)
303 #define CSL_UMC_L2NCOREDES_RQSTR_SHIFT (5U)
304 #define CSL_UMC_L2NCOREDES_RQSTR_RESETVAL (0x00000000U)
305 #define CSL_UMC_L2NCOREDES_RQSTR_MAX (0x00000003U)
306 
307 #define CSL_UMC_L2NCOREDES_MEME_MASK (0x00000018U)
308 #define CSL_UMC_L2NCOREDES_MEME_SHIFT (3U)
309 #define CSL_UMC_L2NCOREDES_MEME_RESETVAL (0x00000000U)
310 #define CSL_UMC_L2NCOREDES_MEME_MAX (0x00000003U)
311 
312 #define CSL_UMC_L2NCOREDES_BANK_MASK (0x00000006U)
313 #define CSL_UMC_L2NCOREDES_BANK_SHIFT (1U)
314 #define CSL_UMC_L2NCOREDES_BANK_RESETVAL (0x00000000U)
315 #define CSL_UMC_L2NCOREDES_BANK_MAX (0x00000003U)
316 
317 #define CSL_UMC_L2NCOREDES_ERROR_FLAG_MASK (0x00000001U)
318 #define CSL_UMC_L2NCOREDES_ERROR_FLAG_SHIFT (0U)
319 #define CSL_UMC_L2NCOREDES_ERROR_FLAG_RESETVAL (0x00000000U)
320 #define CSL_UMC_L2NCOREDES_ERROR_FLAG_MAX (0x00000001U)
321 
322 #define CSL_UMC_L2NCOREDES_RESETVAL (0x00000000U)
323 
324 /* L2NCOREDER */
325 
326 #define CSL_UMC_L2NCOREDER_RSVD0_MASK (0xFFFFFFFFFFFFFFFEU)
327 #define CSL_UMC_L2NCOREDER_RSVD0_SHIFT (1U)
328 #define CSL_UMC_L2NCOREDER_RSVD0_RESETVAL (0x00000000U)
329 
330 #define CSL_UMC_L2NCOREDER_ERROR_RESET_MASK (0x00000001U)
331 #define CSL_UMC_L2NCOREDER_ERROR_RESET_SHIFT (0U)
332 #define CSL_UMC_L2NCOREDER_ERROR_RESET_RESETVAL (0x00000000U)
333 #define CSL_UMC_L2NCOREDER_ERROR_RESET_MAX (0x00000001U)
334 
335 #define CSL_UMC_L2NCOREDER_RESETVAL (0x00000000U)
336 
337 /* L2NCOREDEC */
338 
339 #define CSL_UMC_L2NCOREDEC_RSVD0_MASK (0xFFFFFFFF00000000U)
340 #define CSL_UMC_L2NCOREDEC_RSVD0_SHIFT (32U)
341 #define CSL_UMC_L2NCOREDEC_RSVD0_RESETVAL (0x00000000U)
342 #define CSL_UMC_L2NCOREDEC_RSVD0_MAX (0xFFFFFFFFU)
343 
344 #define CSL_UMC_L2NCOREDEC_ERROR_COUNT_MASK (0xFFFFFFFFU)
345 #define CSL_UMC_L2NCOREDEC_ERROR_COUNT_SHIFT (0U)
346 #define CSL_UMC_L2NCOREDEC_ERROR_COUNT_RESETVAL (0x00000000U)
347 #define CSL_UMC_L2NCOREDEC_ERROR_COUNT_MAX (0xFFFFFFFFU)
348 
349 #define CSL_UMC_L2NCOREDEC_RESETVAL (0x00000000U)
350 
351 /* L2ADDREEA */
352 
353 #define CSL_UMC_L2ADDREEA_RSVD0_MASK (0xFFFFF00000000000U)
354 #define CSL_UMC_L2ADDREEA_RSVD0_SHIFT (44U)
355 #define CSL_UMC_L2ADDREEA_RSVD0_RESETVAL (0x00000000U)
356 #define CSL_UMC_L2ADDREEA_RSVD0_MAX (0x000fffffU)
357 
358 #define CSL_UMC_L2ADDREEA_EADDR_MASK (0xFFFFFFFFFFFU)
359 #define CSL_UMC_L2ADDREEA_EADDR_SHIFT (0U)
360 #define CSL_UMC_L2ADDREEA_EADDR_RESETVAL (0x00000000U)
361 
362 #define CSL_UMC_L2ADDREEA_RESETVAL (0x00000000U)
363 
364 /* L2ADDREES */
365 
366 #define CSL_UMC_L2ADDREES_RSVD0_MASK (0xFFFFFFFFFFFFFF80U)
367 #define CSL_UMC_L2ADDREES_RSVD0_SHIFT (7U)
368 #define CSL_UMC_L2ADDREES_RSVD0_RESETVAL (0x00000000U)
369 
370 #define CSL_UMC_L2ADDREES_RQSTR_MASK (0x00000060U)
371 #define CSL_UMC_L2ADDREES_RQSTR_SHIFT (5U)
372 #define CSL_UMC_L2ADDREES_RQSTR_RESETVAL (0x00000000U)
373 #define CSL_UMC_L2ADDREES_RQSTR_MAX (0x00000003U)
374 
375 #define CSL_UMC_L2ADDREES_ERROR_TYPE_MASK (0x00000018U)
376 #define CSL_UMC_L2ADDREES_ERROR_TYPE_SHIFT (3U)
377 #define CSL_UMC_L2ADDREES_ERROR_TYPE_RESETVAL (0x00000000U)
378 #define CSL_UMC_L2ADDREES_ERROR_TYPE_MAX (0x00000003U)
379 
380 #define CSL_UMC_L2ADDREES_BANK_MASK (0x00000006U)
381 #define CSL_UMC_L2ADDREES_BANK_SHIFT (1U)
382 #define CSL_UMC_L2ADDREES_BANK_RESETVAL (0x00000000U)
383 #define CSL_UMC_L2ADDREES_BANK_MAX (0x00000003U)
384 
385 #define CSL_UMC_L2ADDREES_ERROR_FLAG_MASK (0x00000001U)
386 #define CSL_UMC_L2ADDREES_ERROR_FLAG_SHIFT (0U)
387 #define CSL_UMC_L2ADDREES_ERROR_FLAG_RESETVAL (0x00000000U)
388 #define CSL_UMC_L2ADDREES_ERROR_FLAG_MAX (0x00000001U)
389 
390 #define CSL_UMC_L2ADDREES_RESETVAL (0x00000000U)
391 
392 /* L2ADDREER */
393 
394 #define CSL_UMC_L2ADDREER_RSVD0_MASK (0xFFFFFFFFFFFFFFFEU)
395 #define CSL_UMC_L2ADDREER_RSVD0_SHIFT (1U)
396 #define CSL_UMC_L2ADDREER_RSVD0_RESETVAL (0x00000000U)
397 
398 #define CSL_UMC_L2ADDREER_ERROR_RESET_MASK (0x00000001U)
399 #define CSL_UMC_L2ADDREER_ERROR_RESET_SHIFT (0U)
400 #define CSL_UMC_L2ADDREER_ERROR_RESET_RESETVAL (0x00000000U)
401 #define CSL_UMC_L2ADDREER_ERROR_RESET_MAX (0x00000001U)
402 
403 #define CSL_UMC_L2ADDREER_RESETVAL (0x00000000U)
404 
405 /* L2ALLOCEEA */
406 
407 #define CSL_UMC_L2ALLOCEEA_RSVD0_MASK (0xFFFFF00000000000U)
408 #define CSL_UMC_L2ALLOCEEA_RSVD0_SHIFT (44U)
409 #define CSL_UMC_L2ALLOCEEA_RSVD0_RESETVAL (0x00000000U)
410 #define CSL_UMC_L2ALLOCEEA_RSVD0_MAX (0x000fffffU)
411 
412 #define CSL_UMC_L2ALLOCEEA_EADDR_MASK (0xFFFFFFFFFFFU)
413 #define CSL_UMC_L2ALLOCEEA_EADDR_SHIFT (0U)
414 #define CSL_UMC_L2ALLOCEEA_EADDR_RESETVAL (0x00000000U)
415 
416 #define CSL_UMC_L2ALLOCEEA_RESETVAL (0x00000000U)
417 
418 /* L2ALLOCEES */
419 
420 #define CSL_UMC_L2ALLOCEES_RSVD0_MASK (0xFFFFFFFFFFFFFF80U)
421 #define CSL_UMC_L2ALLOCEES_RSVD0_SHIFT (7U)
422 #define CSL_UMC_L2ALLOCEES_RSVD0_RESETVAL (0x00000000U)
423 
424 #define CSL_UMC_L2ALLOCEES_RQSTR_MASK (0x00000060U)
425 #define CSL_UMC_L2ALLOCEES_RQSTR_SHIFT (5U)
426 #define CSL_UMC_L2ALLOCEES_RQSTR_RESETVAL (0x00000000U)
427 #define CSL_UMC_L2ALLOCEES_RQSTR_MAX (0x00000003U)
428 
429 #define CSL_UMC_L2ALLOCEES_ERROR_TYPE_MASK (0x00000018U)
430 #define CSL_UMC_L2ALLOCEES_ERROR_TYPE_SHIFT (3U)
431 #define CSL_UMC_L2ALLOCEES_ERROR_TYPE_RESETVAL (0x00000000U)
432 #define CSL_UMC_L2ALLOCEES_ERROR_TYPE_MAX (0x00000003U)
433 
434 #define CSL_UMC_L2ALLOCEES_BANK_MASK (0x00000006U)
435 #define CSL_UMC_L2ALLOCEES_BANK_SHIFT (1U)
436 #define CSL_UMC_L2ALLOCEES_BANK_RESETVAL (0x00000000U)
437 #define CSL_UMC_L2ALLOCEES_BANK_MAX (0x00000003U)
438 
439 #define CSL_UMC_L2ALLOCEES_ERROR_FLAG_MASK (0x00000001U)
440 #define CSL_UMC_L2ALLOCEES_ERROR_FLAG_SHIFT (0U)
441 #define CSL_UMC_L2ALLOCEES_ERROR_FLAG_RESETVAL (0x00000000U)
442 #define CSL_UMC_L2ALLOCEES_ERROR_FLAG_MAX (0x00000001U)
443 
444 #define CSL_UMC_L2ALLOCEES_RESETVAL (0x00000000U)
445 
446 /* L2ALLOCEER */
447 
448 #define CSL_UMC_L2ALLOCEER_RSVD0_MASK (0xFFFFFFFFFFFFFFFEU)
449 #define CSL_UMC_L2ALLOCEER_RSVD0_SHIFT (1U)
450 #define CSL_UMC_L2ALLOCEER_RSVD0_RESETVAL (0x00000000U)
451 
452 #define CSL_UMC_L2ALLOCEER_ERROR_RESET_MASK (0x00000001U)
453 #define CSL_UMC_L2ALLOCEER_ERROR_RESET_SHIFT (0U)
454 #define CSL_UMC_L2ALLOCEER_ERROR_RESET_RESETVAL (0x00000000U)
455 #define CSL_UMC_L2ALLOCEER_ERROR_RESET_MAX (0x00000001U)
456 
457 #define CSL_UMC_L2ALLOCEER_RESETVAL (0x00000000U)
458 
459 #ifdef __cplusplus
460 }
461 #endif
462 #endif

© Copyright 2018 Texas Instruments Incorporated. All rights reserved.
Document generated by doxygen 1.8.6