How to Disable Unused Components (Core/LPSC) and Reduce Clock Frequency for Power Consumption
- Example: Front Camera Demo Active Power Optimization
- Comparison: Vision Apps Power Measurement Results With Non Optimized (Normal Build) and Active Power Optimization (ECU Build)
Best Practices for ECU Build
References

The ECU Build process allows you to tailor the system configuration to your demo's requirements. For example, in a front camera demo, only the cores and peripherals needed for camera capture, processing, and display are enabled. All other cores (e.g., unused DSPs, GPU) and LPSC (Local Power Sleep Controllers) domains are disabled in system booting configuration (syscfg in SBL), and clock frequencies are adjusted to optimal levels for the active components. This selective enabling/disabling is typically managed through configuration files and build flags, as shown in the steps above. By carefully analyzing the demo's requirements, you can identify which components can be safely turned off or downclocked, leading to significant power savings.

Step 1: Identify Required Components for the Demo
- Analyze the application code and also run the application to monitor which cores and peripherals are used by print the perf stats.
# Run the front camera demo application
# press "p" and enter to print the performance stats
# check the output below
GRAPH: app_front_cam_graph (#nodes = 13, #executions = 6415)
NODE: CAPTURE1: capture_node: avg = 76 usecs, min/max = 39 / 34547 usecs, #executions = 6415
NODE: VPAC_VISS1: viss_node: avg = 14574 usecs, min/max = 14473 / 15093 usecs, #executions = 6415
NODE: MCU2-0: aewb_node: avg = 412 usecs, min/max = 47 / 8623 usecs, #executions = 6415
NODE: VPAC_LDC1: ldc_node: avg = 5864 usecs, min/max = 5500 / 14218 usecs, #executions = 6415
NODE: VPAC_MSC1: scaler_node: avg = 5505 usecs, min/max = 5451 / 5592 usecs, #executions = 6415
NODE: MPU-0: sg_pre_proc_node: avg = 2951 usecs, min/max = 2560 / 6255 usecs, #executions = 6415
NODE: DSP_C7-1: tidl_node: avg = 55091 usecs, min/max = 26971 / 55929 usecs, #executions = 6415
NODE: MPU-0: sg_post_proc_node: avg = 3152 usecs, min/max = 2939 / 3632 usecs, #executions = 6415
NODE: MPU-0: od_pre_proc_node: avg = 1663 usecs, min/max = 1551 / 1965 usecs, #executions = 6416
NODE: DSP_C7-1: tidl_node: avg = 27042 usecs, min/max = 9826 / 27529 usecs, #executions = 6416
NODE: MPU-0: od_post_proc_node: avg = 659 usecs, min/max = 605 / 893 usecs, #executions = 6416
NODE: VPAC_MSC1: mosaic_node: avg = 2238 usecs, min/max = 2190 / 10116 usecs, #executions = 6416
NODE: DISPLAY1: DisplayNode: avg = 7394 usecs, min/max = 58 / 16839 usecs, #executions = 6416
- Analyze clock frequencies using and LPSC status using the JTAG Power Analysis Tool.
  here is the sample outout of the tool when front camera demo is running.
  ┌────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐
  │ PLL Configuration Table │
  ├────────────┬────────────┬────────────────────────┬──────────────────┬───────────────┬───────────────┬──────────┬────────────┬──────────────────┤
  │ Name │ PLL Status │ Config │ PostDiv │ VCO Freq(MHz) │ Num of HSDIVs │ HSDIV │ Status │ Output Freq(MHz) │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ MAIN_0 │ ENABLED │ M=80, FracM=0 │ ENABLED, M2=2 │ 2000 │ 10 │ HSDIV0 │ ENABLED │ 500 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV1 │ ENABLED │ 200 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV2 │ ENABLED │ 200 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV3 │ ENABLED │ 133.333333 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV4 │ ENABLED │ 80 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV5 │ ENABLED │ 200 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV6 │ ENABLED │ 200 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV7 │ ENABLED │ 200 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV8 │ ENABLED │ 50 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV9 │ ENABLED │ 100 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ MAIN_1 │ ENABLED │ M=76, FracM=13421773 │ ENABLED, M2=2 │ 1920 │ 7 │ HSDIV0 │ ENABLED │ 192 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV1 │ ENABLED │ 160 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV2 │ ENABLED │ 192 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV3 │ ENABLED │ 192 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV4 │ ENABLED │ 320 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV5 │ ENABLED │ 160 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV6 │ ENABLED │ 96 │
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  ...
  ...
  ...
  ├────────────┼────────────┼────────────────────────┼──────────────────┼───────────────┼───────────────┼──────────┼────────────┼──────────────────┤
  │ │ │ │ │ │ │ HSDIV6 │ ENABLED │ 400 │
  └────────────┴────────────┴────────────────────────┴──────────────────┴───────────────┴───────────────┴──────────┴────────────┴──────────────────┘
  ┌──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐
  │ PSC Configuration Table │
  ├──────────────┬──────────────────┬────────────┬────────────────────────┬─────────────┬────────────────────────────────────┤
  │ PSC Name │ PD Name │ PD Status │ LPSC Name │ LPSC Status │ Controlled IP Instances │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ WKUP_PSC0 │ GP_core_CTL_MCU │ ENABLED │ LPSC_mcu_alwayson │ ENABLED │ MCU_CTRL_MMR0 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ │ │ MCU_DCC0 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ │ │ MCU_DCC1 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ │ │ MCU_GPIO0 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ │ │ MCU_MCU_SEC_MMR0 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ │ │ MCU_PADCFG_CTRL0 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ │ │ WKUP_ESM0 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ │ │ WKUP_MCU_GPIOMUX_INTROUTER0 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ │ │ WKUP_PLL0 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ LPSC_main2mcu_ISO │ ENABLED │ │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ LPSC_DM2MCU_ISO │ ENABLED │ │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ LPSC_DM2safe_ISO │ ENABLED │ │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ LPSC_mcu2DM_ISO │ ENABLED │ │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ LPSC_mcu_test │ DISABLED │ │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ PD_MCUSS │ ENABLED │ LPSC_mcu_r5 │ DISABLED │ MCU_R5FSS0_CORE0 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  │ │ │ │ │ │ MCU_RTI0 │
  ├──────────────┼──────────────────┼────────────┼────────────────────────┼─────────────┼────────────────────────────────────┤
  ...
  ...
  ...
  └──────────────┴──────────────────┴────────────┴────────────────────────┴─────────────┴────────────────────────────────────┘
  ┌─────────────────────────────────────────────────────────────────────────────────┐
  │ Frequency of Selected IPs │
  ├──────────────────────────────┬────────────┬────────────────────────┬────────────┤
  │ IP Name │ Freq(MHz) │ LPSC │ Status │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN SMS 0 │ 400 │ LPSC_main_alwayson │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ Domain Manager(WKUP) R5FSS 0 │ 800 │ LPSC_main_dm │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN R5FSS 1 │ 800 │ LPSC_main_mcuss0_core0 │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MCU R5FSS 0 │ 800 │ LPSC_mcu_r5 │ DISABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN A53SS 0 │ 1000 │ LPSC_main_mpu_clst0_co │ ENABLED │
  │ │ │ re0 │ │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN C71SS 0 │ 912.5 │ LPSC_main_c7dsp0_core │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN C71SS 1 │ 912.5 │ LPSC_main_c7dsp1_commo │ DISABLED │
  │ │ │ n │ │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN VPAC 0 │ 600 │ LPSC_main_vpac │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN DMPAC 0 │ 428.571428 │ LPSC_pdrsvd0_rsvd0 │ DISABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN GPU 0 │ 720 │ LPSC_main_gpu_ctrl │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN Video Encoder/Decoder 0 │ 500 │ LPSC_main_codec │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN JPEG Encoder 0 │ 250 │ LPSC_main_jpeg │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ LPDDR4 EMIF 0 │ 933.25 │ LPSC_main_emif_local │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MCU SS /WKUP Module CLK (MCU │ 400 │ LPSC_mcu_alwayson │ ENABLED │
  │ SYSCLK) │ │ │ │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ MAIN Module CLK (SYSCLK) │ 500 │ LPSC_main_alwayson │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ Device Manager Domain CLK │ 400 │ LPSC_mcu_alwayson │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ HSM Domain CLK │ 500 │ LPSC_main_hsm │ ENABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ CSI TX ESC CLK │ 16 │ LPSC_main_csi_tx0 │ DISABLED │
  ├──────────────────────────────┼────────────┼────────────────────────┼────────────┤
  │ CSI TX MAIN CLK │ 500 │ LPSC_main_csi_tx0 │ DISABLED │
  └──────────────────────────────┴────────────┴────────────────────────┴────────────┘
  =====================================================================================================================================================
  CLOCK TREE
  =====================================================================================================================================================
  Device IP: J722S_DEV_DBGSUSPENDROUTER0
  Number of clocks: 1
  ▶ GLUELOGIC_HFOSC0_CLKOUT (25 MHz) --> PLLFRACF2_SSMOD_16FFT_MAIN_0_FOUTVCOP_CLK (2000 MHz) --> HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK (500 MHz) --> SAM62_PLL_CTRL_WRAP_MAIN_0_SYSCLKOUT_CLK (500 MHz) --> SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK (500 MHz) --> INTR_CLK (125 MHz)
  ─────────────────────────────────────────────────────────────────────────────────────────
  Device IP: J722S_DEV_MAIN_GPIOMUX_INTROUTER0
  Number of clocks: 1
  ▶ GLUELOGIC_HFOSC0_CLKOUT (25 MHz) --> PLLFRACF2_SSMOD_16FFT_MAIN_0_FOUTVCOP_CLK (2000 MHz) --> HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK (500 MHz) --> SAM62_PLL_CTRL_WRAP_MAIN_0_SYSCLKOUT_CLK (500 MHz) --> SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK (500 MHz) --> GPIOMUX_INTROUTER0_INTR_CLK (125 MHz)
  ─────────────────────────────────────────────────────────────────────────────────────────
  ...
  ...
  ...
  ...
- Enabled Components: For the front camera demo, the following components are essential:
  - A53 cores
  - Main R5F core
  - Wakeup R5F core
  - Single C7x DSP core
  - VPAC core
  - Video Encoder core
  - CISRX peripheral for camera input
  - DSS peripheral for display output
Step 2: Disable Unused Components
Modify the syscfg settings for sbl and auto run script for QNX to disable unused cores and LPSC domains.
- In the syscfg GUI:
  cd sdk_builder/
  make sbl_syscfg_gui
  
  - Navigate to the "DM Power Config" section.
  - Use PET Config to disable unused core and update the clock settings. (Disable the second C7x DSP core, GPU core, DMPAC core and downclock A73 cores from 2000MHz to 1000MHz).
  - Use PSC Config to disable the LPSC domains for unused peripherals (e.g., GPIO, I2C, UART if not needed).
  - Save the configuration and rebuild the SBL.
- In Auto Run Script for QNX File:
  Auto run script is used to run startup commands and start the application automatically on QNX boot. You need to edit this script to disable unused devices using k3conf disable command for further power optimization. Example path to auto run script : vision_apps/apps/basic_demos/app_linux_fs_files/vision_apps_all/auto_run_app_tidl_front_cam.sh
  cd /ti_fs/vision_apps
  PROCESSOR=`uname -a`
  if [[ ${PROCESSOR} == *_"J722S"_* ]]; then
  k3conf write 0x000f4114 0x50007
  gpio -m0 -n68 -o -h
  fi
  if [[ ${PROCESSOR} == *_"J721S2"_* ]]; then
  # Disable unused devices for ECU_BUILD
  k3conf disable device 128 # GPU
  k3conf disable device 130 # GPU
  k3conf disable device 373 # GPU
  k3conf disable device 360 # USB0
  k3conf disable device 28 # CPSW1
  k3conf disable device 170 # PBIST3
  k3conf disable device 171 # PBIST0
  k3conf disable device 172 # PBIST1
  k3conf disable device 173 # PBIST4
  k3conf disable device 178 # MCU_PBIST2
  k3conf disable device 177 # MCU_PBIST1
  k3conf disable device 176 # MCU_PBIST0
  k3conf disable device 2 # ATL0
  k3conf disable device 117 # GPMC0
  k3conf disable device 95 # ELM0
  k3conf disable device 98 # MMCSD0
  k3conf disable device 276 # PCIE1
  k3conf disable device 214 # I2C0
  k3conf disable device 224 # NAVSS0
  fi
  . ./vision_apps_init.sh
  sleep 8
  ( sleep 3; echo "e11" ) | ./run_app_tidl_front_cam.sh
  - Edit the script as needed to disable unused devices using k3conf disable command and device IDs.
  - Save the script and use following command to copy the updated QNX filesystem to the SD card.
    cd sdk_builder/
    make qnx_fs_install_sd
- Disabled Components: For the front camera demo, the following components are disabled:
  - Second C7x DSP cores (not used in this demo)
  - GPU core (not required for this demo)
  - DMPAC core (not used)
  - Other Unused LPSC domains (e.g., for MCU_I3C, MCSPI, MCAN, ADC, MCU_HYPERBUS, OSPI_1, ECAP, EPWM, EQEP, MMCSD_0, USB0, DSS, AUDIO, PBIST, ATL GPMC, ELM0 , PCIE1, NAVSS etc. not needed)
for more details on using syscfg tool refer DM Power Configuration Tool User Guide.
Step 3: Disable IPC for disabled core

If any core is disabled, ensure that IPC mechanisms related to that core are also disabled in the demo application code to prevent unnecessary initialization or communication attempts.  
In the front camera demo application code, ensure IPC for the disabled C7x_2 core is not initialized. ECU_BUILD flag is used in the demo code to conditionally compile IPC init code.

// sdk_builder/vision_apps_build_flags.mak
ifeq ($(SOC),j721s2)
BUILD_CPU_MPU1?=yes
BUILD_CPU_MCU1_0?=no
BUILD_CPU_MCU2_0?=yes
BUILD_CPU_MCU2_1?=yes
BUILD_CPU_MCU3_0?=no
BUILD_CPU_MCU3_1?=no
BUILD_CPU_C7x_1?=yes
ifeq ($(ECU_BUILD), $(filter $(ECU_BUILD), fc)) # disable C7x-2 for FC ECU build
    BUILD_CPU_C7x_2?=no
else
    BUILD_CPU_C7x_2?=yes
endif
// vision_apps/platform/j721s2/rtos/common/app_cfg_mcu2_1.h
#if ((defined(ECU_SRV) || defined(ECU_FC)))                     // Disabling DMPAC for SRV and FC demos
    #undef ENABLE_VHWA_DMPAC
#elif (defined(ECU_AVP4))                                       // Enabling DMPAC for AVP4 demo
    #define ENABLE_VHWA_DMPAC
#else                                                           // Enabling DMPAC for all non ECU demos
    #define ENABLE_VHWA_DMPAC
#endif
// vision_apps/platform/j721s2/rtos/common/app_cfg.h
#if (defined(ECU_FC))                                         // Enabling C7x_1 IPC only for FC Demo
    #define ENABLE_IPC_C7x_1
#else                                                         // Enabling all C7x IPCs for SRV, AVP4 or non ECU demos
    #define ENABLE_IPC_C7x_1
    #define ENABLE_IPC_C7x_2
#endif

- Step 4: Customize Automatic Demo Startup Scripts (if needed) The ECU Build process includes scripts that automatically start the demo on boot. If you need to customize these scripts (e.g., to change demo parameters or logging options), you can modify the relevant startup scripts located in the QNX filesystem before copying it to the SD card.

# Example path to startup script

vision_apps/apps/basic_demos/app_linux_fs_files/vision_apps_all/auto_run_app_tidl_front_cam.sh

Edit the script as needed to adjust demo startup behavior.

Demo / Application	Base Power Consumption (W)	After ECU Build (W)	Components Disabled / Changes Made
Front Camera Demo	3.82W /25C	3.29W /25C in SBL MMCSD 3.28W /25C in SBL OSPI	- A73 cores downclocked from 2000MHz to 1000MHz - C7x cores downclocked from 1000MHz to 900MHz - Second C7x DSP core disabled - GPU core disabled - DMPAC is disabled - Other unused LPSC domains disabled (e.g., for MCU_I3C, MCSPI, MCAN, ADC, MCU_HYPERBUS, OSPI_1, ECAP, EPWM, EQEP, MMCSD_0, USB0, DSS, AUDIO, PBIST, ATL GPMC, ELM0 , PCIE1, NAVSS etc.)
Srround View Demo	3.41W /25C	3.00W /25C in SBL MMCSD 2.97W /25C in SBL OSPI	- A73 cores downclocked from 2000MHz to 1000MHz - C7x cores downclocked from 1000MHz to 900MHz - DMPAC core disabled - CODEC is disabled - Other unused LPSC domains disabled (e.g., for MCU_I3C, MCSPI, MCAN, ADC, MCU_HYPERBUS, OSPI_1, ECAP, EPWM, EQEP, MMCSD_0, USB0, DSS, AUDIO, PBIST, ATL GPMC, ELM0, PCIE1, NAVSS etc.)
Auto Valet Parking 4	4.63W /25C	4.11W /25C in SBL MMCSD 4.00W /25C in SBL OSPI	- A73 cores downclocked from 2000MHz to 1000MHz - C7x cores downclocked from 1000MHz to 900MHz - DMPAC core disabled - Other unused LPSC domains disabled (e.g., for MCU_I3C, MCSPI, MCAN, ADC, MCU_HYPERBUS, OSPI_1, ECAP, EPWM, EQEP, MMCSD_0, USB0, DSS, AUDIO, PBIST, ATL GPMC, ELM0, PCIE1, NAVSS etc.)

Actual values may vary based on configuration and demo workload. See 153_power_measurement.md "Power Measurement Using XDS110 Debug Probe" for detailed measurement procedure.

Always review which cores and peripherals are required for your demo/use-case.
Use the syscfg tool to further optimize clock and device settings.
Validate power savings by measuring with XDS110 before and after applying ECU Build.

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