1. J721S2 Datasheet

1.1. Introduction

This section provides the performance numbers of device drivers supported in PDK

1.1.1. Setup Details

SOC Details

Values

Core

R5F

Core Operating Speed

1GHz

DDR Speed

4266 MTs

Cache status

Enabled

Optimization Details

Values

Profile

Release

Compile Options for R5F

-g -ms -DMAKEFILE_BUILD -c -qq -pdsw225 –endian=little -mv7R5 –abi=eabi -eo.oer5f -ea.ser5f –symdebug:dwarf –embed_inline_assembly –float_support=vfpv3d16 –emit_warnings_as_errors

Linker Options for R5F

–emit_warnings_as_errors -w -q -u _c_int00 -c -mv7R5 –diag_suppress=10063 -x –zero_init=on

Code Placement

DDR

Data Placement

DDR

1.1.2. Software Performance Numbers

1.1.2.1. DSS

Display Type

Configuration

FPS

CPU Load

DP

1080P60 BGRA32

60

1.0% (MCU2_0)

1.1.2.2. CSI-RX

Instance

Configuration

Time taken to receive one frame

ISR latency

CSI2Rx Inst 0

1CH 1080P30 IMX390 Sensor Raw12

33.3ms (MCU2_0)

6us (MCU2_0)

1.1.2.3. CSI-Tx

Instance

Configuration

Time taken to Transmit one frame

ISR latency

CSI2Tx Inst 0

1CH 1080P 2.5GBPS IMX390 Sensor Raw12

7.09ms (MCU2_0)

13us (MCU2_0)

1.1.2.4. UDMA

1.1.2.4.1. DMA Parameters

  • Ring Order ID: 0

  • Channel Order ID: 0

  • Channel DMA Priority: 1

  • Channel Bus Priority: 4

  • Channel BUS QOS: 4

  • Channel TX FIFO depth: 128

  • Channel Fetch Word Size: 16

  • Channel Burst Size: 64 bytes for normal channel, 128 bytes for HC and UHC channels

1.1.2.4.2. Test Parameters

  • Type: TR15 Block copy

  • TR: one TR per TRPD in PBR mode

  • TR Memory: Same as buffer memory (DDR, MSMC or OCMC depends on the test performed)

  • Transfer Size: 1 MB read and 1MB write

  • 1MB means 1000x1000 bytes and 1KB means 1000 bytes

Note: Throughput numbers mentioned is the combined memory throughput of both read and write operations

1.1.2.4.3. DRU Blockcopy

DRU channel performance with TR submitted through ring

Test Description

Throughput (MCU2)

CPU Load (MCU2)

Throughput (C7x_1)

CPU Load (C7x_1)

[PDK-3501] 1CH DDR 1MB to DDR 1MB

15033 MB/sec

6%

12897 MB/sec

10%

[PDK-3502] 1CH MSMC 1KB Circular to DDR 1MB

36095 MB/sec

7%

28532 MB/sec

14%

[PDK-3503] 1CH DDR 1MB to MSMC circular 1KB

25543 MB/sec

7%

20929 MB/sec

11%

[PDK-3504] 1CH MSMC 1KB to MSMC circular 1KB (1MB per TR)

55627 MB/sec

4%

39869 MB/sec

14%

[PDK-3505] Multi CH DDR 1MB to DDR 1MB

19849 MB/sec (2CH)

14%

13327 MB/sec (2CH)

19%

[PDK-3506] Multi CH MSMC 1KB to MSMC circular 1KB (1 MB per TR)

53980 MB/sec (2CH)

32%

19204 MB/sec (2CH)

21%
1.1.2.4.5. MCU NAVSS Blockcopy (Normal Channel)

MCU NAVSS normal channel performance with TR submitted through ring

Test Description

Throughput (MCU1)

CPU Load (MCU1)

[PDK-3490] 1CH DDR 1MB to DDR 1MB

533 MB/sec

1%

[PDK-3491] 1CH MSMC 1KB Circular to DDR 1MB

833 MB/sec

1%

[PDK-3492] 1CH DDR 1MB to MSMC circular 1KB

602 MB/sec

1%

[PDK-3493] 1CH MSMC 1KB to MSMC circular 1KB (1MB per TR)

833 MB/sec

1%

[PDK-3489] 1CH OCMC 1KB to OCMC circular 1KB (1MB per TR)

2492 MB/sec

2%

[PDK-3495] Multi CH DDR 1MB to DDR 1MB

1128 MB/sec (2CH)

1%

[PDK-3497] Multi CH MSMC 1KB to MSMC circular 1KB (1 MB per TR)

1709 MB/sec (2CH)

2%

[PDK-12918] 1CH MCU OCMC 1MB to DDR 1MB

1213 MB/sec

1%

[PDK-12919] 1CH DDR 1MB to MCU OCMC 1 MB

1095 MB/sec

1%

1.1.2.5. OSPI

1.1.2.5.1. OSPI Memory Non Cached Test Set-up

  • Platform: J721S2 EVM.

  • OS Type: Baremetal/FreeRTOS.

  • Core : R5F_0 at 1 GHz.

  • Software/Application Used: OSPI_Flash_TestApp/OSPI_Flash_Dma_TestApp

  • System Configuration: Cache OFF, Read/Write Buffer in DDR. DMA Enabled/Disabled, Interrupts ON.

1.1.2.5.2. OSPI Phy Tuning Time (DDR Octal Mode)

OSPI RCLK

Tuning Time

133 MHz

8.579

166 MHz

7.789

Note: PHY tuning time varies across silicon samples and PHY tuning point varies with voltage and temperature.

1.1.2.5.3. OSPI Read/Write Performance (DDR Octal Mode)
1.1.2.5.3.1. S28 (NOR)

OSPI RCLK

Mode

Write Tput (MB/s)

Write CPU Load

Read Tput (MB/s)

Read CPU Load

Read Tput Theoretical Max (MB/s)

133 MHz

DAC

NOT-SUPPORTED

NOT-SUPPORTED

7.485

51%

266

DAC DMA

NOT-SUPPORTED

NOT-SUPPORTED

264.658

1%

INDAC

0.494

100%

8.331

51%

166 MHz

DAC

NOT-SUPPORTED

NOT-SUPPORTED

8.570

51%

332

DAC DMA

NOT-SUPPORTED

NOT-SUPPORTED

329.430

1%

INDAC

0.498

100%

10.414

51%
1.1.2.5.3.2. W35N (NAND)

Mode

Frequency

Read Tput (MB/s)

Read Tput Theoretical Max (MB/s)

DAC (1-1-8)

50 MHz

3.777

33

DAC (1-8-8)

50 MHz

5.143

33

DAC DMA

166 MHz

56.214

62

Note: Theoretical Max for W35N caluculated basing on the assumption for page load time to be 42 Usec.

1.1.2.5.4. OSPI Memory Cached Test Set-up

  • Platform: J721S2 EVM.

  • OS Type: Baremetal/FreeRTOS.

  • Core : R5F_0 at 1 GHz.

  • Software/Application Used: OSPI_Flash_Cache_TestApp/OSPI_Flash_Dma_Cache_TestApp

  • System Configuration: Cache ON, Read/Write Buffer in DDR. DMA Enabled/Disabled, Interrupts ON.

1.1.2.5.5. OSPI Read/Write Performance (DDR Octal Mode)
1.1.2.5.5.1. S28 (NOR)

OSPI RCLK

Mode

Write Tput (MB/s)

Write CPU Load

Read Tput (MB/s)

Read CPU Load

Read Tput Theoretical Max (MB/s)

133 MHz

DAC

NOT-SUPPORTED

NOT-SUPPORTED

81.652

51%

266

DAC DMA

NOT-SUPPORTED

NOT-SUPPORTED

264.458

1%

INDAC

0.490

100%

8.332

51%

166 MHz

DAC

NOT-SUPPORTED

NOT-SUPPORTED

93.157

51%

332

DAC DMA

NOT-SUPPORTED

NOT-SUPPORTED

330.364

2%

INDAC

0.496

100%

10.415

51%
1.1.2.5.5.2. W35N (NAND)

Mode

Frequency

Read Tput (MB/s)

Read Tput Theoretical Max (MB/s)

DAC (1-1-8)

50 MHz

32.694

33

DAC (1-8-8)

50 MHz

32.783

33

DAC DMA

166 MHz

56.232

62

Note: Theoretical Max for W35N caluculated basing on the assumption for page load time to be 42 Usec.

1.1.2.6. MMCSD

1.1.2.6.1. Test Set-up

  • Platform: J721S2 EVM.

  • OS Type: FreeRTOS

  • Core : R5F_1 at 1 GHz.

  • Software/Application Used: MMCSD_<EMMC>_Regression_TestApp (A menu based application which outputs the benchmark numbers on UART)

  • System Configuration: Cache ON, Read/Write Buffer in DDR. ADMA enabled, Interrupts ON.

  • SD Card used: Sandisk 16GB, Class 10. FAT32 formatted with allocation size = 4K (for optimal FAT32 throughput & compatibility with various cards)

  • EMMC: EMMC on J721S2 EVM. Please refer to the EVM data sheet for details

1.1.2.6.2. SD Card Performance
1.1.2.6.2.1. DS Mode (25 Mhz, 4-bit) Theoretical Max: 12.5 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

9.283

9.596

512

10.338

10.737

1024

10.220

11.100

2048

10.999

11.292

5120

11.007

11.410
1.1.2.6.2.2. HS Mode (50 Mhz, 4-bit) Theoretical Max: 50 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

15.720

16.443

512

18.934

20.050

1024

20.490

21.355

2048

20.356

21.992

5120

21.265

22.528
1.1.2.6.2.3. SDR12 Mode (25 Mhz, 4-bit) Theoretical Max: 12.5 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

9.417

9.603

512

10.356

10.737

1024

10.779

11.101

2048

10.717

11.292

5120

11.007

11.410
1.1.2.6.2.4. SDR25 Mode (50 Mhz, 4-bit) Theoretical Max: 25 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

16.098

16.422

512

16.046

20.045

1024

20.493

21.354

2048

21.376

22.072

5120

20.998

22.529
1.1.2.6.2.5. SDR50 Mode (50 Mhz, 4-bit) Theoretical Max: 50 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

25.326

25.498

512

33.107

35.413

1024

37.806

39.699

2048

37.045

42.237

5120

35.116

43.547
1.1.2.6.2.6. DDR50 Mode (50 Mhz, 4-bit) Theoretical Max: 50 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

24.699

25.056

512

31.899

34.602

1024

30.910

38.676

2048

38.900

41.097

5120

38.904

42.703
1.1.2.6.3. EMMC Performance
1.1.2.6.3.1. DS Mode (25 Mhz, 8-bit) Theoretical Max: 25 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

15.886

18.470

512

18.021

20.083

1024

18.349

21.012

2048

20.057

21.500

5120

20.499

21.808
1.1.2.6.3.2. HS-SDR Mode (50 Mhz, 8-bit) Theoretical Max: 50 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

25.514

31.571

512

30.446

36.583

1024

35.009

39.755

2048

37.864

41.556

5120

38.217

42.695
1.1.2.6.3.3. HS-DDR Mode (50 Mhz, 8-bit) Theoretical Max: 100 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

33.982

47.209

512

44.033

59.324

1024

49.164

68.153

2048

53.514

73.649

5120

55.609

77.382
1.1.2.6.3.4. HS-200 Mode (200 Mhz, 8-bit) Theoretical Max: 200 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

34.780

67.490

512

46.325

95.268

1024

50.481

120.24

2048

53.474

138.37

5120

53.875

151.81
1.1.2.6.3.5. HS-400 Mode (200 Mhz, 8-bit) Theoretical Max: 400 MB/s

Size of transfer (KB)

RAW Write Throughput (MB/s)

RAW Read Throughput (MB/s)

256

38.897

81.978

512

44.745

126.28

1024

50.861

175.09

2048

53.729

188.86

5120

55.615

192.06

1.1.2.7. CPSW_2G

1.1.2.7.1. Test Setup
_images/enet_j721s2_cpsw2g_test_setup.png

Hardware Configuration

Value

Processing Core

Main R5F0 Core 0

Core Frequency

1 GHz

Ethernet Interface Type

RGMII at 1Gbps

Packet buffer memory

DDR

Hardware checksum offload

Yes

Scatter-gather TX

Yes

Scatter-gather RX

No

Software Configuration

Value

RTOS

FreeRTOS

RTOS application

Enet LLD lwIP example

TCP/IP stack

lwIP 2.2.0

Host PC tool version

iperf v2.0.10
1.1.2.7.2. TCP Performance

Test

Bandwidth (Mbps)

CPU Load (%)

TCP RX

416

82

TCP TX

438

100

TCP Bidirectional

RX=259 TX=192

100

Host PC commands:

iperf -c <evm_ip> -r
iperf -c <evm_ip> -d
1.1.2.7.3. UDP Performance

Test

Datagram Length = 64B

Datagram Length = 256B

Datagram Length = 512B

Datagram Length = 1470B
Bandwidth
(Mbps)
CPU
Load
(%)
Packet
Loss
(%)
Bandwidth
(Mbps)
CPU
Load
(%)
Packet
Loss
(%)
Bandwidth
(Mbps)
CPU
Load
(%)
Packet
Loss
(%)
Bandwidth
(Mbps)
CPU
Load
(%)
Packet
Loss
(%)

UDP RX

4.81

13

0.000

24.1

26

0.000

24.1

17

0.000

24.1

11

0.000

9.62

22

0.000

48.3

48

0.000

48.1

29

0.000

48.2

17

0.000

14.4

31

0.000

96.2

93

0.000

96.2

54

0.000

96.4

29

0.000

UDP RX (Max)

48.3

97

0.085

101

98

0.032

178

97

0.002

373

100

1.2

UDP TX (Max)

47.5

75

0.059

108

75

0.045

217

75

0.058

842

100

0.06

Host PC commands:

  • Test with datagram length of 64B:

    iperf -c <evm_ip> -u -l64 -b<bw> -r
where <bw> is 5M, 10M, 15M, etc

  • Test with datagram length of 256B:

    iperf -c <evm_ip> -u -l256 -b<bw> -r
where <bw> is 25M, 50M, 100M, etc

  • Test with datagram length of 512B:

    iperf -c <evm_ip> -u -l512 -b<bw> -r
where <bw> is 25M, 50M, 100M, etc

  • Test with datagram length of 1470B (max):

    iperf -c <evm_ip> -u -b<bw> -r
where <bw> is 25M, 50M, 100M, etc

1.1.2.8. SBL Boot Performance Numbers

1.1.2.8.1. Test Set-up

  • Platform: J721S2 EVM.

  • OS Type: Baremetal

  • Core : R5F_0 at 1 GHz

  • Note that app image load time could vary depending on the actual image size

1.1.2.8.2. GP EVM Performance (Legacy Boot)

Boot Modes

SBL Used

Application Used

MMCSD

sbl_mmcsd_img

sbl_boot_perf_test

eMMC Boot0

sbl_emmc_boot0_img

sbl_boot_perf_test

eMMC UDA

sbl_emmc_uda_img

sbl_boot_perf_test

OSPI NOR

sbl_ospi_img

sbl_boot_perf_test

OSPI NOR Optimized

sbl_boot_perf_cust_img

sbl_boot_perf_early_can_test

OSPI NAND

sbl_ospi_nand_img

sbl_boot_perf_test

SBL Boot Time Breakdown

MMCSD

eMMC Boot0

OSPI NAND

eMMC UDA

OSPI NOR

OSPI NOR Optimized

RBL Execution Time

566.257ms

67.164ms

16.283ms

508.289ms

9.119ms

9.109ms

SBL : SBL_SciClientInit: ReadSysfwImage

69.230ms

70.366ms

8.427ms

77.098ms

0.086ms

0.083ms

Load/Start SYSFW

2.444ms

2.338ms

2.450ms

2.511ms

5.275ms

5.209ms

Sciclient_init

3.153ms

3.152ms

3.152ms

3.152ms

3.152ms

3.152ms

Board Config

7.219ms

7.209ms

7.278ms

7.209ms

7.278ms

1.845ms

PM Config

1.088ms

1.087ms

1.084ms

1.085ms

1.103ms

0.102ms

Security Config

1.261ms

1.260ms

1.260ms

1.261ms

1.260ms

1.315ms

RM Config

0.933ms

0.933ms

0.932ms

0.931ms

0.932ms

0.369ms

SBL : Board_init (pinmux)

1.453ms

1.453ms

1.443ms

1.451ms

1.445ms

0.629ms

SBL : Board_init (PLL)

0.119ms

0.118ms

0.118ms

0.118ms

0.120ms

0.435ms

SBL: Board_init (CLOCKS)

1.538ms

1.537ms

1.585ms

1.538ms

1.581ms

1.028ms

SBL: DDR initialization

65.266ms

65.325ms

65.278ms

65.301ms

65.156ms

0.001ms

SBL: Ethernet Configuration

0.001ms

0.001ms

0.001ms

0.001ms

0.001ms

0.000ms

SBL: EEPROM copying time

6.841ms

6.841ms

6.841ms

6.841ms

6.841ms

0.000ms

SBL: HSM Core App Copying Time

3.489ms

0.219ms

8.231ms

0.218ms

0.248ms

0.318ms

SBL: Boot Media Drivers init

0.007ms

24.353ms

1.206ms

25.122ms

1.208ms

1.281ms

SBL: OSPI PHY Tuning time

0.212ms

0.001ms

5.548ms

0.161ms

8.135ms

8.176ms

SBL: Appication Image Verification

0.001ms

0.000ms

0.000ms

0.000ms

0.000ms

0.000ms

SBL: App copy to MCU SRAM & Jump to App

63.324ms

2.285ms

5.204ms

49.841ms

1.964ms

1.960ms

Misc

0.000ms

0.000ms

0.000ms

0.000ms

0.000ms

0.000ms

TOTAL time

793.836ms

255.642ms

136.321ms

752.128ms

114.904ms

35.012ms
1.1.2.8.3. HS EVM Performance (Legacy Boot)

Boot Modes

SBL Used

Application Used

MMCSD

sbl_mmcsd_img_hs

sbl_boot_perf_test

OSPI NOR

sbl_ospi_img_hs

sbl_boot_perf_test

OSPI NOR Optimized

sbl_boot_perf_cust_img_hs

sbl_boot_perf_hs_early_can_test

OSPI NAND

sbl_ospi_nand_img_hs

sbl_boot_perf_test

SBL Boot Time Breakdown

OSPI NOR Optimized

MMCSD

OSPI NOR

OSPI NAND

RBL Execution Time

14.064ms

358.687ms

14.098ms

21.297ms

SBL : SBL_SciClientInit: ReadSysfwImage

0.084ms

60.906ms

0.086ms

8.430ms

Load/Start SYSFW

7.085ms

4.128ms

6.991ms

4.308ms

Sciclient_init

3.152ms

3.152ms

3.153ms

3.152ms

Board Config

3.398ms

8.764ms

8.834ms

8.834ms

PM Config

0.102ms

1.087ms

1.087ms

1.085ms

Security Config

2.994ms

2.993ms

2.993ms

2.992ms

RM Config

1.948ms

2.511ms

2.511ms

2.511ms

SBL : Board_init (pinmux)

0.630ms

1.452ms

1.449ms

1.446ms

SBL : Board_init (PLL)

0.434ms

0.119ms

0.119ms

0.119ms

SBL: Board_init (CLOCKS)

1.030ms

1.538ms

1.570ms

1.572ms

SBL: DDR initialization

0.000ms

61.552ms

61.304ms

61.602ms

SBL: Ethernet Configuration

0.000ms

0.001ms

0.001ms

0.001ms

SBL: EEPROM copying time

0.000ms

6.841ms

6.841ms

6.841ms

SBL: HSM Core App Copying Time

2.160ms

17.813ms

0.250ms

41.082ms

SBL: Boot Media Drivers init

1.289ms

0.903ms

1.210ms

1.208ms

SBL: OSPI PHY Tuning time

7.985ms

0.224ms

8.065ms

5.469ms

SBL: Appication Image Verification

19.902ms

90.906ms

23.037ms

25.205ms

SBL: App copy to MCU SRAM & Jump to App

1.168ms

2.298ms

2.725ms

2.725ms

Misc

0.000ms

0.000ms

0.000ms

0.000ms

TOTAL time

67.425ms

625.875ms

146.324ms

199.879ms
1.1.2.8.4. GP EVM Performance (Combined Boot)

Boot Modes

SBL Used

Application Used

MMCSD

sbl_mmcsd_img_combined

sbl_combined_boot_perf_test

OSPI NOR

sbl_ospi_img_combined

sbl_combined_boot_perf_test

OSPI NOR Optimized

sbl_boot_perf_cust_img_combined

sbl_combined_boot_perf_early_can_test

SBL Boot Time Breakdown

OSPI NOR

MMCSD

OSPI NOR Optimized

ROM : init + SBL and TIFS load from OSPI

12.368ms

1083.690ms

12.361ms

Sciclient Boot Notification

7.867ms

7.195ms

7.755ms

Sciclient_init

1.213ms

0.026ms

1.131ms

SBL : Board_init (pinmux)

2.626ms

0.102ms

1.306ms

SBL : Board_init (PLL)

0.119ms

0.120ms

1.342ms

SBL: Board_init (CLOCKS)

1.555ms

1.440ms

0.246ms

SBL: DDR initialization

65.435ms

63.509ms

0.000ms

SBL: Ethernet Configuration

0.001ms

0.001ms

0.000ms

SBL: EEPROM copying time

6.841ms

6.841ms

0.000ms

SBL: HSM Core App Copying Time

0.272ms

77.688ms

0.264ms

SBL: Boot Media Drivers init

1.213ms

0.894ms

0.790ms

SBL: OSPI PHY Tuning time

8.176ms

0.221ms

8.191ms

SBL: Appication Image Verification

0.000ms

0.000ms

0.001ms

SBL: App copy to MCU SRAM & Jump to App

1.968ms

66.735ms

2.876ms

TOTAL time

108.243ms

1317.927ms

36.172ms
1.1.2.8.5. HS EVM Performance (Combined Boot)

Boot Modes

SBL Used

Application Used

MMCSD

sbl_mmcsd_img_combined_hs

sbl_combined_boot_perf_test

OSPI NOR

sbl_ospi_img_combined_hs

sbl_combined_boot_perf_test

OSPI NOR Optimized

sbl_boot_perf_cust_img_combined_hs

sbl_combined_boot_perf_hs_early_can_test

SBL Boot Time Breakdown

OSPI NOR Optimized

OSPI NOR

MMCSD

ROM : init + SBL and TIFS load from OSPI

18.442ms

18.681ms

498.308ms

Sciclient Boot Notification

8.508ms

8.327ms

8.360ms

Sciclient_init

1.165ms

1.228ms

1.236ms

SBL : Board_init (pinmux)

1.379ms

2.699ms

2.704ms

SBL : Board_init (PLL)

1.332ms

0.118ms

0.118ms

SBL: Board_init (CLOCKS)

0.242ms

1.554ms

1.533ms

SBL: DDR initialization

0.000ms

61.665ms

61.553ms

SBL: Ethernet Configuration

0.000ms

0.001ms

0.001ms

SBL: EEPROM copying time

0.000ms

6.842ms

6.841ms

SBL: HSM Core App Copying Time

2.174ms

33.225ms

18.580ms

SBL: Boot Media Drivers init

1.218ms

1.215ms

0.894ms

SBL: OSPI PHY Tuning time

7.978ms

7.976ms

0.380ms

SBL: Appication Image Verification

19.807ms

22.927ms

92.586ms

SBL: App copy to MCU SRAM & Jump to App

1.164ms

2.674ms

2.225ms

TOTAL time

63.317ms

167.719ms

693.884ms

1.1.2.9. Early CAN Response

  • CAN response is measured from MCU_PORZ_OUT to pulling the CAN-H line out of standby.

  • Below numbers are measured on J721S2 ES1.1 GP EVM.

Measured Time

Early CAN

36.9 ms

POST + Early CAN

60.0 ms

1.1.2.10. Memory Configuration Benchmarking

  • These numbers were collected from the memory_benchmarking_app demo which provides a means of measuring the performance of a realistic application where the text of the application is sitting in various memory locations and the data is sitting in On-Chip-Memory RAM (referred to as OCM, OCMC or OCMRAM).

  • The application executes 10 different configurations of the same text varying by data buffer size. Each test calls 16 separate functions 200 total times in random order.

  • More data instensive tests have more repetitive code, achieving much lower ICM rates

  • The Memcpy size is just a knob to make the synthetic benchmark application more data or instruction centric with no additional significance. (small memcpy size is more instruction centric with more ICM rate and vice versa)

1.1.2.10.1. Supported Configurations

Core

SOC

Supported Memory Configurations (MEM_CONF)

mcu1_0

j721s2

ocmc msmc ddr xip

mcu2_0

j721s2

ocmc msmc ddr xip

mcu1_0 + mcu2_0

j721s2

ocmc ddr xip
1.1.2.10.2. Test Set-up

  • Platform: J721S2 EVM.

  • OS Type: FreeRTOS

  • Core – MCU Domain R5_0 (MCU1_0) & Main Domain R5_0 (MCU2_0)

  • Software/Application Used: sbl_cust_img and [MEM_CONF]_memory_benchmarking_app_freertos appimage

  • Refer Memory Benchmarking Apps user guide to which SBL variant to use to test different [MEM_CONF]_memory_benchmarking_app_freertos

1.1.2.10.3. MCU Domain Single Core Execution

Memcpy Size

0

50

500

1000

2048

OCMC

OCMC Baseline Execution Time (us)

17056

17213

18830

20524

24237

ICM/sec

2259146

2242200

2051725

1890469

1613607

DDR

DDR execution time (us)

23594

23756

25386

27240

30973

DDR / OCMC Baseline

1.383

1.38

1.348

1.327

1.278

MSMC

MSMC execution time (us)

19705

19864

21441

23200

26911

MSMC / OCMC Baseline

1.155

1.154

1.139

1.13

1.11

XIP

XIP 133 MHz execution time (us)

91934

91900

93569

95586

99045

XIP 133 MHz / OCMC Baseline

5.39

5.339

4.969

4.657

4.087

XIP 166 MHz execution time (us)

75445

75301

77380

79104

83116

XIP 166 MHz / OCMC Baseline

4.423

4.375

4.109

3.854

3.429
1.1.2.10.4. MAIN Domain Single Core Execution

Memcpy Size

0

50

500

1000

2048

OCMC

OCMC Baseline Execution Time (us)

15149

15281

16609

18062

21143

ICM/sec

2481615

2463255

2271238

2098438

1801541

DDR

DDR execution time (us)

19133

19323

21569

23967

29033

DDR / OCMC Baseline

1.263

1.265

1.299

1.327

1.373

MSMC

MSMC execution time (us)

15545

15683

17888

20272

25344

MSMC / OCMC Baseline

1.026

1.026

1.077

1.122

1.199

XIP

XIP 133 MHz execution time (us)

92645

93062

98530

104632

117639

XIP 133 MHz / OCMC Baseline

6.116

6.09

5.932

5.793

5.564

XIP 166 MHz execution time (us)

75737

76168

81632

87715

100533

XIP 166 MHz / OCMC Baseline

4.999

4.984

4.915

4.856

4.755
1.1.2.10.5. MCU Domain Multi-Core Execution

Memcpy Size

0

50

500

1000

2048

OCMC

OCMC Baseline Execution Time (us)

17091

17246

18858

20561

24279

ICM/sec

2271487

2248579

2061724

1900734

1619547

DDR

DDR execution time (us)

23887

24034

25655

27381

31138

DDR / OCMC Baseline

1.398

1.394

1.36

1.332

1.283

XIP

XIP 133 MHz execution time (us)

91861

91637

93633

95737

99363

XIP 133 MHz / OCMC Baseline

5.375

5.314

4.965

4.656

4.093

XIP 166 MHz execution time (us)

75298

75307

77283

78950

83181

XIP 166 MHz / OCMC Baseline

4.406

4.367

4.098

3.84

3.426
1.1.2.10.6. MAIN Domain Multi-Core Execution

Memcpy Size

0

50

500

1000

2048

OCMC

OCMC Baseline Execution Time (us)

15314

15442

16797

18265

21383

ICM/sec

2470615

2453827

2260284

2083328

1790160

DDR

DDR execution time (us)

19299

19410

21673

24092

29250

DDR / OCMC Baseline

1.26

1.257

1.29

1.319

1.368

XIP

XIP 133 MHz execution time (us)

90706

90947

97061

102740

115612

XIP 133 MHz / OCMC Baseline

5.923

5.89

5.778

5.625

5.407

XIP 166 MHz execution time (us)

74085

74662

80081

86158

98805

XIP 166 MHz / OCMC Baseline

4.838

4.835

4.768

4.717

4.621
1.1.2.10.7. Additional OCMC Baseline Details - MCU Domain

Mem Cpy Size

0

50

100

200

500

750

1000

1250

1500

2048

Start Time in Usec

371277

665079

960088

1256085

1553087

1851089

2150087

2451091

2753093

3056089

Exec Time in Usec

17056

17213

17437

17659

18830

19593

20524

21371

22238

24237

Task Calls

200

200

200

200

200

200

200

200

200

200

Inst Cache Miss

38532

38595

38637

38353

38634

38452

38800

38644

38657

39109

Inst Cache Acc

3346774

3382995

3414641

3473153

3665155

3818456

3978325

4132707

4288282

4637597

Num Instr Exec

3905019

3946797

3989221

4062853

4308415

4504145

4709851

4905801

5105835

5552425

ICM/sec

2259146

2242200

2215805

2171867

2051725

1962537

1890469

1808244

1738330

1613607

INST/sec

228952802

229291640

228779090

230072654

228805894

229885418

229480169

229554115

229599559

229088789
1.1.2.10.8. Additional OCMC Baseline Details - MAIN Domain

Mem Cpy Size

0

50

100

200

500

750

1000

1250

1500

2048

Start Time in Usec

55138

346063

639067

933066

1227067

1523067

1820068

2119070

2418072

2718072

Exec Time in Usec

15149

15281

15450

15653

16609

17283

18062

18764

19488

21143

Task Calls

200

200

200

200

200

200

200

200

200

200

Inst Cache Miss

37594

37641

37712

37399

37723

37531

37902

37584

37596

38090

Inst Cache Acc

3131472

3166569

3198798

3257469

3449580

3601767

3763283

3917109

4072127

4420764

Num Instr Exec

3905814

3947634

3989938

4063972

4309366

4505136

4710716

4906566

5106732

5552582

ICM/sec

2481615

2463255

2440906

2389254

2271238

2171555

2098438

2002984

1929187

1801541

INST/sec

257826523

258336103

258248414

259628952

259459690

260668633

260808105

261488275

262044950

262620347