35 #ifndef SDL_AEP_SOC_MTOG_H_ 36 #define SDL_AEP_SOC_MTOG_H_ 39 #include <tistdtypes.h> 62 #define SDL_INSTANCE_MAIN_MTOG0 0U 64 #define SDL_INSTANCE_MAIN_MTOG1 1U 66 #define SDL_INSTANCE_MAIN_MTOG4 2U 68 #define SDL_INSTANCE_MAIN_MTOG5 3U 70 #define SDL_INSTANCE_MAIN_MTOG14 4U 72 #define SDL_INSTANCE_MAIN_MTOG24 5U 74 #define SDL_INSTANCE_MAIN_MTOG25 6U 76 #define SDL_INSTANCE_MAIN_MTOG32 7U 78 #define SDL_INSTANCE_MAIN_MTOG33 8U 80 #define SDL_INSTANCE_MAIN_MTOG34 9U 82 #define SDL_INSTANCE_MAIN_MTOG35 10U 84 #define SDL_INSTANCE_MAIN_MTOG36 11U 86 #define SDL_INSTANCE_MAIN_MTOG37 12U 88 #define SDL_INSTANCE_MAIN_MTOG38 13U 90 #define SDL_INSTANCE_MAIN_MTOG39 14U 92 #define SDL_INSTANCE_MCU_MTOG0 15U 94 #define SDL_INSTANCE_MCU_MTOG16 16U 96 #define SDL_INSTANCE_MCU_MTOG17 17U 98 #define SDL_INSTANCE_MCU_MTOG18 18U 100 #define SDL_INSTANCE_MCU_MTOG19 19U 102 #define SDL_INSTANCE_MCU_MTOG20 20U 104 #define SDL_INSTANCE_MCU_MTOG21 21U 106 #define SDL_INSTANCE_MCU_MTOG22 22U 108 #define SDL_INSTANCE_MCU_MTOG23 23U 110 #define SDL_INSTANCE_MTOG_MAX SDL_INSTANCE_MCU_MTOG23 114 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG0_CTRL ),
115 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG1_CTRL ),
116 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG4_CTRL ),
117 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG5_CTRL ),
118 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG14_CTRL),
119 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG24_CTRL),
120 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG25_CTRL),
121 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG32_CTRL),
122 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG33_CTRL),
123 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG34_CTRL),
124 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG35_CTRL),
125 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG36_CTRL),
126 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG37_CTRL),
127 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG38_CTRL),
128 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG39_CTRL),
129 (SDL_MCU_CTRL_MMR0_CFG0_BASE +SDL_MCU_CTRL_MMR_CFG0_MCU_MTOG0_CTRL),
130 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG16_CTRL ),
131 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG17_CTRL),
132 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG18_CTRL),
133 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG19_CTRL),
134 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG20_CTRL),
135 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG21_CTRL),
136 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG22_CTRL),
137 (SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_MAIN_MTOG23_CTRL),
uint8_t SDL_MTOG_Inst
Definition: sdl_soc_mtog.h:59
This file contains SOC specific defintions.
#define SDL_INSTANCE_MTOG_MAX
Definition: sdl_soc_mtog.h:110
static uint32_t SDL_MTOG_baseAddress[SDL_INSTANCE_MTOG_MAX+1U]
Definition: sdl_soc_mtog.h:112