2.4. Release Notes - 08_00_04

2.4.1. Introduction

This release notes provides important information that will assist you in using the PDK software package for the J721S2 family of devices.
This document provides the product information and known issues that are specific to the PDK software package.

2.4.2. What’s New

  • This is the early adopter release for J721S2.
    This package contains drivers required for J721S2 platform only.

  • PDK modules validated on J721S2 EVM:

Module A72 R5F C7x
FreeRTOS/OSAL NA YES YES
SCICLIENT YES YES YES
UART YES YES YES
UDMA YES YES YES
IPC YES YES YES
OSPI NO YES NA
MCSPI NA YES NA
MMCSD YES YES NA
VHWA NA YES NA
CSIRX NA YES NA
CSITX NA YES NA
GPIO YES YES NA
DSS NA YES NA
CRC(CSL) YES NA NA
VTM(CSL) NA YES NA
SPINLCOK(CSL) YES YES NA
ESM(CSL) NA YES NA
DMTIMER(CSL) NA YES NA
DCC(CSL) NA YES NA
UART(CSL) YES YES NA
MCAN(CSL) NA YES NA
VIM(CSL) NA YES NA
ECC(CSL) NA YES NA
  • SBL Boot Modes:
    • UART, MMC, OSPI
    • Internal Memory, DDR
    • DMA mode, non-DMA mode
  • Board Diagnostic
    • DDR
    • Board ID EEPROM
    • Boot EEPROM
    • UART
    • SD card
    • eMMC
    • OSPI NOR Flash
    • QSPI Flash
    • Current Monitor
    • Temperature sensor
    • On board RTC
    • User LED
    • Automation Header
  • Uniflash
    • OSPI NOR Flash
    • OSPI NAND Flash

2.4.3. Upgrade and Compatibility

2.4.3.1. FreeRTOS

  • By default all the tasks will be created with floating point context enabled; i.e, save/restore of FPU Registers will be performed during each task switch.
  • Until last release, this was not enabled and any task that required floating point hardware had to call portTASK_USES_FLOATING_POINT.

For more details, refer Task FPU context

2.4.3.2. Display Port

  • HPD pin cannot be used to detect DP on J721S2 EVM due to HW limitations (HPD is not connected correctly)
  • Added a new IOCTL in display driver to detect the DP connection :IOCTL_DSS_DCTRL_IS_DP_CONNECTED. Application should call this IOCTL to detect if DP is connected instead of relying on isHpdConnected parameter.

2.4.4. Device Support

  • J721S2 EVM (BOARD=j721s2_evm)

2.4.5. CCS Setup

2.4.6. Validation Information

This release is validated on J721S2 EVM for the applicable components.

Refer :FAQ - Supported Cores by example applications for list of validated application

2.4.7. Tool Chain Information

Component Version
FreeRTOS Kernel 10.4.3
lwIP stack 2.1.2
lwIP-contrib 2.1.0
TI ARM CLANG 1.3.0.LTS
TI C7x code generation tools 2.1.1.LTS
GCC ARM code generation tools ARCH64 9.2-2019.12

2.4.8. Change Request

ID Head Line Original Fix Version New Fix Version
PDK-9558 PDK: Support for CSI-Tx updates 08.02.00 08.04.00
PDK-8684 VHWA: Flex-connect with DDR->L3->LDC->DDR path 08.02.00 09.00.00
PDK-8685 VHWA: Flex-connect with DDR->VISS->L3->LDC->DDR path 08.02.00 09.00.00
PDK-8690 VHWA: Flex-connect with DDR->VISS->L3->DDR (compression) path 08.02.00 09.00.00
PDK-8688 VHWA: Flex-connect with DDR->VISS->MSC->L3->LDC->DDR path 08.02.00 09.00.00

2.4.9. Fixed Issues

ID Head Line Module Affected Versions Affected Platforms
PDK-10819 Must have some way to identify DM firmware and rm_pm_hal version SCICLIENT 08.00.03 J721S2
PDK-10849 Sciclient_rmIrqSet is not programming Interrupt Aggregator Unmapped Event Mapping Register (udmass_inta0__cfg__unmap) for BCDMA events SCICLIENT 08.00.03 J721S2
PDK-10850 Scicleint_rmRingCfg API is not programming BCDMA Ring Cfg Register (bcdma0__cfg__ring) SCICLIENT 08.00.03 J721S2
PDK-10827 McSPI DMA UT is not functional McSPI 08.00.03 J721S2
PDK-11006 UDMA OSPI example failing in OspiFlash_ospiConfigPHY api OSPI, UDMA 08.00.03 J721S2
PDK-11013 Unable to perform Udma_Init() after Udma_deinit() is performed UDMA 08.00.03 J721S2
PDK-11057 FreeRTOS UT results in exception on R5F cores except mcu1_0 FreeRTOS 08.00.03 J721S2
PDK-11126 Sciclient: Disable ENABLE_MSG_FWD for all MAIN R5s SCICLIENT 08.00.03 J721S2
PDK-11159 DSS init fails when display is not connected to EVM DSS 08.00.03 J721S2
PDK-11168 dss_display_testapp_freertos fails when run with BGR24 DSS 08.00.03 J721S2
PDK-11210 CSI-Tx sample application hangs at D-PHY lane speeds greater than or equal to 800Mbps. CSI2TX 08.00.03 J721S2
PDK-11239 Diagnostic test failure on mcu1_0 core DIAG 08.00.03 J721S2

2.4.10. Known Issues

Key Summary Module Reported in Release Affected Platforms Workaround in this release
PDK-8601 csl ecc testapp fails on J721S2 CSL 08.00.03 J721S2 None
PDK-10535 CSL: Inconsistent naming of some macros in cslr_soc_baseaddress.h CSL 08.00.03 J721S2 None
PDK-10546 CSL: Inconsistent naming of some macros in cslr_intr_compute_cluster0_gic500ss_0.h CSL 08.00.03 J721S2 None
PDK-10829 Sciclient UT in Interrupt mode is hanging on C7x cores SCICLIENT 08.00.03 J721S2 Use polling mode
PDK-10847 UART DMA UT is hanging on mcu1_0/mcu1_1 UART 08.00.03 J721S2 Use Non-DMA mode
PDK-10973 MCU R5 VIM Test failing on mcu1_0/mcu1_1 CSL 08.00.03 J721S2 None
PDK-11085 SPI instance should be decided by SPI driver and not Board Module OSPI 08.00.03 J721S2 None
PDK-11093 ACK/NACK is send for TISCI messages without AOP flag SCICLIENT 08.00.03 J721S2 None
PDK-11133 UDMA DRU Direct TR Example Fails UDMA 08.00.03 J721S2 Use DRU In-Drirect TR mode
PDK-11227 UART instances 3-9 does not work on MAIN R5 in interrupt mode UART 08.00.03 J721S2 None

2.4.11. Limitations

  • Display Port:
    • HPD pin cannot be used to detect DP on J721S2 EVM due to HW limitations (HPD is not connected correctly), thereby rendering isHpdConnected parameter unreliable.
  • VHWA:
    • VISS-> MSC Flexconnect is not yet up.