TIOVX User Guide
TIOVX Supported Kernels

Table of Contents

Legend

Meaning of terms in the following tables,

  • DMA: Kernel implemented and memory access done using DMA (NOTE: Not enabled in this release)
  • Cache: Kernel implemented and memory access done using CPU Cache
  • [empty]: Kernel is not supported on target

OpenVX Standard Kernels

This table lists the mapping of standard OpenVX kernels to compute targets on the Jacinto7 platform. When mapped to C7X DSP, it indicates if it is implemented using BAM DMA acceleration, or cache only.

All of the below kernels default to running on the standalone C7X DSP. If a different target is needed, it can be selected from the available targets indicated below by using the vxSetNodeTarget() API.

Note: all of the standard kernels were initially developed on J721E running on the C66x DSP. When porting to the C7x, the VXLIB kernels and TIOVX kernel wrappers were recompiled for the C7x. If custom kernels need to be recompiled from C66x to C7x, these kernels in VXLIB and associated kernel wrappers in TIOVX can be referenced for information on how to recompile these kernels.

Kernel C7X HWA PC Em
Absolute Difference Cache Yes
Accumulate Cache Yes
Accumulate Squared Cache Yes
Accumulate Weighted Cache Yes
Arithmetic Addition Cache Yes
Arithmetic Subtraction Cache Yes
Bitwise AND Cache Yes
Bitwise EXCLUSIVE OR Cache Yes
Bitwise INCLUSIVE OR Cache Yes
Bitwise NOT Cache Yes
Box Filter Cache Yes
Canny Edge Detector Cache Yes
Channel Combine Cache Yes
Channel Extract Cache Yes
Color Convert Cache Yes
Convert Bit depth Cache Yes
Custom Convolution Cache Yes
Dilate Image Cache Yes
Equalize Histogram Cache Yes
Erode Image Cache Yes
Fast Corners Cache Yes
Gaussian Filter Cache Yes
Non Linear Filter Cache Yes
Harris Corners Cache Yes
Histogram Cache Yes
Gaussian Image Pyramid Cache VPAC_MSC* Yes
Laplacian Image Pyramid Cache Yes
Reconstruction from a Laplacian Image Pyramid Cache Yes
Integral Image Cache Yes
Magnitude Cache Yes
Mean and Standard Deviation Cache Yes
Median Filter Cache Yes
Min, Max Location Cache Yes
Optical Flow Pyramid (LK) Cache Yes
Phase Cache Yes
Pixel-wise Multiplication Cache Yes
Remap Cache Yes
Scale Image Cache VPAC_MSC* Yes
Sobel 3x3 Cache Yes
TableLookup Cache Yes
Thresholding Cache Yes
Warp Affine Cache Yes
Warp Perspective Cache Yes
  • Subset of configuration options and or accuracy tradeoff to speed is to be considered for this HWA implementation.

TI Extension Kernels

Kernel Target PC Emulation Support
tivxCaptureNode CSIRX No
tivxDisplayNode DSS No
tivxTIDLNode C7x + MMA Yes
tivxVpacVissNode VPAC_VISS Yes
tivxVpacLdcNode VPAC_LDC Yes
tivxVpacNfGenericNode VPAC_NF Yes
tivxVpacNfBilateralNode VPAC_NF Yes
tivxVpacMscScaleNode VPAC_MSC Yes
tivxVpacMscPyramidNode VPAC_MSC Yes
tivxDmpacSdeNode DMPAC_SDE Yes
tivxDmpacDofNode DMPAC_DOF Yes
tivxCsitxNode CSITX No
tivxDisplayM2MNode DSS No