2.1. Release Notes - 08_05_00¶
2.1.1. Introduction¶
This release notes provides important information that will assist you in using the PDK software package for the Jacinto family of devices. This document provides the product information and known issues that are specific to the PDK software package.
New features added / supported is listed below and defects fixed are highlighted in Fixed Issues. Also please check Upgrade and Compatibility for backward compatibility
2.1.2. What’s New¶
ID | Description | Module | Supported Platforms |
---|---|---|---|
PDK-9558 | PDK: Support for CSI-Tx Loopback Mux | CSITX | J721S2 |
PDK-11876 | Support for SBL booting from eMMC | SBL | J721S2, J784S4 |
PDK-12135 | PDK shall support boot of SMS HSM M4 core | SBL | J721S2, J784S4 |
PDK-12235 | McASP Support for J7AEP | MCASP | J721S2 |
PDK-12417 | Processor SDK should validate with SafeRTOS on R5F | OSAL | J721S2 |
PDK-12418 | Processor SDK should validate with SafeRTOS on C7x | OSAL | J721S2 |
ETHFW-1912 | ENET LLD : support DMA Scatter gather TX functionality | ENET | J721S2 |
ETHFW-1953 | CPSW: lwIP: Checksum offload support | ENET | J721S2 |
ETHFW-2027 | mdio: MDIO CDC errata (i2329) workaround implementation (CPSW) | ENET | J721S2 |
2.1.3. Upgrade and Compatibility¶
2.1.3.1. CSL¶
CSL ARM R5 Cache operation APIs now accepts a third argument wait, to specify if the function should wait or not until the operation is completed.
Old New CSL_armR5CacheWb(const void * addr, int32_t size) CSL_armR5CacheWb(const void * addr, int32_t size, bool wait) CSL_armR5CacheWbInv(const void * addr, int32_t size) CSL_armR5CacheWbInv(const void * addr, int32_t size, bool wait) CSL_armR5CacheInv(const void * addr, int32_t size) CSL_armR5CacheInv(const void * addr, int32_t size, bool wait) Added new API CSL_armR5CacheWait. This can be used to wait for the previous cache wb/wbInv/inv operation to complete.
For performance optimizations, following CSL cache line operation functions will not invoke memory barrier instructions. Instead end user is supposed to handle the same after updating all the required cache lines.
- CSL_armR5CacheInvalidateDcacheMva
- CSL_armR5CacheCleanDcacheMva
2.1.3.2. OSAL¶
taskFxn paramater for TaskP_Create is updated from type ‘void*’ to function pointer of type TaskP_Fxn
i.e, TaskP_create expects a function pointer of prototype
void ( * TaskP_Fxn )( void *arg0, void *arg1 )
name param in TaskP_Params is updated from type uint8_t * to const char *
CycleprofilerP_getTimeStamp does not check for R5F PMU counter overflow and refresh the PMU counter higher bits.
- In case of FreeRTOS, OS tick timer handles this internally by periodically checking for R5F PMU counter overflow and refresh the higher bits of PMU counter in the event of any overflow.
- In SafeRTOS and Baremetal, this is not handled by default.
- A new API, CycleprofilerP_refreshCounter is added to check for R5F PMU counter overflow and refresh the higher bits of PMU counter in the event of any overflow.
- Baremetal/SafeRTOS applications can periodically invoke the new API CycleprofilerP_refreshCounter to handle R5F PMU counter overflow.
2.1.3.3. VHWA¶
None
2.1.3.4. Sciclient / TIFS¶
- SYSFW/TIFS have added new PSIL host id verification check.
Due to this RM PSIL messages from mcu1_0 should use MSG forwarding
instead of sending the message to TIFS directly.
- mcu1_0 will always be in secure mode when trying to send the message to TIFS directly, to avoid self blocking. And all the BoardCfg RM entries for mcu1_0 are for default non-secure host id. Hence for this case, the new PSIL host id verification will fail.
- By using MSG forwarding, it retains the host id information of the non-secure/secure mode of mcu1_0. Setting forwarding ensures that the mcu1_0 uses the DM2DMSC secure proxy threads. NOTE: Forwarding always leads to forced polling.
- For all other default base-port and security messages, mcu1_0 can be in secure mode and send the message to TIFS directly.
2.1.3.5. CSI¶
- App can select the source CSIRX instance to re-transmit to a specific CSITX instance using newly added lpbkCsiRxInst parameter in Csitx_InstCfg structure.
- Added a new parameter enableStrm in Csirx_CreateParams. Previously all supported streams were enabled by default, now this info should be provided by the application.
2.1.4. Device Support¶
J721S2 GP SR 1.0 (BOARD=j721s2_evm)
Associated TIFS versions:
TIFS name J721S2 SR revision tifs.bin SR1.0 GP tifs-hs-enc.bin SR1.0 HS
2.1.5. Validation Information¶
For details on the validated examples refer to the platform specific test report available here.
2.1.6. Tool Chain Information¶
Component | Version |
---|---|
FreeRTOS Kernel | 10.4.3 |
lwIP stack | 2.1.2 |
lwIP-contrib | 2.1.0 |
TI ARM CLANG | 1.3.0.LTS |
PRU code generation tools | 2.3.3 |
GCC ARM code generation tools | ARCH64 9.2-2019.12 |
CGT XML Processing Scripts | 2.61.00 |
System Analyzer (UIA Target) | 2_30_01_02 |
Component | Version |
---|---|
TI C7x code generation tools | 3.0.0.STS |
2.1.7. Change Request¶
Refer to monthly roadmap slides for changes in the planned features
2.1.8. Fixed Issues¶
ID | Head Line | Module | Affected Versions | Affected Platforms |
---|---|---|---|---|
PDK-8601 | CSL ECC test application fails on J7200/J721S2 | CSL | 07.01.00 | J7200, J721S2 |
PDK-11237 | CSI-Rx UT hangs when run on mcu2_0 | CSI2RX | 08.02.00 | J721E, J721S2 |
PDK-12015 | SBL: MCU2_0 or MCU3_0 cannot be booted in LockStep mode | SBL | 08.02.00 | J721E, J7200, J721S2, J784S4 |
PDK-12065 | [CSIRX]: RAW12 packed output format is not working | CSI2RX | 08.02.00 | J721E, J721S2, J784S4 |
PDK-12080 | taskFxn parameter is not pointer to function in TaskP_create | OSAL | 08.02.00 | J721E, J7200, J721S2, J784S4 |
PDK-12081 | UART performance issues in polling mode | UART | 08.02.00 | J721E, J7200, J721S2, J784S4 |
PDK-12082 | [OSAL]: Incorrect type for TaskP_Params.name variable | OSAL | 08.02.00 | J721E, J7200, J721S2, J784S4 |
PDK-12164 | Incorrect DDR End Address with ECC enabled | BOARD | 08.02.00 | J721E, J7200, J721S2, J784S4 |
PDK-12165 | [J7AEP Build] R5 linker file has duplicate entries for .text.hwi in OCMC RAM and DDR | COMMON | 08.04.00 | J721S2 |
PDK-12194 | Re-transmission should be enabled by default in CSL MCAN application | CSL | 08.02.00 | J721E, J7200, J721S2, J784S4 |
PDK-12205 | SBL Build is broken due to missing tool | SBL | 08.02.00 | J721S2 |
PDK-12210 | [CSIRX]: Incorrect powerup sequence | CSI2RX | 08.04.00 | J721E, J721S2, J784S4 |
PDK-12218 | [CSL-R5F] Incorrect usage of DMB and DSB for cache operations | CSL | 08.04.00 | J721E, J7200, J721S2, J784S4 |
PDK-12220 | HSM SRAM address is incorrect | CSL | 08.04.00 | J721S2 |
PDK-12234 | IPC RPMessage_recv() timeout issue | IPC | 08.04.00 | J721E, J7200, J721S2, J784S4 |
PDK-12248 | Wrong variable name in makerules_spec documentation | COMMON | 08.04.00 | J721E, J7200, J721S2, J784S4 |
PDK-12393 | Many SAFERTOS related files are missing from PDK in snapshot release | OSAL | 08.04.00 | J721S2 |
2.1.9. Known Issues¶
ID | Head Line | Module | Reported in Release | Affected Platforms | Impact | Workaround in this release |
---|---|---|---|---|---|---|
PDK-11854 | USART: Spurious DMA Interrupts | UART | 08.04.00 | J721E, J7200, J721S2 | None | None |
PDK-11973 | USART: Erroneous clear/trigger of timeout interrupt | UART | 08.02.00 | J721E, J7200, J721S2 | None | None |
PDK-12023 | Heap OSAL hangs if previous allocation has buffer overflow | OSAL | 08.02.00 | J721E, J721S2 | None | None |
PDK-12085 | [DSS] HPD Pulse event is not handled in the eDP driver | DSS | 08.02.00 | J721E, J721S2, J784S4 | None | None |
PDK-12163 | [CSIRX]: YUV422-8bit data-type capture not working | CSIRX | 08.04.00 | J721S2 | None | None |
PDK-11984 | J721S2/TDA4VE : Missing PCIE+USB3 multilink Torrent CSL in PDK | CSL | 08.04.00 | J721S2 | None | None |
PDK-12213 | IPC: stack corruption of taskWaiter used in RPMessage_getRemoteEndPt | IPC | 08.00.00 | J721E, J7200, J721S2, J784S4 | None | Make taskWaiter element as global |
PDK-12233 | SciServer: Multiple definition of Hwi Data | SCICLIENT | 08.04.00 | J721E, J7200, J721S2, J784S4 | None | None |
PDK-12241 | CSIRX: Incorrect DATA Shift value for RAW8 mode | CSI2RX | 08.04.00 | J721E, J721S2, J784S4 | None | None |
PDK-12242 | CSIRX: Incorrect Dual Pixel mode for YUV422 | CSI2RX | 08.04.00 | J721E, J721S2, J784S4 | None | None |
PDK-12243 | DSS: rxBuffer range check missing in DP_mailbox | DSS | 08.04.00 | J721E, J721S2, J784S4 | DP sink module should not send message > 1 KB size | None |
PDK-12258 | MCSPI DMA does not support 48bit address space | MCSPI | 08.04.00 | J721E, J7200, J721S2, J784S4 | MCSPI is limited to 32 bit address space | None |
PDK-12327 | FreeRTOS taskLoad is not proper | OSAL | 08.02.00 | J721E, J7200, J721S2, J784S4 | Task load calculations could be wrong | None |
PDK-12358 | Non-supported Sciclient APIs are present in header files | SCICLIENT | 08.04.00 | J721E, J7200, J721S2, J784S4 | None | None |
2.1.10. Limitations¶
2.1.10.1. PDK¶
- PDK examples do not support SMP mode. Some of examples still support build in SMP mode but these binaries are not supported or validated.
- TI Clang compiler does not enable O3 optimization level and Thumb2 mode which were enabled by default with TI ARM CGT compiler. This has an impact on driver throughput. E.g. Ethernet performance has reduced by ~20% on J721S2
- For Baremetal and SafeRTOS, in case of usage of CycleprofilerP APIs the R5F PMU counter overflow is not handled by default.
- Applications can periodically use the CycleprofilerP_refreshCounter to check overflow and refresh the higher bits of the PMU counter.
2.1.10.2. ENET¶
- Scatter-gather functionality is currently supported only for packet transmission.
2.1.10.3. SafeRTOS¶
- When snprintf is interrupted by an ISR, C7X core may crash while returning from the ISR. - As a workaround, snprintf can be protected with Hwip_disable() and HwiP_restore() to disable the interrupts.