1. J721S2 Datasheet¶
1.1. Introduction¶
This section provides the performance numbers of device drivers supported in PDK
1.1.1. Setup Details¶
| SOC Details | Values |
|---|---|
| Core | R5F |
| Core Operating Speed | 1GHz |
| DDR Speed | 4266 MTs |
| VPAC Frequency | 650 MHz |
| DMPAC Frequency | 520 MHz |
| Cache status | Enabled |
| Optimization Details | Values |
|---|---|
| Profile | Release |
| Compile Options for R5F | -g -ms -DMAKEFILE_BUILD -c -qq -pdsw225 –endian=little -mv7R5 –abi=eabi -eo.oer5f -ea.ser5f –symdebug:dwarf –embed_inline_assembly –float_support=vfpv3d16 –emit_warnings_as_errors |
| Linker Options for R5F | –emit_warnings_as_errors -w -q -u _c_int00 -c -mv7R5 –diag_suppress=10063 -x –zero_init=on |
| Code Placement | DDR |
| Data Placement | DDR |
1.1.2. Software Performance Numbers¶
1.1.2.1. VHWA¶
| VHWA Driver | Configuration | Measured Throughput (MPix/S) |
|---|---|---|
| DOF | 2MP (2048x1024), 12b Packed, 6 Levels, SR191x96 | 143.38 |
| DOF | 1MP (1312x736), 12b Packed, 5 Levels, SR170x124 | 134.37 |
| MSC | 1080P, 8b YUV420, 10 Scales output | 674.60 |
| NF | 720P, 8b YUV420, Bilateral filter | 678.21 |
| SDE | 2MP (2048x1024), 12b Packed, SR 192, LR Enabled | 77.75 |
| SDE | 720P, 12b Packed, SR 192, LR Disabled | 91.33 |
| LDC | 1080P, 8b YUV420, Single region | 700.50 |
| VISS | 1080P, Raw 12 input, 2 frame Merge, YUV420 12b and 8b output | 662.84 |
1.1.2.2. DSS¶
| Display Type | Configuration | CPU Load |
|---|---|---|
| DP | 1080P60 BGRA32 | 1.0% (MCU2_0) |
1.1.2.3. UDMA¶
1.1.2.3.1. DMA Parameters¶
- Ring Order ID: 0
- Channel Order ID: 0
- Channel DMA Priority: 1
- Channel Bus Priority: 4
- Channel BUS QOS: 4
- Channel TX FIFO depth: 128
- Channel Fetch Word Size: 16
- Channel Burst Size: 64 bytes for normal channel, 128 bytes for HC and UHC channels
1.1.2.3.2. Test Parameters¶
- Type: TR15 Block copy
- TR: one TR per TRPD in PBR mode
- TR Memory: Same as buffer memory (DDR, MSMC or OCMC depends on the test performed)
- Transfer Size: 1 MB read and 1MB write
- 1MB means 1000x1000 bytes and 1KB means 1000 bytes
Note: Throughput numbers mentioned is the combined memory throughput of both read and write operations
1.1.2.3.3. DRU Blockcopy¶
DRU channel performance with TR submitted through ring
| Test Description | Throughput (MCU2) | CPU Load (MCU2) |
|---|---|---|
| [PDK-3501] 1CH DDR 1MB to DDR 1MB | 14453 MB/sec | 100% |
| [PDK-3502] 1CH MSMC 1KB Circular to DDR 1MB | 35605 MB/sec | 100% |
| [PDK-3503] 1CH DDR 1MB to MSMC circular 1KB | 25115 MB/sec | 100% |
| [PDK-3504] 1CH MSMC 1KB to MSMC circular 1KB (1MB per TR) | 53635 MB/sec | 100% |
| [PDK-3505] Multi CH DDR 1MB to DDR 1MB | 19065 MB/sec (2CH) | 100% |
| [PDK-3506] Multi CH MSMC 1KB to MSMC circular 1KB (1 MB per TR) | 60349 MB/sec (2CH) | 100% |
1.1.2.4. CPSW¶
1.1.2.4.1. TCP (IP stack) Performance¶
1.1.2.4.1.1. Main CPSW2G - Main domain R5_0 core 0 (mcu2_0)¶
- Main domain R5_0 at 1GHz
- RGMII interface at 1Gbps
- TCP window size: 128 KByte
Single Direction Test
| Test | Measured Throughput (Mbps) | CPU Load (%) |
|---|---|---|
| TCP RX | 131.0 | 53 |
| TCP TX | 187.0 | 86 |
Bidirectional Test
| Test | Measured Throughput (Mbps) | CPU Load (%) |
|---|---|---|
| TCP RX | 105.0 | 99 |
| TCP TX | 139.0 |
1.1.2.4.1.2. CPSW2G - MCU domain R5 core 0 (mcu1_0)¶
- MCU domain R5_0 at 1GHz
- RGMII interface at 1Gbps
- TCP window size: 128 KByte
Single Direction Test
| Test | Measured Throughput (Mbps) | CPU Load (%) |
|---|---|---|
| TCP RX | 127.0 | 70 |
| TCP TX | 139.0 | 100 |
Bidirectional Test
| Test | Measured Throughput (Mbps) | CPU Load (%) |
|---|---|---|
| TCP RX | 64.1 | 100 |
| TCP TX | 87.3 |
1.1.2.4.2. UDP (IP stack) Performance¶
1.1.2.4.2.1. Main CPSW2G - Main domain R5_0 core 0 (mcu2_0)¶
- Main domain R5_0 at 1GHz
- RGMII interface at 1Gbps
Single Direction Test
| Test | Measured Throughput (Mbps) | CPU Load (%) | Drop (%) |
|---|---|---|---|
| UDP RX | 294.0 | 94 | 0.003 |
| UDP TX | 361.0 | 100 | 0.005 |
1.1.2.4.2.2. CPSW2G - MCU domain R5 core 0 (mcu1_0)¶
- MCU domain R5_0 at 1GHz
- RGMII interface at 1Gbps
Single Direction Test
| Test | Measured Throughput (Mbps) | CPU Load (%) | Drop (%) |
|---|---|---|---|
| UDP RX | 210.0 | 95 | 0.002 |
| UDP TX | 398.0 | 100 | 0.012 |
Note:
- Current performance numbers are preliminary as throughput profiling is not done in fully optimized environment.
1.1.2.5. SBL OSPI Boot Performance App¶
1.1.2.5.1. Test Set-up¶
- Platform: J721S2 EVM.
- OS Type: Baremetal
- Core : R5F_0 at 1 GHz
- Software/Application Used: sbl_cust_img (with custom flags) and sbl_boot_perf_test appimage
1.1.2.5.2. GP EVM Performance¶
| SBL Boot Time Breakdown | Time (ms) |
| MCU_PORZ_OUT to MCU_RESETSTATz | 0.63 |
| ROM : init + SBL load from OSPI | 14.00 |
| SBL : SBL_SciClientInit: ReadSysfwImage | 0.052 |
| Load/Start SYSFW | 4.185 |
| Sciclient_init | 3.153 |
| Board Config | 1.847 |
| PM Config | 0.380 |
| Security Config | 0.163 |
| RM Config | 0.423 |
| SBL: SoC Late-Init | 0.00 |
| SBL : Board_init (pinmux) | 2.477 |
| SBL : Board_init (PLL) | 1.135 |
| SBL: Board_init (CLOCKS) | 0.873 |
| SBL: OSPI init | 0.380 |
| SBL: App copy to MCU SRAM & Jump to App | 2.344 |
| Misc | 0.074 |
| MCUSW: CAN response | 1.00 |
| TOTAL time | 33.116 |