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Spi_Cfg.h
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62 
70  /*****************************************************************************
71  Project: SPI_CONFIG_J721E
72  Date : 2022-11-29 01:31:24
73  This file is generated by EB Tresos
74  Do not modify this file, otherwise the software may behave in unexpected way.
75  ******************************************************************************/
76 
84 #ifndef SPI_CFG_H_
85 #define SPI_CFG_H_
86 
87 /* ========================================================================== */
88 /* Include Files */
89 /* ========================================================================== */
90 #include "Os.h"
91 #include "Dem.h"
92 #include "Det.h"
93 #include "Spi_Cbk.h"
94 
95 #ifdef __cplusplus
96 extern "C" {
97 #endif
98 
104 #define SPI_VARIANT_POST_BUILD (STD_ON)
105 
112 #define SPI_CHANNELBUFFERS (SPI_IB_EB)
113 
115 #define SPI_IB_MAX_LENGTH (64U)
116 
118 #define SPI_DEV_ERROR_DETECT (STD_ON)
119 
121 #define SPI_JOB_LOG (STD_ON)
122 
124 #define SPI_MAX_JOB_LOG (100U)
125 
126 
127 
128 
129 
130 
131 
132 
133 
134 
135 
136 
138 #define SPI_MAX_HW_DMA_UNIT (0U)
139 
141 #define SPI_DMA_ENABLE (STD_OFF)
142 
143 /*
144  * Scalability levels
145  */
147 #define SPI_LEVEL_0 (0U)
148 
149 #define SPI_LEVEL_1 (1U)
150 
151 #define SPI_LEVEL_2 (2U)
152 
154 #define SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT (STD_OFF)
155 
157 #define SPI_SCALEABILITY (SPI_LEVEL_2)
158 
160 #define SPI_VERSION_INFO_API (STD_ON)
161 
163 #define SPI_HW_STATUS_API (STD_ON)
164 
166 #define SPI_CANCEL_API (STD_ON)
167 
168 /*
169  * All below macros are used for static memory allocation and can be changed to
170  * match the usecase requirements.
171  */
173 #define SPI_MAX_CHANNELS_PER_JOB (1U)
174 
176 #define SPI_MAX_JOBS_PER_SEQ (1U)
177 
179 #define SPI_MAX_CHANNELS (1U)
180 
182 #define SPI_MAX_JOBS (1U)
183 
185 #define SPI_MAX_SEQ (1U)
186 
191 #define SPI_MAX_HW_UNIT (8U)
192 
196 #define SPI_MAX_EXT_DEV (11U)
197 
198 /*
199  All below macros are used for enabling the ISR for a particular hardware.
200  */
201 
204 #define SPI_UNIT_MCU_MCSPI0_ACTIVE (STD_ON)
205 
208 #define SPI_UNIT_MCU_MCSPI1_ACTIVE (STD_ON)
209 
212 #define SPI_UNIT_MCU_MCSPI2_ACTIVE (STD_ON)
213 
216 #define SPI_UNIT_MCSPI0_ACTIVE (STD_ON)
217 
220 #define SPI_UNIT_MCSPI1_ACTIVE (STD_ON)
221 
224 #define SPI_UNIT_MCSPI2_ACTIVE (STD_ON)
225 
228 #define SPI_UNIT_MCSPI3_ACTIVE (STD_ON)
229 
230 
233 #define SPI_UNIT_MCSPI4_ACTIVE (STD_ON)
234 
237 #define SPI_UNIT_MCSPI5_ACTIVE (STD_OFF)
238 
241 #define SPI_UNIT_MCSPI6_ACTIVE (STD_OFF)
242 
245 #define SPI_UNIT_MCSPI7_ACTIVE (STD_OFF)
246 
247 
248 
249 
250 
251 
252 
253 
254 
255 
256 
257 
258 
260 #define SPI_ISR_TYPE (SPI_ISR_CAT1)
261 
263 #define SPI_OS_COUNTER_ID ((CounterType)OsCounter_0)
264 
270 #define SPI_TIMEOUT_DURATION (32000U)
271 
273 #define SPI_REGISTER_READBACK_API (STD_ON)
274 
276 #define SPI_SAFETY_API (STD_ON)
277 
279 #define SpiConf_SpiChannel_SpiChannel_0 (0U)
280 
282 #define SpiConf_SpiExternalDevice_CS0 (SPI_CS0)
283 
284 
286 #define SpiConf_SpiJob_SpiJob_0 (0U)
287 
289 #define SpiConf_SpiSequence_SpiSequence_0 (0U)
290 
291 
293 #define SpiConf_SpiExternalDevice_HwUnitId0 (CSIB0)
294 
295 #define SpiConf_SpiExternalDevice_HwUnitId1 (CSIB1)
296 
297 #define SpiConf_SpiExternalDevice_HwUnitId2 (CSIB2)
298 
299 #define SpiConf_SpiExternalDevice_HwUnitId3 (CSIB3)
300 
301 #define SpiConf_SpiExternalDevice_HwUnitId4 (CSIB4)
302 
303 #define SpiConf_SpiExternalDevice_HwUnitId5 (CSIB5)
304 
305 #define SpiConf_SpiExternalDevice_HwUnitId6 (CSIB6)
306 
307 #define SpiConf_SpiExternalDevice_HwUnitId7 (CSIB7)
308 
309 
316 #define DemConf_DemEventParameter_SPI_DEM_NO_EVENT (0xFFFFU)
317 #define SPI_DEM_NO_EVENT DemConf_DemEventParameter_SPI_DEM_NO_EVENT
318 
319 #ifndef SPI_E_HARDWARE_ERROR
320 
321 #define SPI_E_HARDWARE_ERROR (DemConf_DemEventParameter_SPI_E_HARDWARE_ERROR)
322 #endif
323 
328 #define SPI_UNIT_MCU_MCSPI0 ((Spi_HWUnitType) CSIB0)
329 
330 #define SPI_UNIT_MCU_MCSPI1 ((Spi_HWUnitType) CSIB1)
331 
332 #define SPI_UNIT_MCU_MCSPI2 ((Spi_HWUnitType) CSIB2)
333 
334 #define SPI_UNIT_MCSPI0 ((Spi_HWUnitType) CSIB3)
335 
336 #define SPI_UNIT_MCSPI1 ((Spi_HWUnitType) CSIB4)
337 
338 #define SPI_UNIT_MCSPI2 ((Spi_HWUnitType) CSIB5)
339 
340 #define SPI_UNIT_MCSPI3 ((Spi_HWUnitType) CSIB6)
341 
342 #define SPI_UNIT_MCSPI4 ((Spi_HWUnitType) CSIB7)
343 
344 #define SPI_UNIT_MCSPI5 ((Spi_HWUnitType) CSIB8)
345 
346 #define SPI_UNIT_MCSPI6 ((Spi_HWUnitType) CSIB9)
347 
348 #define SPI_UNIT_MCSPI7 ((Spi_HWUnitType) CSIB10)
349 /* @} */
350 
355 #define SPI_HW_UNIT_CNT (11U)
356 
357 extern const uint32 Spi_HwUnitBaseAddr[SPI_HW_UNIT_CNT];
358 
359 /* @} */
360 
361 /* ========================================================================== */
362 /* Structures and Enums */
363 /* ========================================================================== */
364 
365 
366 
367 
372 typedef enum
373 {
374  CSIB0 = 0U,
397 
399 extern void SpiApp_wbInvCache(uint8 *buf, uint16 len);
401 extern void SpiApp_wbCache(uint8 *buf, uint16 len);
403 extern void SpiApp_invCache(uint8 *buf, uint16 len);
404 
405 
406 
408 extern const struct Spi_ConfigType_s SpiDriver;
409 
410 
411 /* ========================================================================== */
412 /* Function Declarations */
413 /* ========================================================================== */
420 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi0TxRx(void);
421 
423 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi1TxRx(void);
424 
426 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi2TxRx(void);
427 
429 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi3TxRx(void);
430 
432 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi4TxRx(void);
433 
435 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi5TxRx(void);
436 
438 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi6TxRx(void);
439 
441 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi7TxRx(void);
442 
443 
444 
445 
446 
447 #ifdef __cplusplus
448 }
449 #endif
450 
451 #endif /* #ifndef SPI_CFG_H_ */
452 
453 /* @} */
Definition: Spi_Cfg.h:376
void Spi_IrqUnitMcuMcspi0TxRx(void)
SPI Hwunit ISR.
void Spi_IrqUnitMcspi3TxRx(void)
SPI MCSPI3 ISR.
Definition: Spi_Cfg.h:388
void Spi_IrqUnitMcspi6TxRx(void)
SPI MCSPI6 ISR.
void Spi_IrqUnitMcuMcspi1TxRx(void)
SPI MCU_MCSPI1 ISR.
const struct Spi_ConfigType_s SpiDriver
SPI Configuration struct declaration.
void SpiApp_wbInvCache(uint8 *buf, uint16 len)
Cache write-back invalidate function.
Definition: Spi_Cfg.h:390
Definition: Spi_Cfg.h:374
Definition: Spi_Cfg.h:378
void Spi_IrqUnitMcspi5TxRx(void)
SPI MCSPI5 ISR.
void SpiApp_wbCache(uint8 *buf, uint16 len)
Cache write-back function.
#define SPI_HW_UNIT_CNT
Total HW units - used for array allocation. This should be +1 of the max unit number.
Definition: Spi_Cfg.h:355
void SpiApp_invCache(uint8 *buf, uint16 len)
Cache invalidate function.
void Spi_IrqUnitMcspi4TxRx(void)
SPI MCSPI4 ISR.
Definition: Spi_Cfg.h:392
void Spi_IrqUnitMcuMcspi2TxRx(void)
SPI MCU_MCSPI2 ISR.
Definition: Spi_Cfg.h:386
Definition: Spi_Cfg.h:380
Spi_HwUnitType
This type defines a range of HW SPI Hardware microcontroller peripheral allocated to this Job.
Definition: Spi_Cfg.h:372
void Spi_IrqUnitMcspi7TxRx(void)
SPI MCSPI7 ISR.
Definition: Spi_Cfg.h:394
const uint32 Spi_HwUnitBaseAddr[SPI_HW_UNIT_CNT]
Definition: Spi_Cfg.h:382
Definition: Spi_Cfg.h:384