J7200_DEV_CPSW0 |
19 |
cpts_comp 0 |
0 |
J7200_DEV_CPSW0 |
19 |
cpts_genf0 0 |
1 |
J7200_DEV_CPSW0 |
19 |
cpts_genf1 0 |
2 |
J7200_DEV_CPSW0 |
19 |
cpts_sync 0 |
3 |
J7200_DEV_CPSW0 |
19 |
evnt_pend 0 |
4 |
J7200_DEV_CPSW0 |
19 |
mdio_pend 0 |
5 |
J7200_DEV_CPSW0 |
19 |
stat_pend 0 |
6 |
J7200_DEV_DCC0 |
30 |
intr_done_level 0 |
0 |
J7200_DEV_DCC1 |
31 |
intr_done_level 0 |
0 |
J7200_DEV_DCC2 |
32 |
intr_done_level 0 |
0 |
J7200_DEV_DCC3 |
33 |
intr_done_level 0 |
0 |
J7200_DEV_DCC4 |
34 |
intr_done_level 0 |
0 |
J7200_DEV_DCC5 |
36 |
intr_done_level 0 |
0 |
J7200_DEV_DCC6 |
37 |
intr_done_level 0 |
0 |
J7200_DEV_DDR0 |
8 |
ddrss_controller 0 |
0 |
J7200_DEV_DDR0 |
8 |
ddrss_hs_phy_global_error 0 |
1 |
J7200_DEV_DDR0 |
8 |
ddrss_pll_freq_change_req 0 |
2 |
J7200_DEV_DDR0 |
8 |
ddrss_v2a_other_err_lvl 0 |
3 |
J7200_DEV_ECAP0 |
80 |
ecap_int 0 |
0 |
J7200_DEV_ECAP1 |
81 |
ecap_int 0 |
0 |
J7200_DEV_ECAP2 |
82 |
ecap_int 0 |
0 |
J7200_DEV_EHRPWM0 |
83 |
epwm_etint 0 |
0 |
J7200_DEV_EHRPWM0 |
83 |
epwm_tripzint 0 |
1 |
J7200_DEV_EHRPWM1 |
84 |
epwm_etint 0 |
0 |
J7200_DEV_EHRPWM1 |
84 |
epwm_tripzint 0 |
1 |
J7200_DEV_EHRPWM2 |
85 |
epwm_etint 0 |
0 |
J7200_DEV_EHRPWM2 |
85 |
epwm_tripzint 0 |
1 |
J7200_DEV_EHRPWM3 |
86 |
epwm_etint 0 |
0 |
J7200_DEV_EHRPWM3 |
86 |
epwm_tripzint 0 |
1 |
J7200_DEV_EHRPWM4 |
87 |
epwm_etint 0 |
0 |
J7200_DEV_EHRPWM4 |
87 |
epwm_tripzint 0 |
1 |
J7200_DEV_EHRPWM5 |
88 |
epwm_etint 0 |
0 |
J7200_DEV_EHRPWM5 |
88 |
epwm_tripzint 0 |
1 |
J7200_DEV_ELM0 |
89 |
elm_porocpsinterrupt_lvl 0 |
0 |
J7200_DEV_EQEP0 |
94 |
eqep_int 0 |
0 |
J7200_DEV_EQEP1 |
95 |
eqep_int 0 |
0 |
J7200_DEV_EQEP2 |
96 |
eqep_int 0 |
0 |
J7200_DEV_GPIO0 |
105 |
gpio_bank 0 to 7 |
0 to 7 |
J7200_DEV_GPIO2 |
107 |
gpio_bank 0 to 7 |
0 to 7 |
J7200_DEV_GPIO4 |
109 |
gpio_bank 0 to 7 |
0 to 7 |
J7200_DEV_GPIO6 |
111 |
gpio_bank 0 to 7 |
0 to 7 |
J7200_DEV_GPMC0 |
115 |
gpmc_sinterrupt 0 |
0 |
J7200_DEV_GTC0 |
61 |
gtc_push_event 0 |
0 |
J7200_DEV_I2C0 |
187 |
pointrpend 0 |
0 |
J7200_DEV_I2C1 |
188 |
pointrpend 0 |
0 |
J7200_DEV_I2C2 |
189 |
pointrpend 0 |
0 |
J7200_DEV_I2C3 |
190 |
pointrpend 0 |
0 |
J7200_DEV_I2C4 |
191 |
pointrpend 0 |
0 |
J7200_DEV_I2C5 |
192 |
pointrpend 0 |
0 |
J7200_DEV_I2C6 |
193 |
pointrpend 0 |
0 |
J7200_DEV_I3C0 |
116 |
i3c__int 0 |
0 |
J7200_DEV_MCAN0 |
156 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN0 |
156 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN1 |
158 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN1 |
158 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN10 |
168 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN10 |
168 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN11 |
169 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN11 |
169 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN12 |
170 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN12 |
170 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN13 |
171 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN13 |
171 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN14 |
150 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN14 |
150 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN15 |
151 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN15 |
151 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN16 |
152 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN16 |
152 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN17 |
153 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN17 |
153 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN2 |
160 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN2 |
160 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN3 |
161 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN3 |
161 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN4 |
162 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN4 |
162 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN5 |
163 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN5 |
163 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN6 |
164 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN6 |
164 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN7 |
165 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN7 |
165 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN8 |
166 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN8 |
166 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCAN9 |
167 |
mcanss_ext_ts_rollover_lvl_int 0 |
0 |
J7200_DEV_MCAN9 |
167 |
mcanss_mcan_lvl_int 0 to 1 |
1 to 2 |
J7200_DEV_MCASP0 |
174 |
rec_intr_pend 0 |
0 |
J7200_DEV_MCASP0 |
174 |
xmit_intr_pend 0 |
1 |
J7200_DEV_MCASP1 |
175 |
rec_intr_pend 0 |
0 |
J7200_DEV_MCASP1 |
175 |
xmit_intr_pend 0 |
1 |
J7200_DEV_MCASP2 |
176 |
rec_intr_pend 0 |
0 |
J7200_DEV_MCASP2 |
176 |
xmit_intr_pend 0 |
1 |
J7200_DEV_MCSPI0 |
266 |
intr_spi 0 |
0 |
J7200_DEV_MCSPI1 |
267 |
intr_spi 0 |
0 |
J7200_DEV_MCSPI2 |
268 |
intr_spi 0 |
0 |
J7200_DEV_MCSPI3 |
269 |
intr_spi 0 |
0 |
J7200_DEV_MCSPI4 |
270 |
intr_spi 0 |
0 |
J7200_DEV_MCSPI5 |
271 |
intr_spi 0 |
0 |
J7200_DEV_MCSPI6 |
272 |
intr_spi 0 |
0 |
J7200_DEV_MCSPI7 |
273 |
intr_spi 0 |
0 |
J7200_DEV_MCU_CPSW0 |
18 |
cpts_comp 0 |
0 |
J7200_DEV_MCU_CPSW0 |
18 |
cpts_genf0 0 |
1 |
J7200_DEV_MCU_CPSW0 |
18 |
cpts_genf1 0 |
2 |
J7200_DEV_MCU_CPSW0 |
18 |
cpts_sync 0 |
3 |
J7200_DEV_MCU_NAVSS0_MCRC_0 |
238 |
dma_event_intr 0 to 3 |
0 to 3 |
J7200_DEV_MCU_NAVSS0_MCRC_0 |
238 |
intaggr_vintr_pend 0 |
4 |
J7200_DEV_MMCSD0 |
91 |
emmcss_intr 0 |
0 |
J7200_DEV_MMCSD1 |
92 |
emmcsdss_intr 0 |
0 |
J7200_DEV_NAVSS0 |
199 |
cpts0_comp 0 |
0 |
J7200_DEV_NAVSS0 |
199 |
cpts0_genf0 0 |
1 |
J7200_DEV_NAVSS0 |
199 |
cpts0_genf1 0 |
2 |
J7200_DEV_NAVSS0 |
199 |
cpts0_genf2 0 |
3 |
J7200_DEV_NAVSS0 |
199 |
cpts0_genf3 0 |
4 |
J7200_DEV_NAVSS0 |
199 |
cpts0_genf4 0 |
5 |
J7200_DEV_NAVSS0 |
199 |
cpts0_genf5 0 |
6 |
J7200_DEV_NAVSS0 |
199 |
cpts0_sync 0 |
7 |
J7200_DEV_NAVSS0_CPTS_0 |
201 |
event_pend_intr 0 |
0 |
J7200_DEV_NAVSS0_MAILBOX_0 |
214 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_1 |
215 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_10 |
224 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_11 |
225 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_2 |
216 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_3 |
217 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_4 |
218 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_5 |
219 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_6 |
220 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_7 |
221 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_8 |
222 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MAILBOX_9 |
223 |
pend_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MCRC_0 |
227 |
dma_event_intr 0 to 3 |
0 to 3 |
J7200_DEV_NAVSS0_MCRC_0 |
227 |
intaggr_vintr_pend 0 |
4 |
J7200_DEV_NAVSS0_VIRTSS |
301 |
dma_pvu0_exp_intr 0 |
0 |
J7200_DEV_NAVSS0_VIRTSS |
301 |
io_pvu0_exp_intr 0 |
1 |
J7200_DEV_PCIE1 |
240 |
pcie_cpts_comp 0 |
0 |
J7200_DEV_PCIE1 |
240 |
pcie_cpts_genf0 0 |
1 |
J7200_DEV_PCIE1 |
240 |
pcie_cpts_hw1_push 0 |
2 |
J7200_DEV_PCIE1 |
240 |
pcie_cpts_pend 0 |
3 |
J7200_DEV_PCIE1 |
240 |
pcie_cpts_sync 0 |
4 |
J7200_DEV_PCIE1 |
240 |
pcie_downstream_pulse 0 |
5 |
J7200_DEV_PCIE1 |
240 |
pcie_dpa_pulse 0 |
6 |
J7200_DEV_PCIE1 |
240 |
pcie_error_pulse 0 |
7 |
J7200_DEV_PCIE1 |
240 |
pcie_flr_pulse 0 |
8 |
J7200_DEV_PCIE1 |
240 |
pcie_hot_reset_pulse 0 |
9 |
J7200_DEV_PCIE1 |
240 |
pcie_legacy_pulse 0 |
10 |
J7200_DEV_PCIE1 |
240 |
pcie_link_state_pulse 0 |
11 |
J7200_DEV_PCIE1 |
240 |
pcie_local_level 0 |
12 |
J7200_DEV_PCIE1 |
240 |
pcie_phy_level 0 |
13 |
J7200_DEV_PCIE1 |
240 |
pcie_ptm_valid_pulse 0 |
14 |
J7200_DEV_PCIE1 |
240 |
pcie_pwr_state_pulse 0 |
15 |
J7200_DEV_TIMER0 |
49 |
intr_pend 0 |
0 |
J7200_DEV_TIMER1 |
50 |
intr_pend 0 |
0 |
J7200_DEV_TIMER10 |
60 |
intr_pend 0 |
0 |
J7200_DEV_TIMER11 |
62 |
intr_pend 0 |
0 |
J7200_DEV_TIMER12 |
63 |
intr_pend 0 |
0 |
J7200_DEV_TIMER13 |
64 |
intr_pend 0 |
0 |
J7200_DEV_TIMER14 |
65 |
intr_pend 0 |
0 |
J7200_DEV_TIMER14 |
65 |
timer_pwm 0 |
1 |
J7200_DEV_TIMER15 |
66 |
intr_pend 0 |
0 |
J7200_DEV_TIMER15 |
66 |
timer_pwm 0 |
1 |
J7200_DEV_TIMER16 |
67 |
intr_pend 0 |
0 |
J7200_DEV_TIMER16 |
67 |
timer_pwm 0 |
1 |
J7200_DEV_TIMER17 |
68 |
intr_pend 0 |
0 |
J7200_DEV_TIMER17 |
68 |
timer_pwm 0 |
1 |
J7200_DEV_TIMER18 |
69 |
intr_pend 0 |
0 |
J7200_DEV_TIMER18 |
69 |
timer_pwm 0 |
1 |
J7200_DEV_TIMER19 |
70 |
intr_pend 0 |
0 |
J7200_DEV_TIMER19 |
70 |
timer_pwm 0 |
1 |
J7200_DEV_TIMER2 |
51 |
intr_pend 0 |
0 |
J7200_DEV_TIMER3 |
52 |
intr_pend 0 |
0 |
J7200_DEV_TIMER4 |
53 |
intr_pend 0 |
0 |
J7200_DEV_TIMER5 |
54 |
intr_pend 0 |
0 |
J7200_DEV_TIMER6 |
55 |
intr_pend 0 |
0 |
J7200_DEV_TIMER7 |
57 |
intr_pend 0 |
0 |
J7200_DEV_TIMER8 |
58 |
intr_pend 0 |
0 |
J7200_DEV_TIMER9 |
59 |
intr_pend 0 |
0 |
J7200_DEV_UART0 |
146 |
usart_irq 0 |
0 |
J7200_DEV_UART1 |
278 |
usart_irq 0 |
0 |
J7200_DEV_UART2 |
279 |
usart_irq 0 |
0 |
J7200_DEV_UART3 |
280 |
usart_irq 0 |
0 |
J7200_DEV_UART4 |
281 |
usart_irq 0 |
0 |
J7200_DEV_UART5 |
282 |
usart_irq 0 |
0 |
J7200_DEV_UART6 |
283 |
usart_irq 0 |
0 |
J7200_DEV_UART7 |
284 |
usart_irq 0 |
0 |
J7200_DEV_UART8 |
285 |
usart_irq 0 |
0 |
J7200_DEV_UART9 |
286 |
usart_irq 0 |
0 |
J7200_DEV_USB0 |
288 |
host_system_error 0 |
0 |
J7200_DEV_USB0 |
288 |
irq 0 to 7 |
1 to 8 |
J7200_DEV_USB0 |
288 |
otgirq 0 |
9 |
J7200_DEV_WKUP_GPIO0 |
113 |
gpio_bank 0 to 5 |
0 to 5 |
J7200_DEV_WKUP_GPIO1 |
114 |
gpio_bank |
0 to 5 |