5. PSDK QNX Components¶
5.1. QNX BSP release¶
The QNX BSP package must be downloaded from QNX Software Center or Contact QNX.
Note
Refer Release Notes software dependencies section and Getting Started for more information.
5.1.1. TI Modifications to the BSP¶
Memory Carveout
Memory sections with pre-defined physical addresses must be set aside in the QNX BSP IFS build file so that the memory is not given to other programs and can be used solely by the remote cores and video codec.
Specify a section to be set aside by modifying the startup line to use the “-r” option. For example, to reserve 0x60000000 bytes (1.5GB), starting at physical address 0xA0000000, on J722S QNX BSP, the build file arguments would be (highlighted below, along with other memory carveout reservations):
[+keeplinked] startup-j722s-evm -v -r0x90000000,0x10000000,1 -r0xA0000000,0x60000000,1 -r0x880000000,0x10000000,1 -r0x940000000,0x60000000,1 -r0x900000000,0x20000000,1
Note
For vision apps remote cores, the memory carveouts are as follows:
The first remote core carevout 0x60000000 (1.5GB) is in the lower 2GB memory range starting at address 0xA0000000.
The second remote core carevout 0x10000000 (256MB) is in the higher 6GB memory range starting at address 0x880000000.
The third remote core carevout 0x20000000 (512MB) is in the higher 6GB memory range starting at address 0x900000000.
For video codecs, the memory carveouts are as follows:
If working with high mem enabled, the memory carveout is in the higher 6GB memory range at address 0x940000000 and of size 0x60000000 (1536MB).
Attention
Only one of the codec carveout configurations needs to be defined (either highmem or lowmem). The reference evm configuration maintains both configurations as a means to validate both.
Reference TI build file
The reference TI build file is provide in the qnx/scripts/bsp/<BSP_REVISION> directory.
# Copy in TI specific build scripts and settings to allow building of a QNX-IFS which supports
# vision_apps demos and video codec demos
cp ${PSDK_RTOS_PATH}/psdkqa/qnx/scripts/bsp/<BSP_REVISION>/j722s-evm-ti.build ${PSDK_RTOS_PATH}/psdkqa/qnx/bsp/images/
Note
Other build file deltas between QNX and TI PSDK QNX environment may be present. TI modifies build scripts for ease of use on TI EVM and running of demonstration software.
5.2. SCI Client Resource Manager¶
The SCI Client Resource Manager (tisci-mgr) provides support for multiple users to make use of the sciclient library from PSDK RTOS without interfering with each other requests. It provides a mechanism to serialize the transactions to the DMSC.
Note
The tisci-mgr logs the SYSFW information to the slogger.
Note
Refer PSDK RTOS Components for more information about each individual component.
Note
Unlike other Jacinto 7 devices, SCI Client only supports polling mode on J722S. For this reason tisci-mgr defaults to polling mode without having to specify -p.
5.3. IPC Resource Manager¶
5.3.1. Overview¶
The IPC resource manager (tiipc-mgr) provides a processor-agnostic API which can be used for communication between processors in a multi-processor environment.
The IPC resource manager provides a user library (tiipc-usr) that exposes the IPC LLD API to QNX applications for communication through the IPC resource manager. The IPC LLD API is described in detail in the MCU+SDK documentation.
Note
The size of the input buffer passed to the RPMessage_recv() API MUST be 528 (IPC_RPMESSAGE_MSG_BUFFER_SIZE) bytes.
5.3.2. Example Application¶
An IPC example application (ipc_test) is provided to test the IPC communication with remote cores running the IPC echo test remote core firmware images. To use this application, the appropriate remote core firmware images need to be built and placed on the target filesystem.
For remote core firmware build instructions, please refer to the IPC LLD MCU+SDK documentation.
Note
The below step to copy the remote core firmware to the rootfs partition of target filesystem is applicable only to the SPL-UBOOT bootflow. For the SBL-BootApp bootflow, the ipc echo test images need to be bundled into the appimage. Please refer to the MCUSW documentation for details.
Once the remote core firmware is built, copy the images to the target filesystem in the rootfs partition. Existing firmware binaries should be backed up as required.
Note
As seen above, the wakeup r5f firmware image is not copied to the target filesystem in the rootfs partition. Instead it need to be built into the tispl.bin as part of the SPL-UBOOT boot binaries. This is not often done as the wakeup r5f is usually reserved for running System Firmware. To skip trying to ping this core use the -s option.
After copying the firmware and booting the target, the ipc_test can be run from the command line (example output given below):
J722S-EVM@QNX:/# ipc_test -s
Creating thread 1 for Core mcu1_0
Creating thread 2 for Core main_r5f
Creating thread 3 for Core c7x_1
Creating thread 4 for Core c7x_2
waiting for thread 1
SendTask4: mpu1_0 <--> c7x_2, Ping- 10, pong - 10 completed
SendTask2: mpu1_0 <--> main_r5f, Ping- 10, pong - 10 completed
SendTask3: mpu1_0 <--> c7x_1, Ping- 10, pong - 10 completed
SendTask0: mpu1_0 <--> mcu1_0, Ping- 10, pong - 10 completed
waiting for thread 2
waiting for thread 3
waiting for thread 4
Exiting the test successfully!!
Make sure that the tiipc-mgr is running before executing the ipc_test. Note that the test app will not exit. Press “ctrl+c” to exit
Note
Run “ipc-test -s” to avoid waiting for the user to exit the test using “ctrl+c”.
Note
Without modification, the ipc_test will not be able to communicate with wkup_r5f0. All other cores will work. Note that wkup_rf50 is not loaded with any firmware image.
Note
Refer PSDK RTOS Components for more information about each individual component.
5.4. UDMA Resource Manager¶
The UDMA resource manager (tiudma-mgr) provides support for multiple users to make use of the UDMA functionality without interfering with each other requests.
Note
Refer PSDK RTOS Components for more information about each individual component.
5.6. CPSW3G io-sock driver¶
5. Overview¶
The CPSW3G io-sock network driver is provided by QNX and conforms to the io-sock architecture. As of the 9.2 release, the CPSW3G io-sock driver has not been validated under SBL. For development purposes, it is suggested to use SPL+Uboot should CPSW3G io-sock be required. It is planned that SBL will support CPSW3G io-sock in 10.0. Please contact your QNX representative to get the latest version of the CPSW3G io-sock driver or for any questions related to io-sock.
5.7. K3conf QNX utility¶
K3CONF is a QNX port of a standalone application designed to provide a quick’n easy way to dynamically diagnose Texas Instruments’ K3 architecture based processors. K3CONF is intended to provide similar experience to that of OMAPCONF that runs on legacy TI platforms.
Note
WARNING: Use at your own risk. And keep the reset button in reach.
To get more details on how to use k3conf utility, run below:
k3conf --help
5.8. VPU Video Codec¶
5.8.1. Overview¶
The WAVE5 Video Processing Unit (VPU) is a 4K Codec that supports both HEVC and H.264/AVC video formats. It provides high performance encode and decode capability for 8-bit YUV video up to 4K @60fps. The VPU is highly optimized for memory bandwidth loading and it has excellent power management.
Encoder:
Capable of encoding H.265/HEVC Main and Main Still Picture Profiles @ L5.1 High tier.
Capable of encoding H.264/AVC Baseline/Constrained Baseline/Main/High Profiles @ L5.2.
Decoder:
Capable of decoding H.265/HEVC Main and Main Still Picture Profiles @ L5.1 High tier.
Capable of decoding H.264/AVC Baseline/Constrained Baseline/Main/High Profiles @ L5.2.
Maximum Resolutions Supported:
Encoder Maximum resolution: 8192x8192
Decoder Maximum resolution: 8192x4320
Note: the VPU can handle the high resolutions, above, but frame-rate performance will be limited
Codec Constraints:
Encoder Minimum resolution: 256x128
H.265/HEVC Decoder Minimum resolution: 8x8
H.264/AVC Decoder Minimum resolution: 32x32
Picture width for encoding shall be a multiple of 8
Picture height for encoding shall be a multiple of 8
Multiple concurrent encode/decode streams:
Number of concurrent streams is dependent on the resolutions and frame rates required
There is only 1 instance of the VPU codec present in the SoC.
Resource Manager for VPU codec:
The codec is managed by a QNX Resource Manager driver. This is responsible to manage access to VPU hardware and can support parallel encode and decode operations, both encode and decode happening either as multi-channel or multi-instance.
Current Software Limitations:
Note
All VPU codec software is currently configured to work with memory in the high-memory region of DDR (using a mem carveout, specifically at 0x940000000). A codec memory carveout must be currently specified in this DDR region to use all the codec test examples given in the usage instructions below.
The entire codec carveout is currently managed by the TI Shared Memory Allocator resource manager (shmemallocator). This means that the omx components or the codec resource manager does not restrict itself with the memory carveout management. The only portion of the resource manager that is aware of the high mem is the WAVE5_PROC_AXI_EXT_ADDR value which is configured to be 0x9 for the high mem. If you choose to relocate your highmem carveout to a location in high mem other than 0x9 xxxx xxxx then you should make the corresponding change for this base address and obviously update the shared memory allocator blocks that track the codec high mem.
Multi-instance Support: The resource manager supports 16 parallel instances of encode and/or decode simultaneously. The test vector resolution and the codec performance are intentionally left unspecified here since they depend on a number of factors - bitrate, fps, number of channels to name a few. For instance, in our test setup, for D1 resolution test vectors, when we do 8 encodes and 8 decodes simultaneously, we see that the internal buffer carveout for VPU needs to be at least 310M.
Decoder: Handling high bit rate (>100mbps) 4K streams
The decoder currently has 2 fixed size input buffers that it expects to be configured as part of the OMX component initialization. These buffers are of 5MB size each and are physically contiguous and adjacent to each other. This configuration lets the VPU hardware see these 2 input buffers as a single 10MB buffer.
When handling high bit rate input streams, the size of these buffers are not enough for the decoder to decode the first full frame. For such specific scenario, it is advised to increase the input buffer size. For a 220mbps bitstream, the decode works for an input buffer size of 10M. Here are the changes needed to get the input buffer size to 10M.
diff --git a/codec/vpu/OpenMAXIL/components/common/omxil_dec_interface.h b/codec/vpu/OpenMAXIL/components/common/omxil_dec_interface.h
index 3e914af9..f55ed0a5 100644
--- a/codec/vpu/OpenMAXIL/components/common/omxil_dec_interface.h
+++ b/codec/vpu/OpenMAXIL/components/common/omxil_dec_interface.h
@@ -34,7 +34,7 @@
#include "tivpu_dec.h"
-#define VDEC_INPUT_BUF_SIZE (5*1024*1024) // Input Buffer size - set to: ((1 / NUM_IN_BUFFERS) * 10MB)
+#define VDEC_INPUT_BUF_SIZE (10*1024*1024) // Input Buffer size - set to: ((1 / NUM_IN_BUFFERS) * 10MB)
/**
* Event types of callback
diff --git a/codec/vpu/OpenMAXIL/test/dec/input.h b/codec/vpu/OpenMAXIL/test/dec/input.h
index 5a874947..36374a92 100644
--- a/codec/vpu/OpenMAXIL/test/dec/input.h
+++ b/codec/vpu/OpenMAXIL/test/dec/input.h
@@ -29,7 +29,7 @@
#define CONFIG_DATA_BUFFER_SIZE 8096
#define DEFAULT_BUFFER_SIZE (2*1024*1024)
-#define INPUT_BUFFER_SIZE (5*1024*1024) // Input Buffer size - set to: ((1 / NUM_IN_BUFFERS) * 10MB)
+#define INPUT_BUFFER_SIZE (10*1024*1024) // Input Buffer size - set to: ((1 / NUM_IN_BUFFERS) * 10MB)
class OmxilVideoDecInput {
diff --git a/codec/vpu/tivpucodec/decoder/tivpu_dec.h b/codec/vpu/tivpucodec/decoder/tivpu_dec.h
index 1234b9c7..0fc59413 100644
--- a/codec/vpu/tivpucodec/decoder/tivpu_dec.h
+++ b/codec/vpu/tivpucodec/decoder/tivpu_dec.h
@@ -24,7 +24,7 @@
#include "main_helper.h"
#define STREAM_BUF_SIZE_DEFAULT (4*1024*1024)
-#define STREAM_BUF_SIZE_HEVC (10*1024*1024) // bitstream size(HEVC:10MB)
+#define STREAM_BUF_SIZE_HEVC (20*1024*1024) // bitstream size(HEVC:10MB)
5.8.2. Usage¶
OMX IL Components for the VPU video encoder & decoder, and file-based OMX encoder & decoder test applications are provided.
omxil_video_enc is capable of using GOP preset to define frame sequence. Current limitations of the encoder hardware prevent from using GOP structures that utilize more than a single reference frame. This allows for the use of consecutive I frame and consecutive P frame (w/ single ref I frame) preset which is shown below in the usage output. If used w/o GOP preset option, default is 0 (custom_GOP) which follows the consecutive P frame (w/ single ref I frame) preset.
Note that running ti-vpu-codec-mgr (The resource manager for VPU) is a pre-requisite for running the OMX test apps for encoder and decoder. Currently, this is launched as part of the startup scripts.
For more details, run the use command for: omxil_video_enc and omxil_video_dec
$ use omxil_video_enc
This is a test application for OpenMAX IL video encode.
It takes input frames from a .yuv file and encodes them to a H.264 bitstream file.
Syntax:
omxil_video_enc <options>
Options:
-C: VPU Core to choose (0 only for j721s2, 0,1 for j722s)
-v: increase verbosity, max 7
-n: stdin not used (no command-line inputs taken)
-i: input file
-o: output file
-s: coding standard (0 = AVC, 1 = HEVC)
-c: config file for encoder parameters
-d: disable display
-a: multi instance mode:
0 or no option - Use the default memory layout
1 or 2 - Use either one of the memory layout
-f: input format for raw input (.yuv/.rgba/etc.)
e.g.: nv12,1920x1080@30
nv12 is the input color format
1920x1080 is resolution(width x height)
30 is frame rate.
Supported input format: nv12.
-L: Enable lossless encoding
-G: Select GOP preset
0 - custom_GOP (default / user defined structure)
1 - all I frames
9 - consecutive P frames, with single reference I frame
Examples:
# Basic built-in help:
omxil_video_enc -h
# AVC file-to-file encode:
omxil_video_enc -vv -i /ti_fs/codec_test/vpu/nv12/8bit_BQTerrace_720x128_9frame_nv12.yuv -o /ti_fs/codec_test/vpu/output/8bit_BQTerrace_720x128.264 -d -f nv12,720x128@30
# AVC file-to-file encode, with config file specified to override default bitrate, etc. :
cp ti_fs/codec_test/vpu/nv12/mix_1920x1080_8b_10frm_nv12.yuv /tmp/
omxil_video_enc -vv -i /tmp/mix_1920x1080_8b_10frm_nv12.yuv -c /ti_fs/codec_test/vpu/cfg/encoder_parameters.conf -o /tmp/mix_1920x1080.264 -d -f nv12,1920x1080@30
$ use omxil_video_dec
This is a test application for OpenMAX IL video decode.
It takes H.264/HEVC frames from a file, decodes and displays them,
or decodes and saves the decoded frames in another file.
Syntax:
omxil_video_dec <options>
Options:
-i: input file
-o: output file, save output to file
-M: Number of output buffers, between 3 and 64 (default 12)
-C: VPU Core to choose (0 only for j721s2, and j722s 0,1 for j784s4)
-v: increase verbosity, max 7
-n: use the second instance of the carveout. Used for multi-instance testing
-p: pseudo-YUV422 output using YUV420 source
Examples:
# AVC file-to-file decode:
omxil_video_dec -v -i /ti_fs/codec_test/bitstream/example.264 -o /ti_fs/codec_test/output/example_nv12.yuv
# HEVC file-to-file decode:
omxil_video_dec -v -i /ti_fs/codec_test/bitstream/example.265 -o /ti_fs/codec_test/output/example_hevc_nv12.yuv
The omx layer component can be configured to use either instance of the VPU HW. This is still work in progress and the omx app will be updated to test this functionality once implemented. The resource manager is capable of handling both instances of the VPU HW.
An initial version of the VPU Encoder/Decoder driver is provided. It is built as a library. The library accompanies a set of unit-test applications which use file-to-file mode.
For more details, run the use command for: vpu_decoder_test, vpu_encoder_test and vpu_multi_inst_test.
$ use vpu_decoder_test
vpu_decoder_test - This is a VPU Decoder unit-test for file-to-file mode
Syntax:
vpu_decoder_test <options>
Options (describes primary options, run with -h for more details)
h Help
codec Codec format (mandatory if using non HEVC encoded input files). Use 0 for AVC, and 12 for HEVC
input Input encoded file to decode (mandatory)
output Output decoded file (mandatory)
Examples:
# Basic help built into the executable
vpu_decoder_test -h
# AVC file-to-file decode
vpu_decoder_test --codec 0 --input /ti_fs/codec_test/bitstream/HistoryOfTI-480p.264 --output /ti_fs/codec_test/vpu/output/HistoryOfTI-480p.264-720x416.yuv
# HEVC file-to-file decode
vpu_decoder_test --input /ti_fs/codec_test/bitstream/TearOfSteel-Short-1280x720.265 --output /ti_fs/codec_test/vpu/output/TearOfSteel-Short-1280x720.265.yuv
Notes:
- This test is applicable only on J722S SoCs
$ use vpu_encoder_test
vpu_encoder_test - This is a VPU Encoder unit-test for file-to-file mode
Syntax:
vpu_encoder_test <options>
Options (describes primary options, run with -h for more details)
h Help
cfgFileName Encoder Config parameters (mandatory)
codec Codec format (mandatory if using non HEVC encoded input files). Use 0 for AVC, and 12 for HEVC
input Input YUV file to encode (optional). Overrides 'InputFile' in cfg file if defined
output Output encoded file (mandatory to store encoded binary into a file)
Examples:
# Basic help built into the executable
vpu_encoder_test -h
# AVC file-to-file encode
vpu_encoder_test --codec 0 --cfgFileName /ti_fs/codec_test/vpu/cfg/avc_inter_8b_02.cfg --output /ti_fs/codec_test/vpu/output/avc_inter_8b_02.cfg.264
# HEVC file-to-file encode
vpu_encoder_test --cfgFileName /ti_fs/codec_test/vpu/cfg/hevc_bg_8b_01.cfg --input /ti_fs/codec_test/vpu/yuv/8bit_BQTerrace_720x128_9frame.yuv --output /ti_fs/codec_test/vpu/output/bg_8b_01.cfg.265
Notes:
- This test is applicable only on J722S SoCs
$ use vpu_multi_inst_test
vpu_multi_inst_test - This is a VPU Multi-instance Decode/Encode unit-test (file-to-file mode)
Syntax:
vpu_multi_inst_test --instance-num=<N> -e <test-1>,..,<test-N> --codec=<codec-1>,..,<codec-N> --input <in-1>,..,<in-N> --output <out-1>,..,<out-N>
Options (describes primary options, run with -h for more details)
h Help
instance-num Total number of test instances to run
e 0: decode, 1: encode (per test)
codec Codec format. Use 0 for AVC, and 12 for HEVC (per test)
enable-wtl Enables WTL option (per test), if set to 1, for decoded outputs to be written in linear fashion for a framebuffer
input Input bitstream for decode, or Input .cfg file for encode (per test)
output Output decoded YUV file, or Output encoded bitstream file (per test)
Examples:
# Basic help built into the executable
vpu_multi_inst_test -h
# AVC decode + HEVC encode, and write the decoded output to a single YUV file
vpu_multi_inst_test --instance-num=2 -e 0,1 --codec=0,12 --enable-wtl=1 \
--input /ti_fs/codec_test/bitstream/HistoryOfTI-480p.264,/ti_fs/codec_test/vpu/cfg/hevc_bg_8b_01.cfg \
--output /ti_fs/codec_test/vpu/output/HistoryOfTI-480p.264-720x416.yuv,/ti_fs/codec_test/vpu/output/bg_8b_01.cfg.265
Notes:
- This test is applicable only on J722S SoCs
5.8.3. Performance¶
The resource manager supports making performance measurements for the decoder and encoder. Once enabled, the resource manager creates a slog based performance log per core per channel, in a directory pointed by the environment variable VPU_PERFORMANCE_LOG_DIR. The log will have per frame decode time, total time taken for the decode, the number of frames decoded and the average fps.
To enable this feature, please follow the steps mentioned below:
Set the environment variable VPU_PERFORMANCE_LOG_DIR (for eg: export VPU_PERFORMANCE_LOG_DIR=/tmp/)
Slay the resource manager if already running (slay ti-vpu-codec-mgr)
Re-launch the resource manager from the same console, so that it has the VPU_PERFORMANCE_LOG_DIR env value.
Run the codec use case and you will see a file performance_log_0_ch_0.log
To disable this feature, unset the env variable, slay and relaunch the resource manager.
Sample output for the performance log is shown below:
For encoder:
1970-01-01 19:48:50.224 [OpenMAXIL.] started encoding
1970-01-01 19:49:01.149 [OpenMAXIL.] Total encoding time 10925 ms.
1970-01-01 19:49:01.149 [OpenMAXIL.] Number of encoded frames 601
1970-01-01 19:49:01.149 [OpenMAXIL.] Encoding frame rate is 55.01 fps.
For decoder:
1970-01-01 00:50:48.327 [OpenMAXIL.] [0] done decoding frame
1970-01-01 00:50:48.327 [OpenMAXIL.] Decoding time for frame = 0 ms
1970-01-01 00:50:48.327 [OpenMAXIL.] Total decoding time 1195 ms.
1970-01-01 00:50:48.327 [OpenMAXIL.] Number of decoded frames 42
1970-01-01 00:50:48.327 [OpenMAXIL.] Decoding frame rate is 35.15 fps.