3.2.3. Kernel Drivers

• 3.2.3.1. ADC
• 3.2.3.2. Crypto
• 3.2.3.3. DCAN
• 3.2.3.4. GPIO
• 3.2.3.5. I2C
• 3.2.3.6. CPSW2g Ethernet
  • 3.2.3.6.1. Introduction
  • 3.2.3.6.2. Driver Configuration
  • 3.2.3.6.3. Device tree bindings
  • 3.2.3.6.4. MAC mode
    • 3.2.3.6.4.1. Interrupt pacing
    • 3.2.3.6.4.2. Common Platform Time Sync (CPTS) module
    • 3.2.3.6.4.3. Enhancements for Scheduled Traffic (EST) Offload
    • 3.2.3.6.4.4. Intersperse Express Traffic (IET) Frame Preemption offload
    • 3.2.3.6.4.5. Forwarding and Queuing Enhancements for Time-Sensitive Streams (FQTSS, 802.1Qav)
      • 3.2.3.6.4.5.1. Host port ingress, CPPI Port Receive Rate Limiting offload
      • 3.2.3.6.4.5.2. Switch egress, Ethernet Port Transmit Rate Limiting offload
  • 3.2.3.6.5. Errata: i2329 MDIO interface corruption (CPSW and PRUSS)
    • 3.2.3.6.5.1. Description
    • 3.2.3.6.5.2. Workaround for TI SDK Version > 8.4
• 3.2.3.7. CPSWng virtual MAC (remoteproc)
  • 3.2.3.7.1. Introduction
    • 3.2.3.7.1.1. Virtual MAC switch mode
    • 3.2.3.7.1.2. Virtual MAC only mode
    • 3.2.3.7.1.3. Drivers initialization
    • 3.2.3.7.1.4. rpmsg_kdrv_switch driver
    • 3.2.3.7.1.5. j721e-cpsw-virt-mac driver
    • 3.2.3.7.1.6. Network data flow
  • 3.2.3.7.2. Driver Configuration
  • 3.2.3.7.3. Device tree bindings
  • 3.2.3.7.4. User guide
    • 3.2.3.7.4.1. Starting the interface
    • 3.2.3.7.4.2. Set MAC address
    • 3.2.3.7.4.3. ethtool interface
      • 3.2.3.7.4.3.1. Get driver information
      • 3.2.3.7.4.3.2. Display standard information about device/link
      • 3.2.3.7.4.3.3. Show permanent hardware address
      • 3.2.3.7.4.3.4. RX/TX checksum offload
      • 3.2.3.7.4.3.5. Driver testing
    • 3.2.3.7.4.4. Interrupt pacing
    • 3.2.3.7.4.5. Multicast (MC) filtering
• 3.2.3.8. TSN with CPSW
  • 3.2.3.8.1. Introduction
  • 3.2.3.8.2. Testing Details
  • 3.2.3.8.3. Tests
    • 3.2.3.8.3.1. PTP
      • 3.2.3.8.3.1.1. Setup
      • 3.2.3.8.3.1.2. PTP with Ordinary Clock (MAC mode)
        • 3.2.3.8.3.1.2.1. J7VCL as master clock and AM625-SK as slave clock
        • 3.2.3.8.3.1.2.2. AM625-SK as master clock and J7VCL as slave clock
      • 3.2.3.8.3.1.3. PTP with Transparent Clock (Switch mode)
        • 3.2.3.8.3.1.3.1. J7VCL as transparent clock, PC as master clock and AM625-SK as slave clock
        • 3.2.3.8.3.1.3.2. AM625-SK as transparent clock, PC as master clock and J7VCL as slave clock
    • 3.2.3.8.3.2. EST
      • 3.2.3.8.3.2.1. Setup
      • 3.2.3.8.3.2.2. EST Testing in MAC mode
        • 3.2.3.8.3.2.2.1. EST scheduled on AM625-SK with J7VCL receiving the packets
        • 3.2.3.8.3.2.2.2. EST scheduled on J7VCL with AM625-SK receiving the packets
        • 3.2.3.8.3.2.2.3. EST scheduled on ports 1 and 2 of AM625-SK’s CPSW3G and received by J7VCL
        • 3.2.3.8.3.2.2.4. EST scheduled on ports 1 and 2 of J7VCL’s CPSW5G and received by AM625-SK
      • 3.2.3.8.3.2.3. EST Testing in Switch mode
        • 3.2.3.8.3.2.3.1. AM625-SK acting as a switch and implementing EST schedule
        • 3.2.3.8.3.2.3.2. J7VCL acting as a switch and implementing EST schedule
    • 3.2.3.8.3.3. CBS
      • 3.2.3.8.3.3.1. CBS in MAC mode
        • 3.2.3.8.3.3.1.1. Rate-limiting Host Port Ingress on AM625-SK
        • 3.2.3.8.3.3.1.2. Rate-limiting Host Port Ingress on J7VCL
        • 3.2.3.8.3.3.1.3. Rate-limiting Switch Egress on AM625-SK (Data sent from Host Port of AM625-SK to J7VCL)
        • 3.2.3.8.3.3.1.4. Rate-limiting Switch Egress on J7VCL (Data sent from Host Port of J7VCL to AM625-SK)
      • 3.2.3.8.3.3.2. CBS in Switch mode
        • 3.2.3.8.3.3.2.1. Rate limiting Switch Egress on AM625-SK (Data sent from AM64-SK to J7VCL via AM625-SK switch)
        • 3.2.3.8.3.3.2.2. Rate-limiting Switch Egress on J7VCL (Data sent from AM64-SK to AM625-SK via J7VCL switch)
    • 3.2.3.8.3.4. IET
      • 3.2.3.8.3.4.1. Warning: IET with Fixed-Link Interface
      • 3.2.3.8.3.4.2. IET in MAC mode
        • 3.2.3.8.3.4.2.1. AM625-SK fragments frames and J7VCL assembles them
        • 3.2.3.8.3.4.2.2. J7VCL fragments frames and AM625-SK assembles them
      • 3.2.3.8.3.4.3. IET in Switch mode
        • 3.2.3.8.3.4.3.1. CASE-1: Frame is preempted on Sender and Assembled on Switch Ingress Port
        • 3.2.3.8.3.4.3.2. CASE-2: Frame is preempted on Switch Egress Port and Assembled on Receiver
        • 3.2.3.8.3.4.3.3. CASE-3: Frame is preempted on both Sender and Switch Egress Port
    • 3.2.3.8.3.5. TSN Switch Tuning Guide
      • 3.2.3.8.3.5.1. Background
      • 3.2.3.8.3.5.2. EST (Enhanced Scheduler for Traffic)
      • 3.2.3.8.3.5.3. CBS (Credit Based Shaper)
      • 3.2.3.8.3.5.4. IET (Interspersing Express Traffic)
• 3.2.3.9. PCIe End Point
• 3.2.3.10. PCIe Root Complex
• 3.2.3.11. OSPI/QSPI
• 3.2.3.12. SPI
• 3.2.3.13. NAND
• 3.2.3.14. MMC/SD
  • 3.2.3.14.1. Introduction
  • 3.2.3.14.2. References
  • 3.2.3.14.3. Acronyms & Definitions
  • 3.2.3.14.4. Features
  • 3.2.3.14.5. Supported High Speed Modes
  • 3.2.3.14.6. Driver Configuration
• 3.2.3.15. UART
  • 3.2.3.15.1. Introduction
  • 3.2.3.15.2. Driver Features
  • 3.2.3.15.3. Basic External loopback testing
• 3.2.3.16. USB
  • 3.2.3.16.1. Introduction
  • 3.2.3.16.2. TI SoC Integration
  • 3.2.3.16.3. EVM
• 3.2.3.17. Voltage & Thermal Management (VTM)
  • 3.2.3.17.1. Introduction
  • 3.2.3.17.2. Driver Features
  • 3.2.3.17.3. Finding More Information