SDL API Guide for J742S2
sdlr_esm.h
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31  *
32  * Name : sdlr_esm.h
33 */
34 #ifndef SDLR_ESM_H_
35 #define SDLR_ESM_H_
36 
37 #ifdef __cplusplus
38 extern "C"
39 {
40 #endif
41 #include <sdlr.h>
42 #include <stdint.h>
43 
44 /**************************************************************************
45 * Module Base Offset Values
46 **************************************************************************/
47 
48 #define SDL_ESM_REGS_BASE (0x00000000U)
49 
50 
51 /**************************************************************************
52 * Hardware Region : ESM Registers
53 **************************************************************************/
54 
55 
56 /**************************************************************************
57 * Register Overlay Structure
58 **************************************************************************/
59 
60 typedef struct {
61  volatile uint32_t RAW; /* Config Error Raw Status/Set Register */
62  volatile uint32_t STS; /* Level Error Interrupt Enable Status/Clear Register */
63  volatile uint32_t INTR_EN_SET; /* Level Error Interrutp Enable Set Register */
64  volatile uint32_t INTR_EN_CLR; /* Level Error Interrupt Enabled Clear Register */
65  volatile uint32_t INT_PRIO; /* Level Error Interrupt Enabled Clear Register */
66  volatile uint32_t PIN_EN_SET; /* Level Error Interrupt Enabled Clear Register */
67  volatile uint32_t PIN_EN_CLR; /* Level Error Interrupt Enabled Clear Register */
68  volatile uint8_t Resv_32[4];
69 } SDL_esmRegs_ERR_GRP;
70 
71 
72 typedef struct {
73  volatile uint32_t PID; /* Revision Register */
74  volatile uint32_t INFO; /* Info Register */
75  volatile uint32_t EN; /* Global Enable Register */
76  volatile uint32_t SFT_RST; /* Global Soft Reset Register */
77  volatile uint32_t ERR_RAW; /* Config Error Raw Status/Set Register */
78  volatile uint32_t ERR_STS; /* Config Error Interrupt Enable Status/Clear Register */
79  volatile uint32_t ERR_EN_SET; /* Config Error Interrutp Enable Set Register */
80  volatile uint32_t ERR_EN_CLR; /* Config Error Interrupt Enabled Clear Register */
81  volatile uint32_t LOW_PRI; /* Low Priority Prioritized Register */
82  volatile uint32_t HI_PRI; /* High Priority Prioritized Register */
83  volatile uint32_t LOW; /* Low Priority Interrupt Status Register */
84  volatile uint32_t HI; /* High Priority Interrupt Status Register */
85  volatile uint32_t EOI; /* EOI Interrupt Register */
86  volatile uint8_t Resv_64[12];
87  volatile uint32_t PIN_CTRL; /* Error Pin Control Register */
88  volatile uint32_t PIN_STS; /* Error Pin Status Register */
89  volatile uint32_t PIN_CNTR; /* Error Counter Value Register */
90  volatile uint32_t PIN_CNTR_PRE; /* Error Counter Value Pre-Load Register */
91  volatile uint32_t PWMH_PIN_CNTR; /* Error PWM High Counter Value Register */
92  volatile uint32_t PWMH_PIN_CNTR_PRE; /* Error PWM High Counter Value Pre-Load Register */
93  volatile uint32_t PWML_PIN_CNTR; /* Error PWM Low Counter Value Register */
94  volatile uint32_t PWML_PIN_CNTR_PRE; /* Error PWM Low Counter Value Pre-Load Register */
95  volatile uint8_t Resv_1024[944];
96  SDL_esmRegs_ERR_GRP ERR_GRP[32];
97 } SDL_esmRegs;
98 
99 
100 /**************************************************************************
101 * Register Macros
102 **************************************************************************/
103 
104 #define SDL_ESM_PID (0x00000000U)
105 #define SDL_ESM_INFO (0x00000004U)
106 #define SDL_ESM_EN (0x00000008U)
107 #define SDL_ESM_SFT_RST (0x0000000CU)
108 #define SDL_ESM_ERR_RAW (0x00000010U)
109 #define SDL_ESM_ERR_STS (0x00000014U)
110 #define SDL_ESM_ERR_EN_SET (0x00000018U)
111 #define SDL_ESM_ERR_EN_CLR (0x0000001CU)
112 #define SDL_ESM_LOW_PRI (0x00000020U)
113 #define SDL_ESM_HI_PRI (0x00000024U)
114 #define SDL_ESM_LOW (0x00000028U)
115 #define SDL_ESM_HI (0x0000002CU)
116 #define SDL_ESM_EOI (0x00000030U)
117 #define SDL_ESM_PIN_CTRL (0x00000040U)
118 #define SDL_ESM_PIN_STS (0x00000044U)
119 #define SDL_ESM_PIN_CNTR (0x00000048U)
120 #define SDL_ESM_PIN_CNTR_PRE (0x0000004CU)
121 #define SDL_ESM_PWMH_PIN_CNTR (0x00000050U)
122 #define SDL_ESM_PWMH_PIN_CNTR_PRE (0x00000054U)
123 #define SDL_ESM_PWML_PIN_CNTR (0x00000058U)
124 #define SDL_ESM_PWML_PIN_CNTR_PRE (0x0000005CU)
125 #define SDL_ESM_ERR_GRP_RAW(ERR_GRP) (0x00000400U+((ERR_GRP)*0x20U))
126 #define SDL_ESM_ERR_GRP_STS(ERR_GRP) (0x00000404U+((ERR_GRP)*0x20U))
127 #define SDL_ESM_ERR_GRP_INTR_EN_SET(ERR_GRP) (0x00000408U+((ERR_GRP)*0x20U))
128 #define SDL_ESM_ERR_GRP_INTR_EN_CLR(ERR_GRP) (0x0000040CU+((ERR_GRP)*0x20U))
129 #define SDL_ESM_ERR_GRP_INT_PRIO(ERR_GRP) (0x00000410U+((ERR_GRP)*0x20U))
130 #define SDL_ESM_ERR_GRP_PIN_EN_SET(ERR_GRP) (0x00000414U+((ERR_GRP)*0x20U))
131 #define SDL_ESM_ERR_GRP_PIN_EN_CLR(ERR_GRP) (0x00000418U+((ERR_GRP)*0x20U))
132 
133 /**************************************************************************
134 * Field Definition Macros
135 **************************************************************************/
136 
137 
138 /* RAW */
139 
140 #define SDL_ESM_ERR_GRP_RAW_STS_MASK (0xFFFFFFFFU)
141 #define SDL_ESM_ERR_GRP_RAW_STS_SHIFT (0x00000000U)
142 #define SDL_ESM_ERR_GRP_RAW_STS_MAX (0xFFFFFFFFU)
143 
144 /* STS */
145 
146 #define SDL_ESM_ERR_GRP_STS_MSK_MASK (0xFFFFFFFFU)
147 #define SDL_ESM_ERR_GRP_STS_MSK_SHIFT (0x00000000U)
148 #define SDL_ESM_ERR_GRP_STS_MSK_MAX (0xFFFFFFFFU)
149 
150 /* INTR_EN_SET */
151 
152 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MASK (0xFFFFFFFFU)
153 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_SHIFT (0x00000000U)
154 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MAX (0xFFFFFFFFU)
155 
156 /* INTR_EN_CLR */
157 
158 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MASK (0xFFFFFFFFU)
159 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_SHIFT (0x00000000U)
160 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MAX (0xFFFFFFFFU)
161 
162 /* INT_PRIO */
163 
164 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_MASK (0xFFFFFFFFU)
165 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_SHIFT (0x00000000U)
166 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_MAX (0xFFFFFFFFU)
167 
168 /* PIN_EN_SET */
169 
170 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MASK (0xFFFFFFFFU)
171 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_SHIFT (0x00000000U)
172 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MAX (0xFFFFFFFFU)
173 
174 /* PIN_EN_CLR */
175 
176 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MASK (0xFFFFFFFFU)
177 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_SHIFT (0x00000000U)
178 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MAX (0xFFFFFFFFU)
179 
180 /* PID */
181 
182 #define SDL_ESM_PID_MINOR_MASK (0x0000003FU)
183 #define SDL_ESM_PID_MINOR_SHIFT (0x00000000U)
184 #define SDL_ESM_PID_MINOR_MAX (0x0000003FU)
185 
186 #define SDL_ESM_PID_CUSTOM_MASK (0x000000C0U)
187 #define SDL_ESM_PID_CUSTOM_SHIFT (0x00000006U)
188 #define SDL_ESM_PID_CUSTOM_MAX (0x00000003U)
189 
190 #define SDL_ESM_PID_MAJOR_MASK (0x00000700U)
191 #define SDL_ESM_PID_MAJOR_SHIFT (0x00000008U)
192 #define SDL_ESM_PID_MAJOR_MAX (0x00000007U)
193 
194 #define SDL_ESM_PID_RTL_MASK (0x0000F800U)
195 #define SDL_ESM_PID_RTL_SHIFT (0x0000000BU)
196 #define SDL_ESM_PID_RTL_MAX (0x0000001FU)
197 
198 #define SDL_ESM_PID_FUNC_MASK (0x0FFF0000U)
199 #define SDL_ESM_PID_FUNC_SHIFT (0x00000010U)
200 #define SDL_ESM_PID_FUNC_MAX (0x00000FFFU)
201 
202 #define SDL_ESM_PID_BU_MASK (0x30000000U)
203 #define SDL_ESM_PID_BU_SHIFT (0x0000001CU)
204 #define SDL_ESM_PID_BU_MAX (0x00000003U)
205 
206 #define SDL_ESM_PID_SCHEME_MASK (0xC0000000U)
207 #define SDL_ESM_PID_SCHEME_SHIFT (0x0000001EU)
208 #define SDL_ESM_PID_SCHEME_MAX (0x00000003U)
209 
210 /* INFO */
211 
212 #define SDL_ESM_INFO_GROUPS_MASK (0x000000FFU)
213 #define SDL_ESM_INFO_GROUPS_SHIFT (0x00000000U)
214 #define SDL_ESM_INFO_GROUPS_MAX (0x000000FFU)
215 
216 #define SDL_ESM_INFO_PULSE_GROUPS_MASK (0x0000FF00U)
217 #define SDL_ESM_INFO_PULSE_GROUPS_SHIFT (0x00000008U)
218 #define SDL_ESM_INFO_PULSE_GROUPS_MAX (0x000000FFU)
219 
220 #define SDL_ESM_INFO_LAST_RESET_MASK (0x80000000U)
221 #define SDL_ESM_INFO_LAST_RESET_SHIFT (0x0000001FU)
222 #define SDL_ESM_INFO_LAST_RESET_MAX (0x00000001U)
223 
224 /* EN */
225 
226 #define SDL_ESM_EN_KEY_MASK (0x0000000FU)
227 #define SDL_ESM_EN_KEY_SHIFT (0x00000000U)
228 #define SDL_ESM_EN_KEY_MAX (0x0000000FU)
229 
230 /* SFT_RST */
231 
232 #define SDL_ESM_SFT_RST_KEY_MASK (0x0000000FU)
233 #define SDL_ESM_SFT_RST_KEY_SHIFT (0x00000000U)
234 #define SDL_ESM_SFT_RST_KEY_MAX (0x0000000FU)
235 
236 /* ERR_RAW */
237 
238 #define SDL_ESM_ERR_RAW_STS_MASK (0xFFFFFFFFU)
239 #define SDL_ESM_ERR_RAW_STS_SHIFT (0x00000000U)
240 #define SDL_ESM_ERR_RAW_STS_MAX (0xFFFFFFFFU)
241 
242 /* ERR_STS */
243 
244 #define SDL_ESM_ERR_STS_MSK_MASK (0xFFFFFFFFU)
245 #define SDL_ESM_ERR_STS_MSK_SHIFT (0x00000000U)
246 #define SDL_ESM_ERR_STS_MSK_MAX (0xFFFFFFFFU)
247 
248 /* ERR_EN_SET */
249 
250 #define SDL_ESM_ERR_EN_SET_MSK_MASK (0xFFFFFFFFU)
251 #define SDL_ESM_ERR_EN_SET_MSK_SHIFT (0x00000000U)
252 #define SDL_ESM_ERR_EN_SET_MSK_MAX (0xFFFFFFFFU)
253 
254 /* ERR_EN_CLR */
255 
256 #define SDL_ESM_ERR_EN_CLR_MSK_MASK (0xFFFFFFFFU)
257 #define SDL_ESM_ERR_EN_CLR_MSK_SHIFT (0x00000000U)
258 #define SDL_ESM_ERR_EN_CLR_MSK_MAX (0xFFFFFFFFU)
259 
260 /* LOW_PRI */
261 
262 #define SDL_ESM_LOW_PRI_PLS_MASK (0xFFFF0000U)
263 #define SDL_ESM_LOW_PRI_PLS_SHIFT (0x00000010U)
264 #define SDL_ESM_LOW_PRI_PLS_MAX (0x0000FFFFU)
265 
266 #define SDL_ESM_LOW_PRI_LVL_MASK (0x0000FFFFU)
267 #define SDL_ESM_LOW_PRI_LVL_SHIFT (0x00000000U)
268 #define SDL_ESM_LOW_PRI_LVL_MAX (0x0000FFFFU)
269 
270 /* HI_PRI */
271 
272 #define SDL_ESM_HI_PRI_PLS_MASK (0xFFFF0000U)
273 #define SDL_ESM_HI_PRI_PLS_SHIFT (0x00000010U)
274 #define SDL_ESM_HI_PRI_PLS_MAX (0x0000FFFFU)
275 
276 #define SDL_ESM_HI_PRI_LVL_MASK (0x0000FFFFU)
277 #define SDL_ESM_HI_PRI_LVL_SHIFT (0x00000000U)
278 #define SDL_ESM_HI_PRI_LVL_MAX (0x0000FFFFU)
279 
280 /* LOW */
281 
282 #define SDL_ESM_LOW_STS_MASK (0xFFFFFFFFU)
283 #define SDL_ESM_LOW_STS_SHIFT (0x00000000U)
284 #define SDL_ESM_LOW_STS_MAX (0xFFFFFFFFU)
285 
286 /* HI */
287 
288 #define SDL_ESM_HI_STS_MASK (0xFFFFFFFFU)
289 #define SDL_ESM_HI_STS_SHIFT (0x00000000U)
290 #define SDL_ESM_HI_STS_MAX (0xFFFFFFFFU)
291 
292 /* EOI */
293 
294 #define SDL_ESM_EOI_KEY_MASK (0x000007FFU)
295 #define SDL_ESM_EOI_KEY_SHIFT (0x00000000U)
296 #define SDL_ESM_EOI_KEY_MAX (0x000007FFU)
297 
298 /* PIN_CTRL */
299 
300 #define SDL_ESM_PIN_CTRL_KEY_MASK (0x0000000FU)
301 #define SDL_ESM_PIN_CTRL_KEY_SHIFT (0x00000000U)
302 #define SDL_ESM_PIN_CTRL_KEY_MAX (0x0000000FU)
303 #define SDL_ESM_PIN_CTRL_PWM_EN_MASK (0x000000F0U)
304 #define SDL_ESM_PIN_CTRL_PWM_EN_SHIFT (0x00000004U)
305 #define SDL_ESM_PIN_CTRL_PWM_EN_MAX (0x0000000FU)
306 
307 /* PIN_STS */
308 
309 #define SDL_ESM_PIN_STS_VAL_MASK (0x00000001U)
310 #define SDL_ESM_PIN_STS_VAL_SHIFT (0x00000000U)
311 #define SDL_ESM_PIN_STS_VAL_MAX (0x00000001U)
312 
313 /* PIN_CNTR */
314 
315 #define SDL_ESM_PIN_CNTR_COUNT_MASK (0x00FFFFFFU)
316 #define SDL_ESM_PIN_CNTR_COUNT_SHIFT (0x00000000U)
317 #define SDL_ESM_PIN_CNTR_COUNT_MAX (0x00FFFFFFU)
318 
319 /* PIN_CNTR_PRE */
320 
321 #define SDL_ESM_PIN_CNTR_PRE_COUNT_MASK (0x00FFFFFFU)
322 #define SDL_ESM_PIN_CNTR_PRE_COUNT_SHIFT (0x00000000U)
323 #define SDL_ESM_PIN_CNTR_PRE_COUNT_MAX (0x00FFFFFFU)
324 
325 #ifdef __cplusplus
326 }
327 #endif
328 #endif /* SDLR_ESM_ */
SDL_esmRegs_ERR_GRP::RAW
volatile uint32_t RAW
Definition: sdlr_esm.h:61
SDL_esmRegs::ERR_STS
volatile uint32_t ERR_STS
Definition: sdlr_esm.h:78
SDL_esmRegs::EOI
volatile uint32_t EOI
Definition: sdlr_esm.h:85
SDL_esmRegs::SFT_RST
volatile uint32_t SFT_RST
Definition: sdlr_esm.h:76
SDL_esmRegs::PWMH_PIN_CNTR
volatile uint32_t PWMH_PIN_CNTR
Definition: sdlr_esm.h:91
SDL_esmRegs::EN
volatile uint32_t EN
Definition: sdlr_esm.h:75
SDL_esmRegs
Definition: sdlr_esm.h:72
SDL_esmRegs::INFO
volatile uint32_t INFO
Definition: sdlr_esm.h:74
SDL_esmRegs::ERR_EN_CLR
volatile uint32_t ERR_EN_CLR
Definition: sdlr_esm.h:80
SDL_esmRegs::PIN_CNTR_PRE
volatile uint32_t PIN_CNTR_PRE
Definition: sdlr_esm.h:90
SDL_esmRegs::PWML_PIN_CNTR_PRE
volatile uint32_t PWML_PIN_CNTR_PRE
Definition: sdlr_esm.h:94
SDL_esmRegs::LOW_PRI
volatile uint32_t LOW_PRI
Definition: sdlr_esm.h:81
SDL_esmRegs::LOW
volatile uint32_t LOW
Definition: sdlr_esm.h:83
SDL_esmRegs_ERR_GRP::PIN_EN_CLR
volatile uint32_t PIN_EN_CLR
Definition: sdlr_esm.h:67
SDL_esmRegs::HI
volatile uint32_t HI
Definition: sdlr_esm.h:84
SDL_esmRegs::PIN_CTRL
volatile uint32_t PIN_CTRL
Definition: sdlr_esm.h:87
SDL_esmRegs::ERR_EN_SET
volatile uint32_t ERR_EN_SET
Definition: sdlr_esm.h:79
SDL_esmRegs::PWMH_PIN_CNTR_PRE
volatile uint32_t PWMH_PIN_CNTR_PRE
Definition: sdlr_esm.h:92
SDL_esmRegs_ERR_GRP
Definition: sdlr_esm.h:60
SDL_esmRegs_ERR_GRP::INTR_EN_SET
volatile uint32_t INTR_EN_SET
Definition: sdlr_esm.h:63
SDL_esmRegs::ERR_RAW
volatile uint32_t ERR_RAW
Definition: sdlr_esm.h:77
SDL_esmRegs_ERR_GRP::INTR_EN_CLR
volatile uint32_t INTR_EN_CLR
Definition: sdlr_esm.h:64
SDL_esmRegs::PIN_STS
volatile uint32_t PIN_STS
Definition: sdlr_esm.h:88
SDL_esmRegs_ERR_GRP::STS
volatile uint32_t STS
Definition: sdlr_esm.h:62
SDL_esmRegs::HI_PRI
volatile uint32_t HI_PRI
Definition: sdlr_esm.h:82
SDL_esmRegs::PID
volatile uint32_t PID
Definition: sdlr_esm.h:73
SDL_esmRegs::PWML_PIN_CNTR
volatile uint32_t PWML_PIN_CNTR
Definition: sdlr_esm.h:93
SDL_esmRegs_ERR_GRP::INT_PRIO
volatile uint32_t INT_PRIO
Definition: sdlr_esm.h:65
SDL_esmRegs::PIN_CNTR
volatile uint32_t PIN_CNTR
Definition: sdlr_esm.h:89
SDL_esmRegs_ERR_GRP::PIN_EN_SET
volatile uint32_t PIN_EN_SET
Definition: sdlr_esm.h:66