PDK API Guide for J742S2
csl_mdio.h
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1 
70 #ifndef CSL_MDIO_V5_H
71 #define CSL_MDIO_V5_H
72 
73 #ifdef __cplusplus
74 extern "C" {
75 #endif
76 
77 
78 #include <ti/csl/soc.h>
79 #include <ti/csl/csl.h>
80 #include <ti/csl/cslr_mdio.h>
81 
82 
91 #include <string.h>
92 #include <stdbool.h>
93 #include <ti/csl/cslr.h>
94 #include <ti/csl/hw_types.h>
95 #include <ti/csl/csl_mdio_def.h>
96 
97 typedef volatile CSL_MdioRegs *CSL_mdioHandle;
98 
139  CSL_mdioHandle hMdioRegs,
140  CSL_MDIO_VERSION* mdioVersionInfo
141 );
142 
143 
174 uint16_t CSL_MDIO_getClkDivVal(
175  CSL_mdioHandle hMdioRegs
176 );
177 
178 
218  CSL_mdioHandle hMdioRegs,
219  uint16_t clkDivVal
220 );
221 
259  CSL_mdioHandle hMdioRegs
260 );
261 
292  CSL_mdioHandle hMdioRegs
293 );
294 
328  CSL_mdioHandle hMdioRegs
329 );
330 
374 uint32_t CSL_MDIO_isPhyAlive(
375  CSL_mdioHandle hMdioRegs,
376  uint32_t phyAddr
377 );
378 
379 
422 uint32_t CSL_MDIO_isPhyLinked(
423  CSL_mdioHandle hMdioRegs,
424  uint32_t phyAddr
425 );
426 
474  CSL_mdioHandle hMdioRegs,
475  uint32_t index
476 );
477 
478 
517  CSL_mdioHandle hMdioRegs,
518  uint32_t index
519 );
520 
534 uint32_t CSL_MDIO_phyRegRead(uint32_t baseAddr,
535  uint32_t phyAddr,
536  uint32_t regNum,
537  uint16_t *pData);
538 
551 void CSL_MDIO_phyRegWrite(uint32_t baseAddr, uint32_t phyAddr, uint32_t regNum, uint16_t wrVal);
552 
565 void CSL_MDIO_setMdclkHigh(CSL_mdioHandle hMdioRegs);
566 
579 void CSL_MDIO_setMdclkLow(CSL_mdioHandle hMdioRegs);
580 
593 void CSL_MDIO_setMdoHigh(CSL_mdioHandle hMdioRegs);
594 
607 void CSL_MDIO_setMdoLow(CSL_mdioHandle hMdioRegs);
608 
623 uint32_t CSL_MDIO_readMdi(CSL_mdioHandle hMdioRegs);
638 
652 
668 uint32_t CSL_MDIO_phyLinkStatus(uint32_t baseAddr, uint32_t phyAddr);
669 
689  CSL_mdioHandle hMdioRegs,
690  Uint32 index,
691  Uint32 phyAddr
692 );
693 
709  CSL_mdioHandle hMdioRegs,
710  Uint32 index,
711  Uint32 phyAddr
712 );
713 
746  CSL_mdioHandle hMdioRegs
747 );
748 
781  CSL_mdioHandle hMdioRegs
782 );
783 
815  CSL_mdioHandle hMdioRegs
816 );
817 
849  CSL_mdioHandle hMdioRegs
850 );
851 
852 
867 uint32_t CSL_MDIO_phyRegRead2(CSL_mdioHandle hMdioRegs,
868  uint32_t userGroup,
869  uint32_t phyAddr,
870  uint32_t regNum,
871  uint16_t *pData);
872 
886 void CSL_MDIO_phyRegWrite2(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t regNum, uint16_t wrVal);
887 
900  uint32_t clause45EnableMask);
901 
915 
936  uint32_t userGroup,
937  uint32_t phyAddr,
938  uint32_t mmdNum,
939  uint32_t regAddr,
940  uint16_t wrVal);
941 
962  uint32_t userGroup,
963  uint32_t phyAddr,
964  uint32_t mmdNum,
965  uint32_t regAddr);
966 
986  uint32_t userGroup,
987  uint32_t phyAddr,
988  uint32_t regAddr,
989  uint16_t wrVal);
990 
1010  uint32_t userGroup,
1011  uint32_t phyAddr,
1012  uint32_t regAddr);
1013 
1031 int32_t CSL_MDIO_phyGetRegReadVal(CSL_mdioHandle hMdioRegs,
1032  uint32_t userGroup,
1033  uint16_t *pData);
1034 
1049  uint32_t userGroup);
1050 
1066 uint32_t CSL_MDIO_phyLinkStatus2(CSL_mdioHandle hMdioRegs, uint32_t phyAddr);
1067 
1085 
1102 
1116 
1133  Uint32 index);
1134 
1152 
1169 
1183 
1197 
1211 
1225 void CSL_MDIO_setPollIPG(CSL_mdioHandle hMdioRegs,
1226  uint8_t ipgVal);
1227 
1242 uint8_t CSL_MDIO_getPollIPG(CSL_mdioHandle hMdioRegs);
1243 
1261  uint32_t pollEnableMask);
1262 
1279 
1294 uint32_t CSL_MDIO_getPollEnableMask(CSL_mdioHandle hMdioRegs);
1295 
1299 #ifdef __cplusplus
1300 }
1301 #endif
1302 
1303 #endif /* CSL_MDIO_V5_H */
1304 
uint16_t index
Definition: tisci_rm_proxy.h:146
uint32_t CSL_MDIO_phyRegRead(uint32_t baseAddr, uint32_t phyAddr, uint32_t regNum, uint16_t *pData)
void CSL_MDIO_disableFaultDetect(CSL_mdioHandle hMdioRegs)
uint32_t CSL_MDIO_phyLinkStatus2(CSL_mdioHandle hMdioRegs, uint32_t phyAddr)
This API reads the link status of all PHY connected to this MDIO. The bit corresponding to the PHY ad...
uint32_t CSL_MDIO_isPhyLinked(CSL_mdioHandle hMdioRegs, uint32_t phyAddr)
void CSL_MDIO_setMdoLow(CSL_mdioHandle hMdioRegs)
This API sets MDIO IO pin to LOW state. Description This API sets the MDIO IO Pin to LOW when the M...
uint16_t CSL_MDIO_getClkDivVal(CSL_mdioHandle hMdioRegs)
uint32_t CSL_MDIO_isStateMachineEnabled(CSL_mdioHandle hMdioRegs)
uint32_t CSL_MDIO_phyLinkStatus(uint32_t baseAddr, uint32_t phyAddr)
This API reads the link status of all PHY connected to this MDIO. The bit corresponding to the PHY ad...
uint32_t CSL_MDIO_isStateChangeModeEnabled(CSL_mdioHandle hMdioRegs)
Checks if the State Change Mode is enabled or not.
void CSL_MDIO_disableStateChangeMode(CSL_mdioHandle hMdioRegs)
This function disables the MDIO State Change Mode.
uint32_t CSL_MDIO_isStatusChangeModeInterruptEnabled(CSL_mdioHandle hMdioRegs)
Check if the MDIO link interrupt (MDIO_LINKINT) is enabled.
void CSL_MDIO_setMdoOutputEnable(CSL_mdioHandle hMdioRegs)
This API sets MDIO IO pin as Output. Description This API sets MDIO IO pin state as output when the...
void CSL_MDIO_phyRegWrite(uint32_t baseAddr, uint32_t phyAddr, uint32_t regNum, uint16_t wrVal)
This API writes a PHY register using MDIO.
volatile CSL_MdioRegs * CSL_mdioHandle
Definition: csl_mdio.h:97
void CSL_MDIO_setMdoInputEnable(CSL_mdioHandle hMdioRegs)
This API sets MDIO IO pin as input. Description This API sets MDIO IO pin state as input when the M...
void CSL_MDIO_enableLinkStatusChangeInterrupt(CSL_mdioHandle hMdioRegs, Uint32 index, Uint32 phyAddr)
Enable MDIO link interrupt (MDIO_LINKINT) for PHY monitoring.
void CSL_MDIO_disableLinkStatusChangeInterrupt(CSL_mdioHandle hMdioRegs, Uint32 index, Uint32 phyAddr)
Disable MDIO link interrupt (MDIO_LINKINT) for PHY monitoring.
uint32_t CSL_MDIO_getClause45EnableMask(CSL_mdioHandle hMdioRegs)
Get Clause-45 enable mask. Each bit in the mask is associated with a PHY address, i....
void CSL_MDIO_enableStateChangeMode(CSL_mdioHandle hMdioRegs)
This function enables the MDIO State Change Mode.
Holds the MDIO peripheral's version info.
Definition: csl_mdio_def.h:77
void CSL_MDIO_enableManualMode(CSL_mdioHandle hMdioRegs)
This function enable the MDIO Manual Mode.
int32_t CSL_MDIO_phyInitiateRegReadC22(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t regAddr)
Initiate a non-blocking register read transaction with PHY using Clause-22 frame. The user should cal...
uint32_t CSL_MDIO_isUnmaskedLinkStatusChangeIntSet(CSL_mdioHandle hMdioRegs, uint32_t index)
void CSL_MDIO_clearUnmaskedLinkStatusChangeInt(CSL_mdioHandle hMdioRegs, uint32_t index)
uint32_t CSL_MDIO_phyRegRead2(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t regNum, uint16_t *pData)
int32_t CSL_MDIO_phyGetRegReadVal(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint16_t *pData)
Get the value read from a PHY register from a transaction previously initiated through either CSL_MDI...
void CSL_MDIO_setPollIPG(CSL_mdioHandle hMdioRegs, uint8_t ipgVal)
Set Polling Inter Packet Gap value.
void CSL_MDIO_enableStatusChangeModeInterrupt(CSL_mdioHandle hMdioRegs)
Enable MDIO link interrupt (MDIO_LINKINT)
void CSL_MDIO_clearPollEnableMask(CSL_mdioHandle hMdioRegs)
Clear poll enable mask.
uint8_t CSL_MDIO_getPollIPG(CSL_mdioHandle hMdioRegs)
Get Polling Inter Packet Gap value.
void CSL_MDIO_setMdclkHigh(CSL_mdioHandle hMdioRegs)
This API sets MDIO CLK pin to HIGH state. Description This API sets the MDIO CLK PIn to HIGH when t...
void CSL_MDIO_setMdoHigh(CSL_mdioHandle hMdioRegs)
This API sets MDIO IO pin to HIGH state. Description This API sets the MDIO IO Pin to HIGH when the...
void CSL_MDIO_getVersionInfo(CSL_mdioHandle hMdioRegs, CSL_MDIO_VERSION *mdioVersionInfo)
void CSL_MDIO_disableManualMode(CSL_mdioHandle hMdioRegs)
This function disables the MDIO Manual Mode.
void CSL_MDIO_enableStateMachine(CSL_mdioHandle hMdioRegs)
uint32_t CSL_MDIO_isPhyRegAccessComplete(CSL_mdioHandle hMdioRegs, uint32_t userGroup)
Check if there is a transaction going on in MDIO.
void CSL_MDIO_setPollEnableMask(CSL_mdioHandle hMdioRegs, uint32_t pollEnableMask)
Set poll enable mask.
uint32_t CSL_MDIO_getPollEnableMask(CSL_mdioHandle hMdioRegs)
Get poll enable mask.
int32_t CSL_MDIO_phyInitiateRegReadC45(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t mmdNum, uint32_t regAddr)
Initiate a non-blocking register read transaction with PHY using Clause-45 frame. The user should cal...
void CSL_MDIO_enablePreamble(CSL_mdioHandle hMdioRegs)
void CSL_MDIO_disableStatusChangeModeInterrupt(CSL_mdioHandle hMdioRegs)
Disable MDIO link interrupt (MDIO_LINKINT)
int32_t CSL_MDIO_phyRegInitiateWriteC22(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t regAddr, uint16_t wrVal)
Initiate a non-blocking write transaction with PHY using Clause-22 frame. The user should call CSL_MD...
void CSL_MDIO_phyRegWrite2(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t regNum, uint16_t wrVal)
This API writes a PHY register using MDIO.
void CSL_MDIO_disablePreamble(CSL_mdioHandle hMdioRegs)
int32_t CSL_MDIO_phyInitiateRegWriteC45(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t mmdNum, uint32_t regAddr, uint16_t wrVal)
Initiate a non-blocking write transaction with PHY using Clause-45 frame. The user should call CSL_MD...
void CSL_MDIO_enableFaultDetect(CSL_mdioHandle hMdioRegs)
Uint32 CSL_MDIO_getLinkStatusChangePhyAddr(CSL_mdioHandle hMdioRegs, Uint32 index)
Get the PHY address being monitored.
uint32_t CSL_MDIO_readMdi(CSL_mdioHandle hMdioRegs)
This API reads MDIO IO pin state. Description This API reads MDIO IO Pin state when the MDIO is set...
void CSL_MDIO_disableStateMachine(CSL_mdioHandle hMdioRegs)
uint32_t CSL_MDIO_isPhyAlive(CSL_mdioHandle hMdioRegs, uint32_t phyAddr)
void CSL_MDIO_setClkDivVal(CSL_mdioHandle hMdioRegs, uint16_t clkDivVal)
void CSL_MDIO_setClause45EnableMask(CSL_mdioHandle hMdioRegs, uint32_t clause45EnableMask)
Set Clause-45 enable mask. Each bit in the mask is associated with a PHY address, i....
void CSL_MDIO_setMdclkLow(CSL_mdioHandle hMdioRegs)
This API sets MDIO CLK pin to LOW state. Description This API sets the MDIO CLK Pin to LOW when the...