Eth_Cfg.h

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/*******************************************************************************
    Project         : J721E
    Date            : 2025-04-18 12:22:03
    SW Ver          : 11.0.0
    Module Rele Ver : AUTOSAR 4.3.1 0

    This file is generated by EB Tresos
    Do not modify this file,otherwise the software may behave in unexpected way.
*******************************************************************************/

#ifndef ETH_CFG_H_
#define ETH_CFG_H_

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include "Os.h"
#include "Eth_LL_Types.h"
#include "Udma_Types.h"
#include "Eth_Rpc.h"

#ifdef __cplusplus
extern "C" {
#endif

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
#define ETH_VERSION_INFO_API                       (STD_ON)

#define ETH_GLOBALTIMESUPPORT_API                  (STD_ON)

#define ETH_DEV_ERROR_DETECT                       (STD_ON)

#define ETH_GET_COUNTER_VALUES_API                 (STD_ON)

#define ETH_GET_RX_STATS_API                       (STD_ON)

#define ETH_GET_TX_STATS_API                       (STD_ON)

#define ETH_GET_TX_ERROR_COUNTERSVALUES_API        (STD_ON)

#define ETH_ZERO_COPY_API                          (STD_OFF)

#define ETH_HEADER_ACCESS_API                      (STD_OFF)

#define ETH_TRAFFIC_SHAPING_API                    (STD_OFF)

#define ETH_GET_COUNTER_STATE_API                  (STD_OFF)


#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP      (STD_OFF)

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4      (STD_OFF)

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP       (STD_OFF)

#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP       (STD_OFF)

#define ETH_REGISTER_READBACK_API                  (STD_ON)

#define ETH_TIMESTAMP_VIA_CPTS_EVENT_FIFO                  (STD_ON)

#define ETH_PHY_FAULT_DETECTION_ENABLE                  (STD_ON)

#define ETH_ENABLE_MII_API                         (STD_ON)

#define ETH_UPDATE_PHYS_ADDR_FILTER_API            (STD_ON)

#define ETH_ENABLE_IRQ_PACING                  (STD_OFF)

#define ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API       (STD_OFF)

#define ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API     (STD_OFF)

#define ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API   (STD_OFF)

#define ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API         (STD_OFF)

#define ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API       (STD_OFF)

#define ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API    (STD_OFF)

#define ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF)

#define ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API       (STD_OFF)

#define ETH_VIRTUALMAC_DEL_MACADDR_API             (STD_OFF)

#define ETH_VIRTUALMAC_ADD_VLAN_API                (STD_OFF)

#define ETH_VIRTUALMAC_DEL_VLAN_API                (STD_OFF)


#define ETH_ETHIF_CBK_HEADER                       "EthIf_Cbk.h"

#define ETH_ISR_TYPE                               (ETH_ISR_CAT2)

#define ETH_OS_COUNTER_ID                          ((CounterType)OsCounter_0)

#define ETH_OS_COUNTER_FREQ                        (1000000000U)

#define ETH_INVALID_RING_ID                        (0xFFFFU)

#define ETH_INVALID_EVENT_ID                       (0xFFFFU)

#define ETH_INVALID_CHAN_ID                        (0xFFFFU)

#define ETH_INVALID_FLOW_ID                        (0xFFFFU)

#define ETH_INVALID_IRQ_ID                         (0xFFFFU)

#define ETH_DEM_NO_EVENT                           (0xFFFFU)

#define ETH_VIRTUALMAC_SUPPORT                     (STD_OFF)

#define ETH_VIRTUALMAC_FWINFO_TIMEOUT              (0U)


#define EthConf_EthCtrlConfig_EthConfig_0                                  (0U)
#define ETH_CTRL_ID_0                                                      (0U)
/* @} */

#define ETH_PRE_COMPILE_VARIANT                                            (STD_ON)
#define ETH_LINK_TIME_VARIANT                                              (STD_OFF)
#define ETH_POST_BUILD_VARIANT                                             (STD_OFF)
/* @} */

#define ETH_CTRL_ID_MAX                                                    (1U)


#define NOP1    asm (" NOP ")
#define NOP5    NOP1;   NOP1; NOP1; NOP1; NOP1
#define NOP10   NOP5;   NOP5
#define NOP20   NOP10;  NOP10
#define NOP30   NOP20;  NOP10
#define NOP40   NOP30;  NOP10
#define NOP50   NOP40;  NOP10
#define NOP100  NOP50;  NOP50
#define NOP200  NOP100; NOP100
#define NOP300  NOP200; NOP100
#define NOP400  NOP300; NOP100
#define NOP500  NOP400; NOP100
/* @} */

#define ETH_DMA_IR_SUPPORT                                                 (STD_ON)
#define ETH_DMA_CQ_RING_SUPPORT                                            (STD_ON)
#define ETH_DMA_TEARDOWN_SUPPORT                                           (STD_ON)
#define ETH_DMA_PROXY_SUPPORT                                              (STD_ON)
#define ETH_DMA_RX_CH_SPERATE                                              (STD_OFF)
/* @} */

#define UDMA_DEVICE_ID_RING                                                (235U)
#define UDMA_DEVICE_ID_UDMA                                                (236U)
#define UDMA_DEVICE_ID_PSIL                                                (232U)
#define UDMA_DEVICE_ID_IA                                                  (233U)
#define UDMA_DEVICE_ID_IR                                                  (237U)
#define UDMA_DEVICE_ID_CORE                                                (250U)
#define UDMA_DEVICE_ID_PROXY                                               (234U)
/* @} */

#define UDMA_TX_CHANNEL_PEER_OFFSET                                        (0xf000U)
#define UDMA_RX_CHANNEL_PEER_OFFSET                                        (0x7000U)
#define UDMA_SOURCE_THREAD_OFFSET                                          (0x6000U)
#define UDMA_DEST_THREAD_OFFSET                                            (0xe000U)
/* @} */

#define ETH_DMA_TX_BASE_REG                                                (0x2aa00000U)
#define ETH_DMA_RX_BASE_REG                                                (0x2a800000U)
#define ETH_DMA_RINGRT_BASE                                                (0x2b800000U)
#define ETH_DMA_RINGCFG_BASE                                               (0x28440000U)
#define ETH_DMA_INTAGGR_INTR_BASE                                          (0x2a700000U)
/* @} */

#define ETH_DMA_TXCRT_CHAN_CTL(CHAN)                                       (0x00000000U + ((CHAN) * 0x1000U))
#define ETH_DMA_TXCRT_CHAN_PEER8(CHAN)                                     (0x00000220U + ((CHAN) * 0x1000U))
#define ETH_DMA_RXCRT_CHAN_CTL(CHAN)                                       (0x00000000U + ((CHAN) * 0x1000U))
#define ETH_DMA_RXCRT_CHAN_PEER8(CHAN)                                     (0x00000220U + ((CHAN) * 0x1000U))

#define ETH_DMA_RINGRT_RING_FDB(RING)                                      (0x00000010U + ((RING) * 0x1000U))
#define ETH_DMA_RINGRT_RING_FOCC(RING)                                     (0x00000018U + ((RING) * 0x1000U))
#define ETH_DMA_RINGRT_RING_RDB(RING)                                      (0x00000010U + ((RING) * 0x1000U))
#define ETH_DMA_RINGRT_RING_ROCC(RING)                                     (0x00000018U + ((RING) * 0x1000U))
#define ETH_DMA_RINGRT_RING_HWOCC(RING)                                    (0x00000020U + ((RING) * 0x1000U))
#define ETH_DMA_RINGCFG_RING_SIZE(RING)                                    (0x00000048U + ((RING) * 0x100U))

#define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET(VINT)                         (ETH_DMA_INTAGGR_INTR_BASE + 0x00000000U + ((VINT) * 0x1000U))
#define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR(VINT)                       (ETH_DMA_INTAGGR_INTR_BASE + 0x00000008U + ((VINT) * 0x1000U))
#define ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET(VINT)                         (ETH_DMA_INTAGGR_INTR_BASE + 0x00000010U + ((VINT) * 0x1000U))
#define ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR(VINT)                       (ETH_DMA_INTAGGR_INTR_BASE + 0x00000018U + ((VINT) * 0x1000U))
#define ETH_DMA_INTAGGR_INTR_VINT_STATUSM(VINT)                            (ETH_DMA_INTAGGR_INTR_BASE + 0x00000020U + ((VINT) * 0x1000U))

#define Eth_GetRingFDBReg(RingNum)                                         (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FDB((RingNum)))
#define Eth_GetRingFOCCReg(RingNum)                                        (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FOCC((RingNum)))
#define Eth_GetRingRDBReg(RingNum)                                         (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_RDB((RingNum)))
#define Eth_GetRingROCCReg(RingNum)                                        (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_ROCC((RingNum)))
#define Eth_GetRingHWOCCReg(RingNum)                                       (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_HWOCC((RingNum)))
#define Eth_GetRingSizeReg(RingNum)                                        (ETH_DMA_RINGCFG_BASE + ETH_DMA_RINGCFG_RING_SIZE((RingNum)))
#define ETH_CSL_PROXY0_TARGET0_DATA_BASE                                   (0x2a500000U)
#define ETH_CSL_PROXY_TARGET0_PROXY_CTL(PROXY)                             (ETH_CSL_PROXY0_TARGET0_DATA_BASE + 0x00000000U + ((PROXY)*0x1000U))
#define ETH_CSL_PROXY_TARGET0_PROXY_DATA_FIELD(PROXY)                      (ETH_CSL_PROXY0_TARGET0_DATA_BASE + 0x00000200U + ((PROXY)*0x1000U))
/* @} */

#define UDMA_WAIT_TEARDOWN_COUNTER                                         (10000u)


#define ETH_DEM_EVENT_SUPPORT                                              (STD_OFF)

#define ETH_RX_MTU_HOST_PORT_LENGTH                                        (1522U)



#define Eth_Cpsw_GetPhyMacRegAddr()                                        ( 0x40f00200U )
#define Eth_Cpsw_GetAleRegAddr()                                           ( 0x4603e000U )
#define Eth_Cpsw_GetCptsRegAddr()                                          ( 0x4603d000U )
#define Eth_Cpsw_GetMdioRegAddr()                                          ( 0x46000f00U )
#define Eth_Cpsw_GetCtrlRegAddr()                                          ( 0x46020000U )
#define Eth_Cpsw_GetCppiClockFreq()                                        ( 333333333U )

#define Eth_Cpsw_GetCptsRefClockFreq()                                     ( 1U )
#define Eth_Cpsw_GetMdioBusClockFreq()                                     ( 2200000U )
#define Eth_Cpsw_GetMdioOpMode()                                           ( ETH_MDIO_OPMODE_MANUAL )
#define Eth_Cpsw_GetMdioEnableInterrupt()                                  ( TRUE )
/* @} */

#define Eth_GetDem_E_HARDWARE_ERROR(CtrlIndex)                             ( ETH_DEM_NO_EVENT )
#define Eth_GetDem_E_LATECOLLISION(CtrlIndex)                              ( ETH_DEM_NO_EVENT )
#define Eth_GetDem_E_MULTIPLECOLLISION(CtrlIndex)                          ( ETH_DEM_NO_EVENT )
#define Eth_GetDem_E_SINGLECOLLISION(CtrlIndex)                            ( ETH_DEM_NO_EVENT )
#define Eth_GetDem_E_ALIGNMENT(CtrlIndex)                                  ( ETH_DEM_NO_EVENT )
#define Eth_GetDem_E_OVERSIZEFRAME(CtrlIndex)                              ( ETH_DEM_NO_EVENT )
#define Eth_GetDem_E_UNDERSIZEFRAME(CtrlIndex)                             ( ETH_DEM_NO_EVENT )
#define Eth_GetDem_E_CRC(CtrlIndex)                                        ( ETH_DEM_NO_EVENT )
#define Eth_GetDem_E_RX_FRAMES_LOST(CtrlIndex)                             ( ETH_DEM_NO_EVENT )
#define Eth_GetDem_E_ACCESS(CtrlIndex)                                     ( ETH_DEM_NO_EVENT )
#define Eth_GetDem_E_TX_INTERNAL(CtrlIndex)                                ( ETH_DEM_NO_EVENT )
/* @} */

#define Eth_IsVirtualMacModeEnable(CtrlIndex)                              ( FALSE )
#define Eth_GetTxChannelThreadOffset(CtrlIndex)                            ( 0xf000U )
#define Eth_VirtMacGetEthFwRpcComChannelId(CtrlIndex)                      ( 0xFFFFU )
#define Eth_VirtMacGetEthPollRecvMsgInEthMain(CtrlIndex)                   ( FALSE )
#define Eth_VirtMacGetRpcCmdCompleteFuncPtr(CtrlIndex)                     ( (Eth_RpcCmdComplete)NULL_PTR )
#define Eth_VirtMacGetFwRegisterFuncPtr(CtrlIndex)                         ( (Eth_RpcFwRegistered)NULL_PTR )
#define Eth_VirtMacGetRemoteVirtPort(CtrlIndex)                            ( ETHREMOTECFG_SWITCH_PORT_1 )

#define Eth_VirtMacGetDmaTxChannelPairAll(CtrlIdx)                         ( (EthVirtMacDmaTxChannelPair)NULL_PTR )
#define Eth_VirtMacGetDmaTxChannelUnpairAll(CtrlIdx)                       ( (EthVirtMacDmaTxChannelUnpair)NULL_PTR )
#define Eth_VirtMacGetDmaFlowCfgAll(CtrlIdx)                               ( (EthVirtMacDmaFLowCfg)NULL_PTR )
#define Eth_VirtMacGetDmaFlowResetAll(CtrlIdx)                             ( (EthVirtMacDmaFLowReset)NULL_PTR )

#define Eth_GetTxEnableInterrupt(CtrlIndex)                                ( TRUE )
#define Eth_GetRxEnableInterrupt(CtrlIndex)                                ( TRUE )
#define Eth_GetEnetType(CtrlIndex)                                         ( ETH_ENETTYPE_CPSW2G )
#define Eth_GetMacPortNum(CtrlIndex)                                       ( ETH_PORT_MAC_PORT_1 )
#define Eth_GetMacAddressHigh(CtrlIndex)                                   ( 0xaabbccddU )
#define Eth_GetMacAddressLow(CtrlIndex)                                    ( 0xeeffU )
#define Eth_UseDefaultMacAddress(CtrlIndex)                                ( TRUE )
#define Eth_GetMiiConnectionType(CtrlIndex)                                ( ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND )
#define Eth_GetLoopBackMode(CtrlIndex)                                     ( FALSE )
#define Eth_GetHardwareLoopTimeout(CtrlIndex)                              ( 32000U )
#define Eth_IsPacketMemCacheable(CtrlIndex)                                ( TRUE )
#define Eth_IsRingMemCacheable(CtrlIndex)                                  ( TRUE )
#define Eth_IsDescMemCacheable(CtrlIndex)                                  ( TRUE )

#define Eth_GetRxMtuLength(CtrlIndex)                                      ( 1522U )
#define Eth_GetTxChanStartNum(CtrlIndex)                                   ( 30U )
#define Eth_GetRxChanStartNum(CtrlIndex)                                   ( 30U )
#define Eth_GetEgressFifoTotalNum(CtrlIndex)                               ( 1U )
#define Eth_GetIngressFifoTotalNum(CtrlIndex)                              ( 1U )
#define Eth_GetRingTotalNum(CtrlIndex)                                     ( 6U )
#define Eth_GetTxChanTotalNum(CtrlIndex)                                   ( 1U )
#define Eth_GetRxChanTotalNum(CtrlIndex)                                   ( 1U )
#define Eth_GetFlowTotalNumber(CtrlIndex)                                  ( 1U )
#define Eth_GetEventTotalNum(CtrlIndex)                                    ( 2U )
#define Eth_GetRingEventTotalNum(CtrlIndex)                                ( 2U )
#define Eth_GetTxDmaThresholdNum(CtrlIndex)                                ( 1U )
#define Eth_GetRxDmaThresholdNum(CtrlIndex)                                ( 1U )

#define Eth_GetEgressFifoPacketNum(CtrlIndex, FifoIdx)                     ( 16U )
#define Eth_GetEgressFifoPacketSize(CtrlIndex, FifoIdx)                    ( 1522U )

#define Eth_GetIngressFifoPacketNum(CtrlIndex, FifoIdx)                    ( 16U  )
#define Eth_GetIngressFifoPacketSize(CtrlIndex, FifoIdx)                   ( 1522U )

#define Eth_GetEgressFifoPriorityAsignment(CtrlIndex, Prio)                ( 0U )
#define Eth_GetIngressFifoPriorirtyAsignment(CtrlIndex, Prio)              ( 0U )

#define Eth_GetEgressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx)          (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)] )
#define Eth_GetEgressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx)  (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)].bufferInfo )
#define Eth_GetEgressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx)    (&Eth_Ctrl_0_Egress_BufferMem_0[(DescIdx) * 1536U] )
#define Eth_GetEgressFifoQueueAddress(CtrlIndex, FifoIdx)                  ( Eth_Ctrl_0_Egress_Queue_0 )
#define Eth_GetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx)        ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] )
#define Eth_SetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val)   ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] = Val )

#define Eth_GetIngressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx)         (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)] )
#define Eth_GetIngressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)].bufferInfo )
#define Eth_GetIngressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx)   (&Eth_Ctrl_0_Ingress_BufferMem_0[(DescIdx) * 1536U] )
#define Eth_GetIngressFifoQueueAddress(CtrlIndex, FifoIdx)                 ( Eth_Ctrl_0_Ingress_Queue_0 )
#define Eth_GetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx)       ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] )
#define Eth_SetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val)  ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] = Val )

#define Eth_GetEgressFifoCqIdx(CtrlIndex, FifoIdx)                         ( 0U )
#define Eth_GetEgressFifoFqIdx(CtrlIndex, FifoIdx)                         ( 2U )
#define Eth_GetIngressFifoCqIdx(CtrlIndex, FifoIdx)                        ( 1U )
#define Eth_GetIngressFifoFqIdx(CtrlIndex, FifoIdx)                        ( 3U )

#define Eth_GetTxChanId(CtrlIndex, ChIdx)                                  ( 30U )
#define Eth_GetTxChanTdCqRingIdx(CtrlIndex, ChIdx)                         ( 4U )
#define Eth_GetTxChanDepth(CtrlIndex, ChIdx)                               ( 128U )

#define Eth_GetRxChanId(CtrlIndex, ChIdx)                                  ( 30U )
#define Eth_GetRxChanTdCqRingIdx(CtrlIndex, ChIdx)                         ( 5U )
#define Eth_GetRxChanFlowTotalNum(CtrlIndex, ChIdx)                        ( 1U )
#define Eth_GetRxChanFlowStartNum(CtrlIndex, ChIdx)                        ( 60U )

#define Eth_GetFlowId(CtrlIndex, FlowIdx)                                  ( 60U )
#define Eth_GetFlowCqRingIdx(CtrlIndex, FlowIdx)                           ( 1U )
#define Eth_GetFlowFqRingIdx(CtrlIndex, FlowIdx)                           ( 3U )

#define Eth_GetDynRingElemAddress(CtrlIndex, RingIdx)                      ( &Eth_RingDyn_Ctrl_0[(RingIdx)] )

#define Eth_GetRingHwId(CtrlIndex, RingIdx)                                ( Eth_Udma_RingCfg_0[(RingIdx)].hwId )
#define Eth_GetRingTotalElemNum(CtrlIndex, RingIdx)                        ( Eth_Udma_RingCfg_0[(RingIdx)].size )
#define Eth_GetRingPriority(CtrlIndex, RingIdx)                            ( Eth_Udma_RingCfg_0[(RingIdx)].priority )
#define Eth_GetRingMemBaseAddress(CtrlIndex, RingIdx)                      ( Eth_Udma_RingCfg_0[(RingIdx)].memPtr )

#define Eth_GetRingEventRingIdx(CtrlIndex, RingEvtIdx)                     ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].ringIdx )
#define Eth_GetRingEventGlobalEventNum(CtrlIndex, RingEvtIdx)              ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].globalEvent )
#define Eth_GetRingEventVirtBitNum(CtrlIndex, RingEvtIdx)                  ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].virtBitNum )
#define Eth_GetRingEventEventIdx(CtrlIndex, RingEvtIdx)                    ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].eventIdx )
#define Eth_GetRingEventSrcOffsetNum(CtrlIndex, RingEvtIdx)                ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].srcOffset )

#define Eth_GetEventCoreIntrNum(CtrlIndex, EvtIdx)                         ( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum )
#define Eth_GetEventVirtIntrNum(CtrlIndex, EvtIdx)                         ( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum )
#define Eth_GetEventIrIntrNum(CtrlIndex, EvtIdx)                           ( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum )
#define Eth_GetTxEventCoreIntrNum(CtrlIndex)                               ( 80U )
#define Eth_GetRxEventCoreIntrNum(CtrlIndex)                               ( 81U )

#define Eth_GetHwTimerTotalNum(CtrlIndex)                                  ( 0U )
#define Eth_GetHwTimerId(CtrlIndex, Index)                                 ( 0xFFU )
#define Eth_GetHwTimerCounter(CtrlIndex, Index)                            ( 0xFFU )
#define Eth_GetHwTimerBaseAddr(CtrlIndex, Index)                           ( 0xFFFFFFFFU )

#define Eth_GetHwTimerDynRunningState(CtrlIndex, Index)                    ( FALSE )
#define Eth_SetHwTimerDynRunningState(CtrlIndex, Index, Val)               ( (void)(CtrlIndex) )

#define Eth_GetRxIrqPacingEnable(CtrlIndex)                                ( FALSE )
#define Eth_GetTxIrqPacingEnable(CtrlIndex)                                ( FALSE )

#define Eth_GetRxHwTimerIdx(CtrlIndex)                                     ( 255U )
#define Eth_GetTxHwTimerIdx(CtrlIndex)                                     ( 255U )
#define Eth_GetIrqPacingEnable(CtrlIndex)                                  ( (Eth_GetTxIrqPacingEnable(CtrlIndex) == TRUE) || (Eth_GetRxIrqPacingEnable(CtrlIndex) == TRUE) )

#define Eth_GetProxyTotalNum(CtrlIndex)                                    ( 1U )
#define Eth_GetProxyThreadNum(CtrlIndex, ProxyIdx)                         ( 9U )
#define Eth_GetProxyTargetRingNum(CtrlIndex, ProxyIdx)                     ( 0U )
#define Eth_GetRingProxyIdx(CtrlIndex, RingIdx)                            ( Eth_Udma_RingCfg_0[(RingIdx)].proxyIdx )
#define Eth_GetRingMode(CtrlIndex, RingIdx)                                ( Eth_Udma_RingCfg_0[(RingIdx)].ringMode )

#define Eth_GetDmaRingCfg(CtrlIdx)                                         ( (Eth_DmaRingCfg)&AppUtils_EthRingCfg )

#define Eth_GetTxChannelCtlRegAddress(ChanId)                              (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_CTL((ChanId)))
#define Eth_GetTxChannelPeer8RegAddress(ChanId)                            (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_PEER8((ChanId)))
#define Eth_GetRxChannelCtlRegAddress(ChanId)                              (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_CTL((ChanId)))
#define Eth_GetRxChannelPeer8RegAddress(ChanId)                            (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_PEER8((ChanId)))

/* @} */

/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */

typedef void (*Eth_RpcCmdComplete)(uint8 CtrlIdx,
                                   uint8 sid,
                                   sint32 status);

typedef void (*Eth_RpcFwRegistered)(uint8 CtrlIdx);

typedef Std_ReturnType (*Eth_DmaRingCfg)(uint8 ctrlIdx, uint8 ringIdx);

typedef void (*Eth_MdioDelayNsecFunc)(void);

typedef Std_ReturnType (*EthVirtMacDmaTxChannelPair)(uint8 ctrlIdx);

typedef Std_ReturnType (*EthVirtMacDmaTxChannelUnPair)(uint8 ctrlIdx);

typedef Std_ReturnType (*EthVirtMacDmaFLowCfg)(uint8 ctrlIdx);

typedef Std_ReturnType (*EthVirtMacDmaFLowReset)(uint8 ctrlIdx);

typedef enum
{
    ETH_PORT_HOST_PORT      = 0x00U,
    ETH_MAC_PORT_FIRST      = 0x01U,
    ETH_PORT_MAC_PORT_1     = 0x01U,
    ETH_PORT_MAC_PORT_2     = 0x02U,
    ETH_PORT_MAC_PORT_3     = 0x03U,
    ETH_PORT_MAC_PORT_4     = 0x04U,
    ETH_PORT_MAC_PORT_5     = 0x05U,
    ETH_PORT_MAC_PORT_6     = 0x06U,
    ETH_PORT_MAC_PORT_7     = 0x07U,
    ETH_PORT_MAC_PORT_8     = 0x08U,
    ETH_PORT_MAC_PORT_LAST  = ETH_PORT_MAC_PORT_8,
} Eth_PortType;

typedef enum
{
    ETH_MAC_CONN_TYPE_RMII_10               = 0x01U,
    ETH_MAC_CONN_TYPE_RMII_100              = 0x02U,
    ETH_MAC_CONN_TYPE_RGMII_FORCE_100_HALF  = 0x03U,
    ETH_MAC_CONN_TYPE_RGMII_FORCE_100_FULL  = 0x04U,
    ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL = 0x05U,
    ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND   = 0x06U,
} Eth_MacConnectionType;

typedef enum
{
    ETH_ENETTYPE_CPSW2G     = 0x00U,
    ETH_ENETTYPE_CPSW9G     = 0x01U,
    ETH_ENETTYPE_CPSW5G     = 0x02U,
    ETH_ENETTYPE_CPSW3G     = 0x03U,
    ETH_ENETTYPE_CPSWLAST,
} Eth_EnetType;

typedef enum
{
    ETH_MDIO_OPMODE_NORMAL    = 0x00U,
    ETH_MDIO_OPMODE_MANUAL    = 0x01U,
} Eth_MdioOperModeType;

typedef struct Eth_CpswConfigType_s
{
    uint32 phyMacAddr;
    uint32 aleAddr;
    uint32 cptsAddr;
    uint32 mdioAddr;
    uint32 ctrlAddr;
    uint32 cppiClockFreqHz;
    boolean enableMdioIrq;
    uint32 mdioBusFreqHz;
    Eth_MdioOperModeType mdioOpMode;
    uint32 cptsRefClockFreq;
} Eth_CpswConfigType;

typedef struct Eth_Udma_RingCfgType_s
{
    uint64 *memPtr;
    uint32  hwId;
    uint32  size;
    uint32  priority;
    uint32  proxyIdx;
    uint32  ringMode;
} Eth_Udma_RingCfgType;

typedef struct Eth_Udma_ProxyCfgType_s
{
    uint32  proxyId;
    uint32  targetNumRingId;
} Eth_Udma_ProxyCfgType;

typedef struct Eth_Udma_EventCfgType_s
{
    uint32  coreIntrNum;
    uint32  virtIntrNum;
    uint32  IrIntrNum;
} Eth_Udma_EventCfgType;

typedef struct Eth_Udma_RingEventCfgType_s
{
    uint8  ringIdx;
    uint8  eventIdx;
    uint8  virtBitNum;
    uint32 globalEvent;
    uint32 srcOffset;
} Eth_Udma_RingEventCfgType;

typedef struct Eth_FifoRingMapCfgType_s
{
    uint8 cqRingIdx;
    uint8 fqRingIdx;
} Eth_FifoRingMapCfgType;

typedef struct Eth_ChannelCfgType_s
{
    uint8 tdCqRingIdx;
    uint16 chId;
} Eth_ChannelCfgType;

typedef struct Eth_FlowCfgType_s
{
    uint8  cqRingIdx;
    uint8  fqRingIdx;
    uint16 flowId;
} Eth_FlowCfgType;

typedef struct Eth_ChannelFlowCfgType_s
{
    uint8            flowNum;
    uint16           startFlowId;
} Eth_ChannelFlowCfgType;

typedef struct Eth_FifoHandleType_s
{
    uint8         *fifoBufferPtr;
    Eth_DescType  *descPtr;
    Eth_QueueType *queuePtr;
    uint8         *bufferState;
    uint16        fifoNum;
    uint16        elemSize;
    uint16        pktSize;
    uint32        totalSize;
} Eth_FifoHandleType;

typedef struct Eth_Udma_CfgType_s
{
    Eth_Udma_EventCfgType     *eventCfgPtr;
    Eth_Udma_RingCfgType      *ringCfgPtr;
    Eth_Udma_RingDynType      *ringDynPtr;
    Eth_Udma_RingEventCfgType *ringEvenCfgPtr;
    Eth_FifoHandleType        *egressFifoCfgPtr;
    Eth_FifoHandleType        *ingressFifoCfgPtr;
    Eth_FifoRingMapCfgType    *egressFifoRingMapCfgPtr;
    Eth_FifoRingMapCfgType    *ingressFifoRingMapCfgPtr;
    uint8                     *egressFifoPrioAssignCfgPtr;
    uint8                     *ingressFifoPrioAssignCfgPtr;
    Eth_ChannelCfgType        *txChanCfgPtr;
    Eth_ChannelCfgType        *rxChanCfgPtr;
    Eth_ChannelFlowCfgType    *rxChanFlowCfgPtr;
    Eth_FlowCfgType    *flowCfgPtr;
    Eth_Udma_ProxyCfgType     *proxyCfgPtr;
    uint32 txChDmaBaseAddr;
    uint32 rxChDmaBaseAddr;
    uint16 startTxNum;
    uint16 startRxNum;
    uint8 totalEventNum;
    uint8 totalRingNum;
    uint8 totalRingEventNum;
    uint8 txThresholdNum;
    uint8 rxThresholdNum;
    uint8 totalEgressFifoNum;
    uint8 totalIngressFifoNum;
    uint8 totalTxChanNum;
    uint8 totalRxChanNum;
    uint8 totalFlowNum;
    uint16 totalProxyNum;
    uint16 txCoreIrq;
    uint16 rxCoreIrq;
    uint16 rxMtuLength;
    Eth_DmaRingCfg EthDmaRingCfgOps;
} Eth_Udma_CfgType;

typedef struct Eth_VirtualMacConfigType_s
{
    uint32 ethfwRpcComChId;
    EthRemoteCfg_VirtPort remoteVirtPort;
    Eth_RpcCmdComplete rpcCmdComplete;
    boolean pollRecvMsgInEthMain;
    Eth_RpcFwRegistered fwRegisteredCb;
    EthVirtMacDmaTxChannelPair txChannelPair;
    EthVirtMacDmaTxChannelUnPair txChannelUnPair;
    EthVirtMacDmaFLowCfg dmaFLowCfg;
    EthVirtMacDmaFLowReset dmaFLowReset;
} Eth_VirtualMacConfigType;

typedef struct Eth_HwTimerConfigType_s
{
    uint8  hwTimerId;
    uint32 hwTimerCounter;
    uint32 hwTimerBaseAddr;
} Eth_HwTimerConfigType;

typedef struct Eth_ControlerConfigType_s
{
    uint32 ctrlIdx;
    Eth_EnetType enetType;
    Eth_PortType macPort;
    uint32 macAddrHigh;
    uint32 macAddrLow;
    boolean useDefaultMac;
    Eth_MacConnectionType connType;
    boolean loopback;
    uint32 hwLoopTimeout;
    boolean enableTxIrq;
    boolean enableRxIrq;
    boolean isPacketMemCacheable;
    boolean isRingMemCacheable;
    boolean isDescMemCacheable;
    boolean enableVirtualMac;
    uint16 demEventNum;
    boolean enableRxIrqPacing;
    boolean enableTxIrqPacing;
    uint8 totalHwTimerNum;
    uint8 rxHwTimerIdx;
    uint8 txHwTimerIdx;
    Eth_VirtualMacConfigType *virtualMacCfg;
    uint16 *demEventCfg;
    Eth_CpswConfigType *cpswCfg;
    Eth_Udma_CfgType *dmaCfgPtr;
    Eth_HwTimerConfigType *hwTimerCfgPtr;
    boolean *hwTimerDynPtr;
    Eth_MdioDelayNsecFunc mdioWriteLowDelayNsec;
    Eth_MdioDelayNsecFunc mdioWriteHighDelayNsec;
    Eth_MdioDelayNsecFunc mdioReadLowDelayNsec;
    Eth_MdioDelayNsecFunc mdioReadHighDelayNsec;
} Eth_ControlerConfigType;

typedef struct Eth_ConfigType_s
{
    Eth_ControlerConfigType *pControler[ETH_CTRL_ID_MAX];
} Eth_ConfigType;

/* ========================================================================== */
/*                         Generate Configuration                             */
/* ========================================================================== */

#define  ETH_START_SEC_CONST_UNSPECIFIED
#include "Eth_MemMap.h"

extern CONST(Eth_Udma_RingCfgType, ETH_VAR_NO_INIT) Eth_Udma_RingCfg_0[6U];
extern CONST(Eth_Udma_EventCfgType, ETH_VAR_NO_INIT) Eth_EventCfg_Ctrl_0[2U];
extern CONST(Eth_Udma_RingEventCfgType, ETH_VAR_NO_INIT) Eth_RingEventCfg_Ctrl_0[2U];


#define  ETH_STOP_SEC_CONST_UNSPECIFIED
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

extern VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[24576U];
extern VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_Descriptor_0[16U];

extern VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Ingress_BufferMem_0[24576U];
extern VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Ingress_Descriptor_0[16U];

#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

#define ETH_START_SEC_VAR_NO_INIT_8
#include "Eth_MemMap.h"

extern VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_BufferState_0[16U];
extern VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Ingress_BufferState_0[16U];

#define ETH_STOP_SEC_VAR_NO_INIT_8
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

extern VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_Queue_0[1U];
extern VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Ingress_Queue_0[1U];

extern VAR(Eth_Udma_RingDynType, ETH_VAR_NO_INIT) Eth_RingDyn_Ctrl_0[6U];
#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

/* ========================================================================== */
/*                          External Function Prototype                       */
/* ========================================================================== */
#define ETH_START_SEC_CODE
#include "Eth_MemMap.h"



extern Std_ReturnType AppUtils_EthRingCfg(uint8 ctrlIdx, uint8 Id);

#define ETH_STOP_SEC_CODE
#include "Eth_MemMap.h"


/* ========================================================================== */
/*                          Internal Function Declarations                    */
/* ========================================================================== */


#define Eth_GetMdioWriteLowBaseNsec()  do { \
    NOP50;\
    NOP30;\
 } while(TRUE == FALSE)
#define Eth_GetMdioWriteHighBaseNsec() do { \
    NOP100;\
 } while(TRUE == FALSE)
#define Eth_GetMdioReadLowBaseNsec()   do { \
    NOP50;\
    NOP30;\
 } while(TRUE == FALSE)
#define Eth_GetMdioReadHighBaseNsec()  do  { \
    NOP100;\
    NOP50;\
    NOP30;\
 } while(TRUE == FALSE)
/* @} */

#define Eth_GetMdioWriteLowDelayNsec(CtrlIdx)  do { \
    NOP100;\
    NOP50;\
    NOP20;\
 } while(TRUE == FALSE)
#define Eth_GetMdioWriteHighDelayNsec(CtrlIdx) do { \
    NOP100;\
    NOP50;\
 } while(TRUE == FALSE)
#define Eth_GetMdioReadLowDelayNsec(CtrlIdx)   do { \
    NOP100;\
    NOP50;\
    NOP20;\
 } while(TRUE == FALSE)
#define Eth_GetMdioReadHighDelayNsec(CtrlIdx)  do { \
    NOP50;\
    NOP20;\
 } while(TRUE == FALSE)
/* @} */

#ifdef __cplusplus
}
#endif

#endif  /* #ifndef ETH_CFG_H_ */

/* @} */