The on-chip oscillator circuit of all the TMS570/RMx devices enables a crystal/resonator connected to the OSCIN and OSCOUT pins. The internal oscillator is a single-stage inverter held in bias by an integrated bias resistor. The crystal is connected across the OSCIN and OSCOUT pins. Kelvin_GND should not be connected to any other GND.

Figure above shows the external circuitry and connections required for using the internal oscillator, along with the equation defining the relationship between the manufacturer’s specified crystal load capacitance CLOAD, formed by two external capacitors C1 and C2. The effective load capacitance, CLOAD, appears to the crystal circuit as the series combination of C1 and C2. Correct CLOAD is important for proper operating frequency. Crystals are available with a variety of CLOAD values.

CLOAD = (C1 * C2 ) / (C1 + C2 ) + CS

CS is the stray capacitance in the oscillator circuit. Stray capacitance is a function of trace lengths, PCB construction, and microcontroller pin design. For a typical design, CS should be approximately 2pF to 4pF. Because C1 and C2 are normally of equal value, the calculation for a typical circuit simplifies slightly to: C1 and C2 = (CLOAD – 3pF) * 2

NOTE: TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine which load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature and voltage extremes.

An external oscillator source can be used by connecting a 3.3-V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open). Kelvin_GND is connected to board digital GND.

The device supports up to two external clock inputs (EXTCLKIN1, EXTCLKIN2). This clock input must be a square-wave input. The maximum clock frequency is 80MHz. The electrical and timing requirements for these clock inputs are specified in device datasheet. The external clock sources are not checked for validity. They are assumed valid when enabled.

TMS570 and RMx microcontroller has a built in LPOCLKDET circuitry. The LPOCLKDET (low-power oscillator and clock detect) compares the oscillator input frequency with the internal LPO HF. The clock detect circuit works by checking for a rising edge on one clock (oscillator or HF LPO) between rising edges of the other clock. In case the OSCIN frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp mode clock). Application firmware should detect the input clock failure and initiate a necessary shut-down procedure for the system.

The ECLK pin can be configured to output a pre-scaled clock signal of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency. It also can be used as a clock source for other device. ECLK pin can be configured as a GPIO pin.

The key layout objectives should be to minimize both the loop area of the oscillator signals and the overall trace length. A poor oscillator layout can result in unreliable or inaccurate oscillator operation and can also be a noise source.

The nRST pin is open-drain bidirectional (input and output) with a glitch filter. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

The nRST pin has an internal weak pullup. If the open drain reset circuit and its relative switch need a capacitor in order to filter its input signal, an external pullup can speed up the charger of this capacitor.

Caution: Do not connect the nRST pin to a strong high voltage level without a pullup resistor.

The RST pin should never be left floating. It can be driven from a voltage supervisor or other control chip. It can be connected to an external RC combination or it can be pulled up using a 0 to 100K resistor connected to VCCIO (3.3V).

The nRST pin input contains a glitch filter to prevent noise from causing a system reset. It can filter out the pulses less than 475ns (2.1MHz). We still recommend to protect the nRST signal from noise particularly in applications that involve power switching can couple into the reset line. The reset PCB trace should be routed away from noisy signals. Do not run the reset trace close to the edge of the board or parallel to other traces with fast transients.

If the RST signal source is another board, it is recommended to add a buffer IC on the TMS570 board to filter the signal.

A simple push-switch can be used to provide a manual reset. To protect against possible device damage due to electrostatic discharge and to avoid ringing on the nRST signal caused by switch bounce and stray inductance, add a low-value resistor (100 Ω) in series with the switch.

This is the power-on reset. This reset must be asserted by an external circuitry whenever any power supply is outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

During the device is powered up, the nPORRST must be hold down for at least 1ms after VCC reaches to VCCPORH. When the device is powered down, the nPORRST must be hold down for at least 1ms after VCCIO and VCCP reaches to VCCIOPORL.

For the nPORRST pin, simple R-C filter is adequate. However, ESD protection diodes may offer a better protection.

VCCAD and VSSAD are not truly analog power and grounds. They contain digital noise generated during conversion. VSSAD is also connected to VSS through p-substrate inside the IC, the high frequency VSS current in the digital and core area can also flow through this VSSAD pin to the board ground. A minimum 100nF decoupling capacitor should be placed between VCCAD and VSSAD. This decoupling capacitor should be placed close the pins.

VREFHI and VREFLO are the reference voltages for the conversion. They should be extremely clean. Random noise on these two pins leads to random noise on the conversion result. A minimum 100nF decoupling capacitor should be placed between VREFHI and VREFLO. This decoupling capacitor should be placed close the pins.

Do not share VIAs between VSSAD and VREFLO or between VCCAD and VREFHI because the self-inductance of the common VIA couples digital noise to the voltage reference pins.

Optimal ADC accuracy is achieved with a low-impedance source (RS ) and a large input filter capacitor (CS ). As the signal source impedance increases and capacitance decreases, noise on the conversion result increases. Noise sources include coupling from other signals, power supplies, external devices, and from the microcontroller itself.

It is a good practice to use an op-amp driver circuit for signal conditioning of input analog signals and as a buffer. The op-amp isolates the ADC, acts as a low-impedance source to charge the sample capacitor, and it can be configured as a unity gain buffer or level shifter. It provides low/stable output impedance and protects the ADC inputs.

If the input frequency and sampling frequency is low, or the input signal driving strength is strong, the OP-AMP is not a MUST.

Usually, the analog input carries all kinds of noise. You should have some prior understanding of the nature of the input signals to be measured, for example, the minimum or maximum frequency. Then, a filter can be designed to improve the signal to noise ratio (SNR).

The external Rext and Cext form a low-pass filter. Rext isolates the ADC from the op-amp, and Cext acts as a reservoir and helps in signal stability during sampling. Please refer to SPNA061 for selecting the optimum capacitor value and the resistor value.

MibADC input pins are always defined as input without internal pull. It is recommended that all unused MibADC inputs are terminated to the analog ground (VSS). Having high-input impedance if left open, these pins can pick up noise signals and affect the performance of other inputs to the MibADC.

It is recommended to keep the connections for the analog power pins - even if the MibADC is not used. ADCREFHI and ADCREFLO need to be connected to VCCAD and GND.

A voltage monitor (VMON) is implemented on all the Hercules devices. The use of VMON eliminates the requirement for a specific sequence when powering up the core and I/O voltage supplies.

It is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any input pin prior to powering up the device. Voltages applied to pins of an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.

The Hercules devices need to follow the power-down sequencing. During power-down, the nPORRST should be asserted low at least 1ms before the VCCIO supply reaches 1.14 V. This helps to keep on-chip flash logic in reset prior to the VCCIO/VCC power supplies ramping down.

It is recommended that you use the external voltage supervisors to meet this constraint.

Hercules devices are fabricated using advanced CMOS technology. The CMOS circuits draw large currents at every transition, producing current spikes on the supply rails. These rising and falling glitches have to be filtered before they traverse into the sensitive circuit area. The bypass or decoupling capacitors placed across power supply pins and ground are used for such filtering.

Hercules devices have several power supply pins. You need to use one capacitor on each power supply pin and should place this capacitor as close to the pin as possible, without using any via. Typically small (100nF), low-ESR ceramic capacitors are used for this purpose.

Adding bypass capacitors to the analog supply pins helps reduce power-supply noise entering the analog circuit.

Hercules devices comply with TI standard ESD specifications and are tested for ESD compliance. Hercules devices offer device-level ESD specifications like the charge device model (CDM, ±500 V for all pins and ±750V for corner pins) and the human body model (HBM, ±2.0 KV). Device level ESD specifications are not sufficient to protect devices in a system. The energy associated with a system-level ESD strike is much higher than a device-level ESD strike.

Any signal from the Hercules microcontroller that is exposed outside the system enclosure via a connector should have an ESD protection.