Advanced Event Triggering Target Library (AET)
02_70_00
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Data Structures | |
struct | AET_jobParams |
Structure that holds the parameters needed to be passed to the AET_setupJob Function. More... | |
Typedefs | |
typedef uint16_t | AET_traceTrigger |
typedef uint8_t | AET_jobIndex |
Type returned in the data parameters structures which indicates which entry in the jobs database that the job programmed occupies. More... | |
Functions | |
AET_error | AET_claim (void) |
Claims the AET unit for use by the application. More... | |
AET_error | AET_configCounter (AET_counterConfigParams *params) |
Configures the Counters used with AET. More... | |
AET_error | AET_clearCounters () |
Disables the AET jobs that have been programmed. More... | |
AET_error | AET_disable (void) |
Clears all existing Counter configurations. | |
AET_error | AET_enable (void) |
Enables the AET jobs that have been programmed. More... | |
void | AET_init (void) |
Initializes the application. More... | |
int32_t | AET_readCounter (AET_counters) |
Read counter value. More... | |
AET_error | AET_release (void) |
Release ownership of the AET resources. More... | |
AET_error | AET_releaseJob (AET_jobIndex jobIndex) |
Clear an AET job. More... | |
AET_error | AET_setupJob (AET_jobType jobType, AET_jobParams *params) |
Programs specified AET jobs. More... | |
AET_error | AET_enableEmuPins (void) |
Enables EMU0 and EMU1 pins for ET0/1 input/output. More... | |
AET_error | AET_disableEmuPins (void) |
Disables EMU0 and EMU1 pins for ET0/1 input/output. More... | |
Platforms Supported
Description
This module allows users to program Advanced Event Triggering hardware from their application at run time. This enables creation of trigger events based on behavior of the application.
2.a Triggering on Events (64x+) There are a number of events that can be triggered on in the 64x+ world. These events can be useful for scenarios like capturing a PC with trace whenever an L2 data cache miss occurs. These events are listed in the AET_eventNumber enumeration. There are 3 categories of events, Memory, Stall, Miscellaneous. A fourth category, System Events, is actually a subset of miscellaneous events. However, only one of these 3 categories can be used at a time. If a job is programmed using the Miscellanous events, subsequently programming a job that uses a memory event will fail. in order to use a memory event, the job that uses the miscellaneous event must be released using the AET_releaseJob function. These categories are managed automatically on a forst programmed category basis. For example: If a memory event job is programmed first, all subsequent jobs must use memory events until all existing memory event jobs are released. The return status will be AET_FINVALIDEVTCLASS for this failure scenario.
============================================================================= | RESOURCE | 64x | 64x+ | ============================================================================= | ADDRESS COMPARATOR | 4 | 6* | | DATA COMPARATOR | 2 | 2 | | 1-WIDE TRIGGER BUILDER | 6 | 6 | | 3-WIDE TRIGGER BUILDER | 6 | 6 | | 7-WIDE TRIGGER BUILDER | 2 | 2 | | COUNTER/TIMER | 2 | 2 | | AUXILLIARY EVENT GENERATOR | 1 | 4 | | STATE MACHINE | 1/2**| 1/2**| ============================================================================= * On the 64x+, Address Comparators 4 & 5 are Program Address only ** The State Machines can be configured as 1 4-state machine or 2 2-state machines
The following tools were used to build and test these libraries.
Software Tools: Codegen: v7.3.1 Code Composer Studio 5.1.1 Hardware: Spectrum Digital 6416DSK (64x) Spectrum Digital 6455DSK (64x+) Advantech EVMC6678L (66x)
#define AET_MAJOR_VERSION (0x4) |
Major version number - Incremented for API changes
#define AET_MINOR_VERSION (0x11) |
Minor version number - Incremented for bug fixes
#define AET_TRACE_NONE (0x0u) |
No Triggers Specified
#define AET_TRACE_TIMING (0x1u) |
Generate a Start Timing Trace Trigger
#define AET_TRACE_PA (0x2u) |
Generate Start PC Trace Trigger
#define AET_TRACE_RA (0x4u) |
Generate Start Read Address Trace Trigger
#define AET_TRACE_WA (0x8u) |
Generate Start Write Address Trace Trigger
#define AET_TRACE_RD (0x10u) |
Generate Start Read Data Trace Trigger
#define AET_TRACE_WD (0x20u) |
Generate Start Write Data Trace Trigger
#define AET_TRACE_PCTAG (0x40u) |
Generate Start PCTAG Trace Trigger
#define AET_TRACE_STOP_PC (0x1u) |
Generate Stop PC Trace Trigger
#define AET_TRACE_STOP_TIMING (0x2u) |
Generate Stop Timing Trace Trigger
#define AET_TRACE_STOP_DATA (0x4u) |
Generate Stop Data Trace Trigger
#define AET_TRACE_STRM_ENBL_NONE (0x0u) |
Enable no streams
#define AET_TRACE_STRM_ENBL_TIMING (0x1u) |
Enable the Trace Timing Stream
#define AET_TRACE_STRM_ENBL_PC (0x2u) |
Enable the Program Address Trace Stream
#define AET_TRACE_STRM_ENBL_MEM_RD (0x4u) |
Enable the Data Read Trace Stream
#define AET_TRACE_STRM_ENBL_MEM_WT (0x8u) |
Enable the Data Write Trace Stream
Note that the stream enable configurations will NOT work when using PIN trace through the XDS560 Trace cable. This is only usable when dumping the trace output to an Embedded Trace Buffer.
#define AET_TRACE_STRM_PRES_NONE (0x00u) |
No Streams are Present
#define AET_TRACE_STRM_PRES_RD_DAT (0x01u) |
Read Data Stream Present
#define AET_TRACE_STRM_PRES_RD_ADDR (0x02u) |
Read Address Stream Present
#define AET_TRACE_STRM_PRES_RD_PC (0x0Cu) |
Read Program Counter Stream Present
#define AET_TRACE_STRM_PRES_WT_DAT (0x10u) |
Write Data Stream Present
#define AET_TRACE_STRM_PRES_WT_ADDR (0x20u) |
Write Address Stream Present
#define AET_TRACE_STRM_PRES_WT_PC (0x40u) |
Write Program Counter Stream Present
#define AET_NUMSYSEVTS 128 |
Number of total possible system events
#define AET_NUMGEMEVTS 128 |
Number of total possible GEM events
#define AET_NUMGEMMEMEVTS 32 |
Number of total possible GEMMemory Events
#define AET_NUMGEMSTALLEVTS 32 |
Number of total possible GEM Stall events
#define AET_NUMGEMMISCEVTS 32 |
Number of total possible GEM Miscellaneous events
#define AET_NUM_EXT_EVTS AET_NUMSYSEVTS + AET_NUMGEMEVTS |
Number of total possible External GEM events
#define AET_GEM_EVT_START AET_NUMSYSEVTS |
Index where Gem Events Start
#define AET_GEM_EVT_END AET_GEM_EVT_START + AET_NUMGEMEVTS-1 |
Index where Gem Events End
#define AET_GEM_MEM_EVT_START AET_GEM_EVT_START+AET_NUMGEMEVTS |
Index where Gem Memory Events Start
#define AET_GEM_MEM_EVT_END AET_GEM_MEM_EVT_START+AET_NUMGEMMEMEVTS-1 |
Index where Gem Memory Events End
#define AET_GEM_STALL_EVT_START AET_GEM_MEM_EVT_START+AET_NUMGEMMEMEVTS |
Index where Gem Stall Events Start
#define AET_GEM_STALL_EVT_END AET_GEM_STALL_EVT_START+AET_NUMGEMSTALLEVTS-1 |
Index where Gem Stall Events End
#define AET_GEM_MISC_EVT_START AET_GEM_STALL_EVT_START+AET_NUMGEMSTALLEVTS |
Index where Gem Miscellaneous Events Start
#define AET_GEM_MISC_EVT_END AET_GEM_MISC_EVT_START+AET_NUMGEMMISCEVTS-1 |
Index where Gem Events End
#define AET_EVT_NONE 0xFFFF |
No Event
#define AET_GEM_EVT_EXCEP (AET_GEM_EVT_START + 64) |
CPU Exception
#define AET_GEM_EVT_NMI (AET_GEM_EVT_START + 65) |
Non-maskable CPU Interrupt
#define AET_GEM_CPUINT_4 (AET_GEM_EVT_START + 68) |
CPU Interrupt 4
#define AET_GEM_CPUINT_5 (AET_GEM_EVT_START + 69) |
CPU Interrupt 5
#define AET_GEM_CPUINT_6 (AET_GEM_EVT_START + 70) |
CPU Interrupt 6
#define AET_GEM_CPUINT_7 (AET_GEM_EVT_START + 71) |
CPU Interrupt 7
#define AET_GEM_CPUINT_8 (AET_GEM_EVT_START + 72) |
CPU Interrupt 8
#define AET_GEM_CPUINT_9 (AET_GEM_EVT_START + 73) |
CPU Interrupt 9
#define AET_GEM_CPUINT_10 (AET_GEM_EVT_START + 74) |
CPU Interrupt 10
#define AET_GEM_CPUINT_11 (AET_GEM_EVT_START + 75) |
CPU Interrupt 11
#define AET_GEM_CPUINT_12 (AET_GEM_EVT_START + 76) |
CPU Interrupt 12
#define AET_GEM_CPUINT_13 (AET_GEM_EVT_START + 77) |
CPU Interrupt 13
#define AET_GEM_CPUINT_14 (AET_GEM_EVT_START + 78) |
CPU Interrupt 14
#define AET_GEM_CPUINT_15 (AET_GEM_EVT_START + 79) |
CPU Interrupt 15
#define AET_GEM_IACK (AET_GEM_EVT_START + 96) |
Interrupt Acknowledge (Any Interrupt)
#define AET_GEM_EACK (AET_GEM_EVT_START + 97) |
Exception Acknowledge for either EXCEP or NMI
#define AET_GEM_IACK_4 (AET_GEM_EVT_START + 100) |
Interrupt Acknowledge for CPU Interrupt 4
#define AET_GEM_IACK_5 (AET_GEM_EVT_START + 101) |
Interrupt Acknowledge for CPU Interrupt 5
#define AET_GEM_IACK_6 (AET_GEM_EVT_START + 102) |
Interrupt Acknowledge for CPU Interrupt 6
#define AET_GEM_IACK_7 (AET_GEM_EVT_START + 103) |
Interrupt Acknowledge for CPU Interrupt 7
#define AET_GEM_IACK_8 (AET_GEM_EVT_START + 104) |
Interrupt Acknowledge for CPU Interrupt 8
#define AET_GEM_IACK_9 (AET_GEM_EVT_START + 105) |
Interrupt Acknowledge for CPU Interrupt 9
#define AET_GEM_IACK_10 (AET_GEM_EVT_START + 106) |
Interrupt Acknowledge for CPU Interrupt 10
#define AET_GEM_IACK_11 (AET_GEM_EVT_START + 107) |
Interrupt Acknowledge for CPU Interrupt 11
#define AET_GEM_IACK_12 (AET_GEM_EVT_START + 108) |
Interrupt Acknowledge for CPU Interrupt 12
#define AET_GEM_IACK_13 (AET_GEM_EVT_START + 109) |
Interrupt Acknowledge for CPU Interrupt 13
#define AET_GEM_IACK_14 (AET_GEM_EVT_START + 110) |
Interrupt Acknowledge for CPU Interrupt 14
#define AET_GEM_IACK_15 (AET_GEM_EVT_START + 111) |
Interrupt Acknowledge for CPU Interrupt 15
#define AET_EVT_MEM_L1D_RH_SRAM_A (AET_GEM_MEM_EVT_START + 0) |
L1D Read Hit SRAM A
#define AET_EVT_MEM_L1D_RH_SRAM_B (AET_GEM_MEM_EVT_START + 1) |
L1D Read Hit SRAM B
#define AET_EVT_MEM_L1D_RH_CACHE_A (AET_GEM_MEM_EVT_START + 2) |
L1D Read Hit Cache A
#define AET_EVT_MEM_L1D_RH_CACHE_B (AET_GEM_MEM_EVT_START + 3) |
L1D Read Hit Cache B
#define AET_EVT_MEM_L1D_WH_BUF_NOT_FULL_A (AET_GEM_MEM_EVT_START + 4) |
L1D Write Hit, Tag Buffer Not Full A
#define AET_EVT_MEM_L1D_WH_BUF_NOT_FULL_B (AET_GEM_MEM_EVT_START + 5) |
L1D Write Hit, Tag Buffer Not Full B
#define AET_EVT_MEM_L1D_WH_BUF_FULL_A (AET_GEM_MEM_EVT_START + 6) |
L1D Write Hit, Tag Buffer Full A
#define AET_EVT_MEM_L1D_WH_BUF_FULL_B (AET_GEM_MEM_EVT_START + 7) |
L1D Write Hit, Tag Buffer Full B
#define AET_EVT_MEM_L1D_RM_HITS_L2_SRAM_A (AET_GEM_MEM_EVT_START + 8) |
L1D Read Miss, Hits L2 SRAM A
#define AET_EVT_MEM_L1D_RM_HITS_L2_SRAM_B (AET_GEM_MEM_EVT_START + 9) |
L1D Read Miss, Hits L2 SRAM B
#define AET_EVT_MEM_L1D_RM_HITS_L2_CACHE_A (AET_GEM_MEM_EVT_START + 10) |
L1D Read Miss, Hits L2 Cache A
#define AET_EVT_MEM_L1D_RM_HITS_L2_CACHE_B (AET_GEM_MEM_EVT_START + 11) |
L1D Read Miss, Hits L2 Cache B
#define AET_EVT_MEM_L1D_RM_HITS_EXT_CABLE_A (AET_GEM_MEM_EVT_START + 12) |
L1D Read Miss, Hits External, Cacheable A
#define AET_EVT_MEM_L1D_RM_HITS_EXT_CABLE_B (AET_GEM_MEM_EVT_START + 13) |
L1D Read Miss, Hits External, Cacheable B
#define AET_EVT_MEM_L1D_RM_HITS_EXT_NON_CABLE_A (AET_GEM_MEM_EVT_START + 14) |
L1D Read Miss, Hits External, Non Cacheable A
#define AET_EVT_MEM_L1D_RM_HITS_EXT_NON_CABLE_B (AET_GEM_MEM_EVT_START + 15) |
L1D Read Miss, Hits External, Non Cacheable B
#define AET_EVT_MEM_L1D_WM_WRT_BUF_NOT_FULL_A (AET_GEM_MEM_EVT_START + 16) |
L1D Write Miss, Write Buffer Not Full A
#define AET_EVT_MEM_L1D_WM_WRT_BUF_NOT_FULL_B (AET_GEM_MEM_EVT_START + 17) |
L1D Write Miss, Write Buffer Not Full B
#define AET_EVT_MEM_L1D_WM_WRT_BUF_FULL_A (AET_GEM_MEM_EVT_START + 18) |
L1D Write Miss, Write Buffer Full A
#define AET_EVT_MEM_L1D_WM_WRT_BUF_FULL_B (AET_GEM_MEM_EVT_START + 19) |
L1D Write Miss, Write Buffer Full B
#define AET_EVT_MEM_L1D_WM_TAG_VIC_WRT_BUF_FLUSH_A (AET_GEM_MEM_EVT_START + 20) |
L1D Write Miss, Tag/Victim/Write Buffer Flush A
#define AET_EVT_MEM_L1D_WM_TAG_VIC_WRT_BUF_FLUSH_B (AET_GEM_MEM_EVT_START + 21) |
L1D Write Miss, Tag/Victim/Write Buffer Flush B
#define AET_EVT_MEM_CPU_CPU_BANK_CONFLICT (AET_GEM_MEM_EVT_START + 22) |
CPU - CPU Bank Conflict
#define AET_EVT_MEM_CPU_SNOOP_CONFLICT (AET_GEM_MEM_EVT_START + 23) |
CPU - Snoop/Coherence Conflict (A or B)
#define AET_EVT_MEM_CPU_IDMA_EDMA_BANK_CONFLICT (AET_GEM_MEM_EVT_START + 24) |
CPU - iDMA/EDMA Bank Conflict (A or B)
#define AET_EVT_MEM_L1P_RH_SRAM (AET_GEM_MEM_EVT_START + 25) |
L1P Read Hit SRAM
#define AET_EVT_MEM_L1P_RH_CACHE (AET_GEM_MEM_EVT_START + 26) |
L1P Read Hit Cache
#define AET_EVT_MEM_L1P_RM_HITS_L2_SRAM (AET_GEM_MEM_EVT_START + 27) |
L1P Read Miss, Hits L2 SRAM
#define AET_EVT_MEM_L1P_RM_HITS_L2_CACHE (AET_GEM_MEM_EVT_START + 28) |
L1P Read Miss, Hits L2 Cache
#define AET_EVT_MEM_L1P_RM_HITS_EXT_CABLE (AET_GEM_MEM_EVT_START + 29) |
L1P Read Miss, Hits External Cacheable
#define AET_EVT_STALL_CPU_PIPELINE (AET_GEM_STALL_EVT_START + 0) |
CPU Stall Cycles
#define AET_EVT_STALL_CROSS_PATH (AET_GEM_STALL_EVT_START + 1) |
Stall Due to a Cross path
#define AET_EVT_STALL_BRANCH_TO_SPAN_EXEC_PKT (AET_GEM_STALL_EVT_START + 2) |
Stall due to a branch to an execute packet that spans two fetch packets
#define AET_EVT_STALL_EXT_FUNC_IFACE (AET_GEM_STALL_EVT_START + 3) |
Stall due to an External Functional Interface
#define AET_EVT_STALL_MVC (AET_GEM_STALL_EVT_START + 4) |
Stall Conditions: 1) AMR write followed by addressing mode instruction and src2 register is affected by AMR Values 2) Read of emulation registers in the ECM
#define AET_EVT_STALL_L1P_OTHER (AET_GEM_STALL_EVT_START + 5) |
Any other stall not prwviously listed
#define AET_EVT_STALL_L1P_WAIT_STATE (AET_GEM_STALL_EVT_START + 6) |
Stall due to Wait states in L1P Memory
#define AET_EVT_STALL_L1P_MISS (AET_GEM_STALL_EVT_START + 8) |
Execute Packed held off due to a Cache Miss
#define AET_EVT_STALL_L1D_OTHER (AET_GEM_STALL_EVT_START + 10) |
Any other L1D Stall not previosuly listed
#define AET_EVT_STALL_L1D_BANK_CONFLICT (AET_GEM_STALL_EVT_START + 11) |
Stall on a memory bank conflict between A and B
#define AET_EVT_STALL_L1D_DMA_CONFLICT (AET_GEM_STALL_EVT_START + 12) |
Stall while CPU access is held off by a DMA Access
#define AET_EVT_STALL_L1D_WRITE_BUFFER_FULL (AET_GEM_STALL_EVT_START + 13) |
Stall on a write miss on A or B while the Write Buffer is Full
#define AET_EVT_STALL_L1D_TAG_UD_BUF_FULL (AET_GEM_STALL_EVT_START + 14) |
Stall on a Write Hit with a tag update on either A or B while the tag update buffer is full
#define AET_EVT_STALL_L1D_LINE_FILL_B (AET_GEM_STALL_EVT_START + 15) |
Stall on a read miss on B while the read miss data is being fetched from the lower memory level
#define AET_EVT_STALL_L1D_LINE_FILL_A (AET_GEM_STALL_EVT_START + 16) |
Stall on a read miss on A while the read miss data is being fetched from the lower memory level
#define AET_EVT_STALL_L1D_WRT_BUF_FLUSH (AET_GEM_STALL_EVT_START + 17) |
Stall on a read Miss on Either A or B while the Write Buffer is being flushed
#define AET_EVT_STALL_L1D_VICTIM_BUF_FLUSH (AET_GEM_STALL_EVT_START + 18) |
Stall on a read miss on either A or B while the Victim Buffer is being flushed
#define AET_EVT_STALL_L1D_TAG_UD_BUF_FLUSH (AET_GEM_STALL_EVT_START + 20) |
Stall on a read miss on either A or B while the Tag Update Buffer is being flushed
#define AET_EVT_STALL_L1D_SNOOP_CONFLICT (AET_GEM_STALL_EVT_START + 21) |
Stall while a CPU access is held off by a Snoop access
#define AET_EVT_STALL_L1D_COH_OP_CONFLICT (AET_GEM_STALL_EVT_START + 22) |
Stall while a CPU access is held off by a block cache coherence operation access
#define AET_EVT_MISC_EXEC_CYCLES (AET_GEM_MISC_EVT_START + 0) |
Execute Cycle Event
#define AET_EVT_MISC_STALL_PIPELINE (AET_GEM_MISC_EVT_START + 1) |
Pipeline Stall Event
#define AET_EVT_MISC_MARK_INS_0 (AET_GEM_MISC_EVT_START + 2) |
Mark Instruction Id 0 Event
#define AET_EVT_MISC_MARK_INS_1 (AET_GEM_MISC_EVT_START + 3) |
Mark Instruction Id 1 Event
#define AET_EVT_MISC_MARK_INS_2 (AET_GEM_MISC_EVT_START + 4) |
Mark Instruction Id 2 Event
#define AET_EVT_MISC_MARK_INS_3 (AET_GEM_MISC_EVT_START + 5) |
Mark Instruction Id 3 Event
#define AET_EVT_MISC_ET0 (AET_GEM_MISC_EVT_START + 6) |
External Trigger 0
#define AET_EVT_MISC_ET1 (AET_GEM_MISC_EVT_START + 7) |
External Trigger 1
#define AET_EVT_MISC_IACK (AET_GEM_MISC_EVT_START + 8) |
Interrupt Acknowledge Event
#define AET_EVT_MISC_AEGEVT0 (AET_GEM_MISC_EVT_START + 9) |
System Event connected through Interrupt Controller to AEGEVT0
#define AET_EVT_MISC_AEGEVT1 (AET_GEM_MISC_EVT_START + 10) |
System Event connected through Interrupt Controller to AEGEVT1
#define AET_EVT_MISC_AEGEVT2 (AET_GEM_MISC_EVT_START + 11) |
System Event connected through Interrupt Controller to AEGEVT2
#define AET_EVT_MISC_AEGEVT3 (AET_GEM_MISC_EVT_START + 12) |
System Event connected through Interrupt Controller to AEGEVT3
#define AET_EVT_MISC_AEGEVT4 (AET_GEM_MISC_EVT_START + 13) |
System Event connected through Interrupt Controller to AEGEVT4
#define AET_EVT_MISC_AEGEVT5 (AET_GEM_MISC_EVT_START + 14) |
System Event connected through Interrupt Controller to AEGEVT5
#define AET_EVT_MISC_AEGEVT6 (AET_GEM_MISC_EVT_START + 15) |
System Event connected through Interrupt Controller to AEGEVT6
#define AET_EVT_MISC_AEGEVT7 (AET_GEM_MISC_EVT_START + 16) |
System Event connected through Interrupt Controller to AEGEVT7
#define AET_EVT_MISC_EXCEP (AET_GEM_MISC_EVT_START + 17) |
Exception
#define AET_EVT_MISC_EXC (AET_GEM_MISC_EVT_START + 18) |
Exception Acknowledge
#define AET_EVT_MISC_NMI (AET_GEM_MISC_EVT_START + 19) |
Non Maskable Interrupt
#define AET_EVT_MISC_RTDX_RX_END (AET_GEM_MISC_EVT_START + 20) |
HS-RTDX Receive Completed
#define AET_EVT_MISC_RTDX_TX_END (AET_GEM_MISC_EVT_START + 21) |
HS-RTDX Transmit Completed
#define AET_EVT_MISC_DTDMA_END (AET_GEM_MISC_EVT_START + 22) |
DT-DMA Upload Completed
#define AET_EVT_MISC_L1D_WM_HIT_L2SRAM (AET_GEM_MISC_EVT_START + 23) |
L1D write miss, hits L2 SRAM
#define AET_EVT_MISC_L1D_WM_HIT_L2CACHE (AET_GEM_MISC_EVT_START + 24) |
L1D write miss, hits L2 Cache
#define AET_EVT_MISC_L1D_WM_HIT_EXT_CABLE (AET_GEM_MISC_EVT_START + 25) |
L1D write miss, hits external, cacheable
#define AET_EVT_MISC_L1D_WM_HIT_EXT_NONCABLE (AET_GEM_MISC_EVT_START + 26) |
L1D write miss, hits external, non-cacheable
#define AET_EVT_MISC_DIRTY_VICTIM_WRITEBACK_L2 (AET_GEM_MISC_EVT_START + 27) |
Dirty Victim writeback from L2
#define AET_EVT_MISC_DMA_SNOOP_READ (AET_GEM_MISC_EVT_START + 28) |
DMA Snoop Read
#define AET_EVT_MISC_DMA_SNOOP_WRITE (AET_GEM_MISC_EVT_START + 29) |
DMA Snoop Write
#define AET_EVT_MISC_TAG_UD_QUEUED_TAG_UD_BUF (AET_GEM_MISC_EVT_START + 30) |
Tag Update Queued Tag Update Buffer
#define AET_EVT_MISC_DIRTY_VICTIM_WRITEBACK_L1D (AET_GEM_MISC_EVT_START + 31) |
Dirty Vistim Writeback from L1D
typedef uint16_t AET_traceTrigger |
AET_traceTrigger Specifies the bitfields according to which triggers will be enabled
typedef uint8_t AET_jobIndex |
Type returned in the data parameters structures which indicates which entry in the jobs database that the job programmed occupies.
When a job is programmed, a configWord structure is generated which records which resources are used by that job. This structure is stored in an array, and the index to that array can be acquired by the calling application. The calling application can clear the job by passing the index number to the AET_releaseJob function
enum AET_error |
AET_error enumeration Specifies a lise of potential error codes that the library can return to the user
enum AET_jobType |
AET_jobType enumerationn Specififes a list of Jobs that can be passed to the AET_setupJob function. Not all of these jobs are currently implemented.
enum AET_triggerType |
AET_triggerType enumerationn Specififes a list of events that can be triggered by AET
enum AET_refSize |
AET_refSize enumeration Specifies the reference size when using a trigger on data scenario or trigger on data range scenario. The triggers are set up to catch any size read or write. The reference size determines the distance from the given address that will generate a trigger
Examples: Address = 0x80010000, Reference Size = Byte Trigger Generated on Read/Write access to byte address 0x80010000 only Address = 0x80010000, Reference Size = Halfword Trigger Generated on Read/Write access to byte addresses 0x80010000-0x80010001 Address = 0x80010000, Reference Size = Word Trigger Generated on Read/Write access to byte addresses 0x80010000-0x80010003 Address = 0x80010000, Reference Size = Double Word Trigger Generated on Read/Write access to byte addresses 0x80010000-0x80010007
Enumerator | |
---|---|
AET_REF_SIZE_BYTE |
8-bits |
AET_REF_SIZE_HALFWORD |
16-bits |
AET_REF_SIZE_WORD |
32-bits |
AET_REF_SIZE_DOUBLEWORD |
64-bits |
enum AET_watchReadWrite |
enum AET_counterConfig |
AET_counterConfig enumeration Allows specification of both the operating mode and the timer/counter mode of the counter/timer resource. This has been added to replace separate configurations.
AET_traceCacheProfilingMode enumeration Allows specification of the Cache Progiling mode for Trace. The default mode is normal mode.
enum AET_counters |
enum AET_watermarkAction |
enum AET_traceActive |
AET_traceActive Specifies whether to start or stop tracing
AET_triggerLogicOrientation Specifies if the logic for the trigger builder is straightforward or inverted. (eg. for Trigger on PC in range, Straighforward triggers when the PC is in range. Inverted triggers when the PC is outside of the range
enum AET_stateQual |
AET_stateQual Specifies a state machine state to qualify the job with
AET_error AET_claim | ( | void | ) |
Claims the AET unit for use by the application.
This function must be called prior to the following functions
AET_setupJob AET_enable AET_release AET_counterConfig
It must be called after AET_init
The AET unit is shared between the application and the debugger. Calling this function claims it for use by the application. After claim has been executed, the debugger has no access to the AET resources until AET_release has been called. If AET is already claimed by the debugger, the AET_claim call will fail
AET_error AET_configCounter | ( | AET_counterConfigParams * | params | ) |
Configures the Counters used with AET.
This function will set the counter mode, operating mode, and reload value for one of the counters. This function must be called prior to calling AET_setupJob for any of the counter related jobs.
*params | Pointer to the configuration structure for counter configuration |
AET_error AET_clearCounters | ( | ) |
Disables the AET jobs that have been programmed.
AET_disable can be called at any time in the application to temporarily disable any jobs that have been programmed.
AET_error AET_enable | ( | void | ) |
Enables the AET jobs that have been programmed.
AET_enable must be called by the target application after programmation of a job. Programming the job(s) will set all of the register values correctly, but the jobs will not be enabled until the user calls this function. The hardware does not provide an analogous way to disable the AET. In order to disable the AET jobs, the user must execute an AET_release, and then re-issue AET_claim. This functionality is not provided by the library because there is a slight risk that the debugger could claim AET before the application can claim it again.
void AET_init | ( | void | ) |
Initializes the application.
AET_init must be called prior to executing any of the other AET API's It should only be called once. It initializes global variables and some data that the library uses. All of the other API's will fail if the library is not properly initialized
int32_t AET_readCounter | ( | AET_counters | ) |
Read counter value.
AET_readCounter is called to read the value of the specified counter. It simply returns the value in the counter register
AET_error AET_release | ( | void | ) |
Release ownership of the AET resources.
AET_release returns the status of the AET block to available. At this point, it can be claimed by the debugger, or it can be reclaimed by the application.
AET_error AET_releaseJob | ( | AET_jobIndex | jobIndex | ) |
Clear an AET job.
AET_releaseJob releases the resources used by a previously programmed AET job. It removes the references to the AET job in the job table.
jobIndex | Index to an existing job in the job table. |
AET_error AET_setupJob | ( | AET_jobType | jobType, |
AET_jobParams * | params | ||
) |
Programs specified AET jobs.
AET_setupJob programs the AET registers for the job that is specified. Resource management will attempt to use available resources for the job, and will keep track of the resources used. Resource usage is stored by the application. A job id can be acquired by the application by referencing the jobIndex member of the parameters structure after sucessfully executing the AET_setupJob function.
jobType | Enumeration for the type of job being progammed |
*params | Pointer to a configuration structure for the job type selected |
AET_error AET_enableEmuPins | ( | void | ) |
Enables EMU0 and EMU1 pins for ET0/1 input/output.
AET_enableEmuPins programs the pin manager to expose ET0 and ET1 to the pins EMU0 and EMU1 respectively.
AET_error AET_disableEmuPins | ( | void | ) |
Disables EMU0 and EMU1 pins for ET0/1 input/output.
AET_disableEmuPins programs the pin manager to disconnect ET0 and ET1 from the EMU0 and EMU1 pins respectively.