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PCMI_Omap4430.h
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1 #ifndef __PMI_CMI_OMAP4430_H
2 #define __PMI_CMI_OMAP4430_H
3 /*
4  * PCMI_Omap4430.h
5  *
6  * Common Power & Clock Management Instrumentation OMAP4430 Specific Definitions
7  *
8  * Copyright (C) 2009, 2010 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  *
15  * Redistributions of source code must retain the above copyright
16  * notice, this list of conditions and the following disclaimer.
17  *
18  * Redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the
21  * distribution.
22  *
23  * Neither the name of Texas Instruments Incorporated nor the names of
24  * its contributors may be used to endorse or promote products derived
25  * from this software without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
40 
48 #ifdef _PMI
49 
53 typedef enum {
59 
63 typedef enum { eLVD_MPU,
66  eLVD_EndEl
67  } ePMI_LVD_OPP;
68 
72 typedef enum { eMVD_SRAM_MPU,
75  eMVD_EndEl
76  } ePMI_MVD_OPP;
77 
81 typedef enum { eLPD_MPU,
94  eLPD_EndEl
96 
100 typedef enum { eMPD_MPU_L1,
125  eMPD_EndEl
127 
131 typedef enum { eMVD_ON,
133  eMVD_PwrState_EndEl
135 
139 typedef enum { eLPD_OFF,
143  eLPD_PwrState_EndEl
145 
149 typedef enum { eMPD_OFF,
153  eMPD_PwrState_EndEl
155 
156 #ifndef _DOXYGEN_IGNORE
157 extern const char * pPMI_LpdPwrStateStr[];
158 extern const char * pPMI_MvdPwrStateStr[];
159 extern const char * pPMI_MpdOppStr[];
160 extern const char * pPMI_LpdOppStr[];
161 extern const char * pPMI_LpdOppStr[];
162 extern const char * pPMI_MvdOppStr[];
163 extern const char * pPMI_DataClassStr[];
164 extern const char * pPMI_LvdOppStr[];
165 extern const char * pPMI_MpdPwrStateStr[];
166 
167 extern const char PMI_DataValueFmtStr[];
168 #endif
169 #endif
170 #ifdef _CMI
171 
175 typedef enum { eCMI_CLOCK_DOMAIN_STATE_CHANGE,
176  eCMI_CLOCK_DIVIDER_RATIO_CHANGE,
177  eCMI_CLOCK_SOURCE_SELECTION_CHANGE,
178  eCMI_DLPP_SETTINGS_CHANGE
179  } eCMI_DataClasses;
180 
184 typedef enum { //CM1 Clock Domain State Change
185  eCMI_CDSC_MPU_DPLL,
186  eCMI_CDSC_TESALA_ROOT,
187  eCMI_CDSC_ABE_24M_GFCLK,
188  eCMI_CDSC_ABE_ALWON_32K,
189  eCMI_CDSC_ABE_SYSCLK,
190  eCMI_CDSC_FUNC_24M_GFCK,
191  eCMI_CDSC_ABE_OCP_GICLK,
192  eCMI_CDSC_ABE_X2_CLK,
193  eCMI_CDSC_L4_ALWON_ICLK,
195  //CM2 Clock Domain State Change
196  eCMI_CDSC_L3_1,
197  eCMI_CDSC_L3_2,
198  eCMI_CDSC_DUCATI,
199  eCMI_CDSC_L3_DMA,
200  eCMI_CDSC_ASYNC_PHY2,
201  eCMI_CDSC_ASYNC_PHY1,
202  eCMI_CDSC_ASYNC_DLL,
203  eCMI_CDSC_PHY_ROOT,
204  eCMI_CDSC_DLL,
205  eCMI_CDSCL3_EMIF,
206  eCMI_CDSC_L4_D2D,
207  eCMI_CDSC_L3_D2D,
208  eCMI_CDSC_L4_CONFIG,
209  eCMI_CDSC_IVAHD_ROOT,
210  eCMI_CDSC_FDIF,
211  eCMI_CDSC_ISS,
212  eCMI_CDSC_DSS_ALWON_SYS,
213  eCMI_CDSC_DSS,
214  eCMI_CDSC_L3_DSS,
215  eCMI_CDSC_SGX,
216  eCMI_CDSC_L3_GFX,
217  eCMI_CDSC_UTMI_ROOT,
218  eCMI_CDSC_INIT_HSMMC_6,
219  eCMI_CDSC_INIT_HSMMC_2,
220  eCMI_CDSC_INIT_HSMMC_1,
221  eCMI_CDSC_INIT_HSI,
222  eCMI_CDSC_USB_DPLL_HS,
223  eCMI_CDSC_USB_DPLL,
224  eCMI_CDSC_INIT_48MC,
225  eCMI_CDSC_INIT_48M,
226  eCMI_CDSC_INIT_96M,
227  eCMI_CDSC_EMAC_50MHZ,
228  eCMI_CDSC_INIT_L4,
229  eCMI_CDSC_INIT_L3,
230  eCMI_CDSC_PER_ABE_24M,
231  eCMI_CDSC_PER_SYS,
232  eCMI_CDSC_PER_96M,
233  eCMI_CDSC_PER_48M,
234  eCMI_CDSC_FUNC_24MC,
235  eCMI_CDSC_FUNC_12M,
236  eCMI_CDSC_PER_L4,
237  eCMI_CDSC_UNIPRO_DPLL,
238  eCMI_CDSC_EndEl
239 
240  }eCMI_ClockDomainStateChange;
241 
245 typedef enum { eCMI_ClkDomainGated,
246  eCMI_ClkDomainActive
247  }eCMI_clkState;
248 
252 typedef enum { //CM1 Clock Divider Ratio Change
253  eCMI_CDRC_CLKSEL_OPP,
254  eCMI_CDRC_BYPCLK_DPLL_MPU,
255  eCMI_CDRC_BYPCLK_DPLL_IVA,
256  eCMI_CDRC_ABE_AESS,
258  //CM2 Clock Divider Ratio Change
259  eCMI_CDRC_SCALE_FCLK,
260  eCMI_CDRC_CAM_FDIF,
261  eCMI_CDRC_GFX_PER_192M
264  } eCMI_ClockDividerRatioChange;
265 
269 typedef enum { eCMI_DivideBy_dummy, // Just a placeholder for 0
270  eCMI_DivideBy_1,
271  eCMI_DivideBy_2,
272  eCMI_DivideBy_3,
273  eCMI_DivideBy_4,
274  eCMI_DivideBy_EndEl
275  } eCMI_divState;
276 
280 typedef enum { //CM1 Clock Source Selection Change
281  eCMI_CSS_CORE_L4,
282  eCMI_CSS_CORE_L3,
283  eCMI_CSS_CORE,
284  eCMI_CSS_DPLL_CORE,
286  //CM2 Clock Source Selection
287  eCMI_CSS_DUCATI_ISS_ROOT,
288  eCMI_CSS_USB_60MHZ,
289  eCMI_CSS_PER_DPLL_BYP,
290  eCMI_CSS_USB_DPLL_BYP,
291  eCMI_CSS_GFX,
292  eCMI_CSS_MMC1,
293  eCMI_CSS_MMC2,
294  eCMI_CSS_HSI
295  } eCMI_ClockSource;
296 
300 typedef enum { //CM1 DPLL Settings Update
301  eCMI_DLPP_UPDATE_CORE,
302  eCMI_DLPP_UPDATE_MPU,
303  eCMI_DLPP_UPDATE_IVA,
304  eCMI_DLPP_UPDATE_ABE,
305  eCMI_DLPP_UPDATE_DDRPHY,
307  //CM2 DLPP Settings Update
308  eCMI_DLPP_UPDATE_PER,
309  eCMI_DLPP_UPDATE_USB,
310  eCMI_DLPP_UPDATE_UNIPRO
312  }eCMI_DPLLSrc;
313 
314 #ifndef _DOXYGEN_IGNORE
315 extern const char * pCMI_DataClassStr[];
316 
317 #define eCM1_CDSC_firstElement eCMI_CDSC_MPU_DPLL
318 #define eCM1_CDSC_lastElement eCMI_CDSC_L4_ALWON_ICLK
319 #define eCM2_CDSC_firstElement eCMI_CDSC_L3_1
320 #define eCM2_CDSC_lastElement eCMI_CDSC_UNIPRO_DPLL
321 
322 extern const char * pCMI_ClkDomainStr[];
323 
324 #define eCM1_DLPPSRC_firstElement eCMI_DLPP_UPDATE_CORE
325 #define eCM1_DLPPSRC_lastElement eCMI_DLPP_UPDATE_DDRPHY
326 #define eCM2_DLPPSRC_firstElement eCMI_DLPP_UPDATE_PER
327 #define eCM2_DLPPSRC_lastElement eCMI_DLPP_UPDATE_UNIPRO
328 
329 extern const char * pCMI_DLPPSrcStr[];
330 
331 #define eCM1_CDRC_firstElement eCMI_CDRC_CLKSEL_OPP
332 #define eCM1_CDRC_lastElement eCMI_CDRC_ABE_AESS
333 #define eCM2_CDRC_firstElement eCMI_CDRC_SCALE_FCLK
334 #define eCM2_CDRC_lastElement eCMI_CDRC_GFX_PER_192M
335 
336 extern const char * pCMI_DivRatioStr[];
337 
338 #define eCM1_CSSC_firstElement eCMI_CSS_CORE_L4
339 #define eCM1_CSSC_lastElement eCMI_CSS_DPLL_CORE
340 #define eCM2_CSSC_firstElement eCMI_CSS_DUCATI_ISS_ROOT
341 #define eCM2_CSSC_lastElement eCMI_CSS_HSI
342 
343 extern const char * pCMI_ClkSelectStr[];
344 
345 extern const char * pCMI_ClkStateStr[];
346 extern const char * pCMI_DivRatioStateStr[];
347 #endif
348 
349 #endif // End of #ifdef _CMI
350 #endif // End of #ifndef __PMI_CMI_OMAP4430_H
Definition: PCMI_Omap4430.h:121
ePMI_LPD_StateChange
Definition: PCMI_Omap4430.h:81
ePMI_LPD_PwrState
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ePMI_MVD_OPP
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ePMI_MVD_PwrState
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ePMI_MPD_StateChange
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ePMI_LVD_OPP
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ePMI_DataClass
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ePMI_MPD_PwrState
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